CTS

1. what is global skew and local skew?

2. what are NDR rules?

3. what is insertion delay?

4. Cts Exceptions:
5. by default tool optimize global skew or local skew?

6. How do you build the clock tree?

7. In which corner tool will build clk tree ?

8. For better timing, how the target skew should be min or max?

For Better timing the target skew and latency should give min.
9. What was your latency in your projects?

As per design

10. What is your skew? How you reduced the skew if get violated . how you optimize the
skew?

Target Latency: 250ps

Target Skew: 35ps

Experiments
1) Enabling Global routing for timing and skew optimization.

Default : set_app_options –name cts.compile.enable_global_route –value false

Exp1 : set_app_options –name cts.compile.enable_global_route –value true

Global routing is used for the first step of the actual wire implementation. Tries to avoid
global congestion. It takes longer time for optimization but has accurate timing results.

So the advantage of a global router is that we have accurate timing results and the
optimization is done based on the estimation of the routability and congestion in the design.
 The total power consumed by the clk buffer and inverter in the whole design is
increased by 0.7mw and 0.3mw respectively. If we have relaxation for clock buffer
count and power then this switch is useful to reduce timing violations.

2) Concurrent clock and data optimization(CCD)

set_app_options -name clock_opt.flow.enable_ccd -value true

This app option performs clock concurrent and data (CCD) optimization when it is set to
true. In clock concurrent optimization technique, it optimizes both data and clock path
concurrently.

When this option is set to true, At clock_opt stage the CCD optimization is performed.

This attribute also performs area and power optimization at clock_opt stage.

CCD is applying useful skew techniques during datapath optimization to improve the
timing QoR. To solve the setup violation, tool is adjusting the launch and capture path in
such a way that the launch clock path plus data path delay is reduced and capture path
delay is increased. The overall clock buffer and inverter count is less than the default
experiment. Hence the power consumption and area is reduced.

3) Appling NDR
Default : set_app_options –name clock_opt.flow.optimize_ndr –value false

Exp : set_app_options -name clock_opt.flow.optimize_ndr -value true

Tool applies non-default-routing rules on long timing critical nets during clock_opt
optimization to improve timing, by applying NDR on timing critical nets the width of the net
increases due to which resistance in the nets decreases which results in a decrease in net
delay.

4) Enabling Area Recovery

set_app_options -name clock_opt.flow.enable_clock_power_recovery -value area

The clock_opt first tries to fix timing violations and then it optimises the area if the
margin is available. After optimizing timing the setup margin for area recovery is not
sufficient so area optimization didn’t take place. So for performing area recovery timing
margin is required.
6) Disabling Path groups for optimization if margin is available
set_app_options -name ccd.skip_path_groups -value {reg2mem mem2reg}

set_app_options -name clock_opt.flow.enable_ccd -value true

This app option skips the path groups which are mentioned in the list. We can skip those path
groups which are not timing critical. So the tool can put most of its effort on those path which
are timing critical

7) Hold Fixing
set_app_options -name ccd.hold_control_effort -value high

set_app_options -name clock_opt.enable_ccd -value true

11. How will you fix the timing violation in CTS stage?
12. you are seeing huge timing violations in cts, how you fix that?

13. What checks you performed before cts and after cts?

Before CTS we need to check:

1. All cells should be legalized.
2. All power nets are prerouted.
3. All pins should be legalized.
4. Congestion, timing should be in control.

After CTS we need to check:

14. Did you face a clock gating violation after cts?
15. Why will we use clock gating cells in design?

16. Why we need to maintance the minimum latency?

Ans. As clk is high transition signal, cells on clk path consumes more power. So if
number of clk cells reduces, power consumption also can be reduced. That is why we
need to minimize insertion delay

17. In which report you will find the latency of the block?

As per project.

18. What are the reasons for high skew in your design?

In log file need to check first below reasons,

1. The net has don’t touch attribute.

2. If the instance/Pin don’t touch attribute.
3. If any exceptions are missing.
4. Congestion in cts according to NDRs.
5. Flops will be soft fixed otherwise crisscross connection.

19. What is your analysis if skew and insertion delay are violating & How you will fix?
Same as ans 18.

20. what are the uncertainty factors and explain about each factor?

It is used to tight the constraints. It is the extra margin added in the design for future
use. It contains: Net delay, Skew, Ocv, Jitter, Crosstalk, tool margin.
21. What is meant by clock pull and push? useful skew method with diagram?

22. What are the factors we need to consider while pushing/pulling the clock?

Adding buffer, removal buffer and margins.

23. what is the slack for setup and hold?

As per design.

24. What is Cloning? What is ICG cloning? merging of the ICG?

25. clk gating path is violating in cts...given condition like, but in routing you should not
fix then will you fix it in cts or at the time of ecos?

26. What are the inputs required for cts?

INPUTS OF CTS:
1. SDC
2. SPEC FILE
3. Placement db
27. Which flavour cells you used in cts to build clock tree? What if we use high drive
strength cells?

We use clock inverters and clock buffers in the clock tree building. Sometimes we use only
clock inverters and not clock buffers. We also use clock gating cells in the clock tree. so we
have to provide the list of cells that we want to use in the clock tree.

set_ccopt_property inverter_cells {}
set_ccopt_property buffer_cells {}
set_ccopt_property clock_gating_cells {}
set_ccopt_property logic_cells {}

28. What is CTS and why we need to do CTS?

To distribute a clock from Clock port to Clock pin
Why CTS?
To minimize skew and insertion delay to build the clock tree

29. Is target skew, local skew or global skew?

Global skew
30. What is latency & types of latency?

31. Diff btn latency and insertion delay ?

32. What is clk grouping?

Clock Groups : set_clock_groups

There are three options to this command. `-asynchronous`, `-logically_exclusive` and `-

physically_exclusive`

Asynchronous Clocks

`set_clock_groups -asynchronous`

When you say two(or more) clocks are asynchronous, that means there is no phase

relationship between them at all.

Consider the following statements:

`create_clock -period 10 -name ClkA [get_ports CLKA]`

`create_clock -period 1- -name ClkB [get_ports CLKB]`

Here, ClkA and ClkB are two clocks to the design. They are defined on primary ports and are
asynchronous to each other. In such a case, we can specify
`set_clock_groups -asynchronous -group {ClkA} -group {ClkB}`

This is equivalent to setting the following two false path statements.

`set_false_path -from [get_clocks ClkA] -to [get_clocks ClkB]`

`set_false_path -from [get_clocks ClkB] -to [get_clocks ClkA]`

Logically Exclusive Clocks

Two clocks are said to be logically exclusive when they are both active in the design but

doesn’t have any paths between them. An example would be a MUX selecting two or more

of the clocks for a portion of the design using its select lines. Such clocks will not have any

timing path between them.

set_clock_groups -logically_exclusive -group [get_clocks Clk1] -group [get_clocks Clk2]`

Physically Exclusive Clocks

These clocks do not exist in the design at the same time. e.g. Clocks defined on the same

primary port but working in two different modes like the TestClk and Functional Clock.

There will be no SI interaction between these clocks.

`set_clock_groups -physically_exclusive -group [get_clocks TestClk] -group [get_clocks

SysClk]`

33. Is insertion delay, source latency or network latency?

Network latency.
34. What happens if we do not meet target skew?

If we do not meet target skew, timing will violate in further stages

35. What are drvs and what happens if drvs are violating?

DRV’S: Max tran, max cap, max fanout If drvs are violating cell delays cannot be trusted
because every cell is characterised with certain range of targets. So if these exceeds cell
delays cannot be trusted.

36. What is H-tree structure?

Algorithm steps for the H-Tree

 Find out all the flops present.
 Find out the center of all the flops.
 Trace clock port to center point.
 Now divide the core into two parts, trace both the parts and reach to each center.
 Then from this center, again divide the area into two and again trace till center at
both the end.
 Repeat this algorithm till the time we reach the flop clock pin.
37. What is multi point cts?

Implementing a Regular Multisource Clock Tree With an

H-Tree-Only Global Clock Tree Structure

MPCTS enable:

1. Create Tap drivers and assign sinks for Tap Drivers.

2. Build sub tree cts from Tap Drivers.
3. Build Global tree cts form clock root to Tap drivers.

38. What is virtual clock, generated clk?

create_clock [get_ports{clk}] –name pclk –period 10 –waveform {4 8}
create_generated_clock –name clk –source PLL –divided_by 2 [get_pins uff0/q]

39. Diff btn master clk and generated clk?

create_clock -name clk -period 2.22 -waveform {0 1.11} [get_ports clk]

We should provide the clock constraints to all the clk ports in the design.

create_generated_clock -multiply_by 2 -name ckGen2x -source clk [get_pins ckGen/U8/Z]

If there is any pins which has the source clk input we should create generated clk

40. Design with 0 skew, good or bad?

Good but in realtime its not possible because in a design all the flops are not triggered at
same time.
41. Consider 2 designs, one with less skew & more latency other design vice versa then
which one you will choose and why?

42. Runtime for cts?

Ans. As per Design.

SDC CONSTRAINTS:

❖ STATIC TIMING ANALYSIS (STA) is the best method for determining timing analysis, if the
circuit

meets the timing constraints without having to simulate.

❖ We should provide required timing constraints based on the design , the tool checks the
slack

violation using STA(static timing analysis).

create_clock -name clk -period 2.22 -waveform {0 1.11} [get_ports clk]

➢ We should provide the clock constraints to all the clk ports in the design.
create_generated_clock -multiply_by 2 -name ckGen2x -source clk [get_pins ckGen/U8/Z]

➢ If there is any pins which has the source clk input we should create generated clk
set_clock_uncertainty 0.4 [get_clock clk]

➢ We are setting 20% of clk period as clock uncertainty which is an ideal case. We took it as
the limit
for the possible deviation of the clk edge from its ideal location.

set_clock_latency -source 0.2 clk

➢ We are setting insertion delay from clock source to clock definition point as 10% of clock
period.

set_clock_latency 0.2 clk

➢ Similarly, we are setting insertion delay from clock port to clk sink point of sequential
elements as

10%.
set_input_delay 1.33 [all_inputs] -clock clk

➢ We are setting input delay as 60% of clk period for every register to input port paths.

set_output_delay 1.33 [all_outputs] -clock clk

➢ Similarly, we are setting output delay as 60% for every output port to register paths.

❖ For feed through paths the delay is considered as 30% ideal case, otherwise we get input
from full
chip level.
set x [filter [all_fanout -from [all_inputs]] "port_direction == out"]

➢ We are filtering out feed through paths from input to output and taking output ports as a
list.

set y [filter [all_fanin -to [all_outputs]] "port_direction == in"]

➢ We are filtering out feed through paths from output to input and taking input ports as a
list.

set_input_delay 0.77 [get_ports $y] -clock clk

➢ We are setting input delay as 35% for every register to input port paths.

set_output_delay 0.77 [get_ports $x] -clock clk

➢ We are setting output delay as 35% for every output port to register paths.

❖ We are creating four group paths and checking whether the timing constraints have been
met or
not.

group_path -name i2o -from [all_inputs] -to [all_outputs]

group_path -name i2r -from [all_inputs] -to [all_registers]

group_path -name r2r -from [all_registers] -to [all_registers]

group_path -name r2o -from [all_registers] -to [all_outputs]