Advanced Materials - 2018 - Garlapati - Printed Electronics Based on Inorganic Semiconductors From Processes and Materials

REVIEW
Printed Electronics www.advmat.de
Printed Electronics Based on Inorganic Semiconductors:

From Processes and Materials to Devices
Suresh Kumar Garlapati, Mitta Divya, Ben Breitung, Robert Kruk, Horst Hahn,
and Subho Dasgupta*
proposed and investigated, where one

Following the ever-expanding technological demands, printed electronics has can, in principle, obtain a controllable
shown palpable potential to create new and commercially viable technologies current/voltage output. However, the one
that will benefit from its unique characteristics, such as, large-area and wide that is mainly responsible for the com-
range of substrate compatibility, conformability and low-cost. Through the plete paradigm shift in computational
and communication technologies and in
last few decades, printed/solution-processed field-effect transistors (FETs) turn has brought a massive change in the
and circuits have witnessed immense research efforts, technological growth quality of human life is the device where
and increased commercial interests. Although printing of functional inks a solid-state insulator layer (commonly
comprising organic semiconductors has already been initiated in early 1990s, known as dielectric), sandwiched between
gradually the attention, at least partially, has been shifted to various forms the semiconductor and the gate electrode,
polarizes and controls the charge car-
of inorganic semiconductors, starting from metal chalcogenides, oxides,
rier concentration at the semiconductor
carbon nanotubes and very recently to graphene and other 2D semiconduc- interface. These devices, on account of
tors. In this review, the entire domain of printable inorganic semiconductors the critical components that have been
is considered. In fact, thanks to the continuous development of materials/ used to fabricate them, are known as
functional inks and novel design/printing strategies, the inorganic printed metal oxide semiconductor field-effect
semiconductor-based circuits today have reached an operation frequency transistors (MOSFETs). Functionally, the
FETs are interface-dominated electronic
up to several hundreds of kilohertz with only a few nanosecond time delays building blocks that may either be used to
at the individual FET/inverter levels; in this regard, often circuits based on amplify the output power or can function
hybrid material systems have been found to be advantageous. At the end, as an electronic switch.[1–3] The very high
a comparison of relative successes of various printable inorganic semicon- reliability and low power consumption of
ductor materials, the remaining challenges and the available future opportu- FETs have immediately led to the replace-
ment of vacuum tubes already in 1955;[4]
nities are summarized.
the first demonstration of an integrated
circuit (IC) combining multiple FETs took
place in 1958.[5] Since then, riding on
1. Introduction strong and continuous developments in fabrication and min-
iaturization technologies, the transistor integration density
The first successful demonstration of an all-solid-state elec- could follow the well-known Moore’s law where doubling the
tronic device in the late 1940s, where the flow of electrons number of FETs on a chip within every two years was predicted
between two metal electrodes was controlled by a small by Moore.[6,7] Interestingly, the number of transistors that are
potential applied to a third electrode (typically known as the manufactured today worldwide in a year are way more than
control or the gate electrode), was termed as transistor or the number of grains of rice which are harvested; naturally, the
field-effect transistor (FET). Later, various fundamental con- cost of a single transistor has also been reduced dramatically,
cepts and designs of such three-terminal devices have been in fact, it is at present less than a microdollar.[8]
Dr. S. K. Garlapati,[+] Dr. B. Breitung, Dr. R. Kruk, Prof. H. Hahn, M. Divya, Prof. S. Dasgupta
Prof. S. Dasgupta Department of Materials Engineering
Institute of Nanotechnology Indian Institute of Science
Karlsruhe Institute of Technology (KIT) Bangalore 560012, India
D-76344 Eggenstein-Leopoldshafen, Germany Prof. H. Hahn
E-mail: dasgupta@iisc.ac.in KIT-TUD Joint Research Laboratory Nanomaterials
The ORCID identification number(s) for the author(s) of this article Technische Universität Darmstadt (TUD)
can be found under https://doi.org/10.1002/adma.201707600. Institute of Materials Science
[+]Present Jovanka-Bontschits-Str. 2, 64287 Darmstadt, Germany
address: School of Chemistry, Faculty of Science and
Engineering, The University of Manchester, Manchester M13 9PL, UK
DOI: 10.1002/adma.201707600
Adv. Mater. 2018, 30, 1707600 1707600 (1 of 55) © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
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www.advancedsciencenews.com www.advmat.de
Although the first ever experimental demonstration of

a transistor had used germanium, soon it was replaced by Suresh Kumar Garlapati
silicon.[9] It will not be an exaggeration to claim that most of received his M. Tech. degree
these remarkable developments owing due to the outstanding from Indian Institute of
electronic and physical properties of Si, which is an intrinsic Technology, Madras, India
semiconductor, however, at the same time, can be doped as n- in 2011 and PhD in material
and p-type variant with nearly equal electron and hole mass and science from Technical
mobility, which is about >1000[10,11] and 200–300 cm2 V−1 s−1[12] University Darmstadt,
in the single-crystalline and polycrystalline form, respectively. Germany in 2016. From
In addition, Si is abundant in nature and therefore low cost, it 2011–2016, he was appointed
is easy to fabricate, stable, nontoxic, and more importantly it as a research associate at
forms an excellent interface with its naturally occurring oxide Institute of Nanotechnology
SiO2, which has served as the low-leakage gate insulator in (INT), Karlsruhe Institute of
every manufactured MOSFET for over four decades. Technology (KIT), Germany.
However, despite incredible advancements in Si technology, Presently he is working as a postdoctoral researcher in
it has certain critical limitations when it comes to either large- the University of Manchester. His areas of interest include
area or flexible electronic applications. On the one hand, large- printed electronics, oxide electronics, organic field-effect
area electronics with silicon may not be quite cost effective and transistors (OFETs), gas sensors, etc.
there are in fact no suitable fabrication technique for very large
area (meters to kilometers) fabrication of high-performance sil-
Horst Hahn is the
icon electronics; on the other hand, owing to its covalent nature,
Director of the Institute of
the band transport in silicon is by default strongly directional,
Nanotechnology at Karlsruhe
which results in a diminished mobility of only 0.5–1 cm2 V−1 s−1
Institute of Technology.
in its amorphous form.[13] Next, the mechanical properties of
Previously, he held positions
covalent silicon do not allow it to be considered for the so-called
at Argonne National
“flexible electronics” either. The term flexible or printable elec-
Laboratory, University of
tronics became particularly popular only after the invention
Illinois, Rutgers University
of conducting polymers in the late 1970s.[14] Organic mate-
and was full professor
rials are inherently flexible and stretchable; therefore, with
at TU Darmstadt from
improving performances of organic semiconductors in terms
1992 to 2004.
of carrier mobility (the early reports have shown mobility in
the range of 10−5 cm2 V−1 s−1 only) and air stability, an alternate
semiconductor industry with plastic electronics became seem-
ingly feasible. Till date, the bulk of the research efforts and any Subho Dasgupta is an
kind of industrial developments toward flexible and printed Assistant Professor at the
electronics have comprised organic semiconductors almost Department of Materials
exclusively.[15,16] Yet, over the years, it has been realized that the Engineering, Indian Institute
electronic transport properties, time, environmental, and elec- of Science (IISc), Bangalore,
trical stability of organic materials may not actually match the India. He received his PhD
inorganic semiconductors;[16–19] consequently, researchers have degree in Material Science
also started to consider novel and emerging inorganic alterna- from Technical University of
tives to silicon or innovative strategies to make silicon tech- Darmstadt (TUD), Germany
nology compatible to flexible/printable electronics. in 2009. Before joining IISc,
Solution-processed/printed electronics necessarily differenti- he worked as a group leader
ates itself from flexible electronics not only by the solution-based at Karlsruhe Institute of
synthesis constraints, but also by its targeted high-throughput Technology (KIT), Germany from 2012–2016. In 2013–2014
fabrication propositions and relevant application areas requiring he was a visiting scientist at Lawrence Livermore National
low-cost, high-volume electronic circuitry. However, most often Laboratory, USA. His research interests include printed
the printed electronic circuits would also need to be sufficiently oxide electronics, nanomagnetism, electrochemistry, Li-ion
flexible, sometimes only to survive the roll-to-roll processing batteries, electron transport in nanoporous materials, etc.
methods alone. The application areas that are in considera-
tion here include disposable, portable, and wearable electronics
at the first place, along with biosensors, low-end displays, etc. Here, in this review, we summarize the available solution-
However, in the long run, the technology may also become processing and printing techniques, and our scope is strictly
mature enough to be congruent with the Internet of Things limited to FETs, logics, circuits, and demonstrators that are
(IoT), where the aim is to connect everyday objects to the net- prepared using any of the solution-based methods. Moreover,
work to enable smarter performances and optimized processes. only high-performance devices based on inorganic semicon-
Figure 1 schematically represents various possible future appli- ductors are discussed here, for example, crystalline and amor-
cations of printed electronics. phous oxide semiconductors, various 1D, 2D carbon allotropes,
Figure 1. Application areas of printed electronics may include wearables, smart packaging, smart toys, e-textiles, display backplanes, biosensors,
Internet of Things, etc.
other emerging 2D semiconductors, solution-processed qτ m qλm

µin = = (1)
silicon, chalcogenides, etc., are considered and their perfor- m* 3kTm *
mance and suitability in future printed electronic circuits are
assessed. It has been noticed (especially, for inorganic semi- where q is the unit charge, k is the Boltzmann’s constant, and
conductors that usually provide inhomogeneous and rough T is the temperature. Based on this equation, for the same
film morphology when printed) that solution-processed novel, τm, in most cases, electrons show higher mobility (due to
high-k dielectrics offer superior device performance; conse- lower effective mass) than holes. Besides effective mass, scat-
quently, strengths and difficulties of various gating strategies tering phenomena also determine the carrier mobility; and
are compared. At the end of the review, present challenges and carriers can be scattered at defects (impurities, vacancies, and
future opportunities of inorganic semiconductors and devices grain boundaries), at phonons (vibrations due to light, sound,
that can be fabricated using various printing technologies are and temperatures), etc. The equation to calculate field-effect
discussed. mobility in the saturation regime (VDS ≥ VGS − VT) of a field-
Solution processing of inorganic semiconductors may actu- effect transistor can be given as[21]
ally be subdivided into two categories: one is where a pre-
cursor of the semiconductor material is printed, which typically I D,sat 2L
µFET = 2 (2)
requires a substantial postprocessing step, either in terms of WC (VG − VT )
thermal or photonic curing, or curing at specific environments,
etc.; and the other alternative is when the semiconductor mate- where ID,sat is the drain–source current in the saturation regime,
rial is dispersed in its final/usable form in the printable ink L is the length, W is the width, and C is the dielectric capacitance.
(for example, carbon nanotubes (CNTs), various exfoliated 2D However, it is important to note that the field-effect mobility is
semiconductors, oxide nanoparticles, etc.) and after printing a surface/interface phenomenon and its value is typically lower
provides a ready-to-use semiconductor layer. As it will unfold in than bulk or intrinsic mobility due to higher scattering effects
the following sections, the advantages and constraints of both at the semiconductor–dielectric interface.[20] Therefore, large (or
these approaches are considerably different. close to intrinsic) field-effect mobility values can only be achieved
Before proceeding to the methods and materials sections, by preparing defect-free semiconductor layers and creating
initially, we briefly discuss the most important figure of merit extremely conformal semiconductor–dielectric interfaces. It is
of a transistor, namely, field-effect mobility (µFET). The car- not surprising that both of these conditions are extremely chal-
rier mobility defines the ease with which carriers can move lenging when preparing FETs from solution-based techniques.
in a conductor/semiconductor and hence it is the parameter
that, among others, can be directly related to the maximum
operation frequency a device may attain. The bulk or intrinsic 2. Processing
mobility (µin) of a semiconductor material depends on the effec-
tive mass of its carriers (m*), their mean free time (τm), or the Since its inception printed electronics have exploited various
mean free path (λm) in the following manner[20] printing techniques to realize the active and passive components
Figure 2. Schematics showing most relevant solution-processing a–c) and printing techniques d–h): a) spin coating; b) spray coating; c) chemical bath
deposition; d) inkjet printing; e) aerosol-jet printing; f) electrohydrodynamic jet printing; g) gravure printing; and h) screen printing.
of electronic devices, among which some of the processes (e.g., tension–induced recoiling that competes with the centrifugal
spin coating, inkjet printing, etc.) have seen wider acceptance force. This effect can become negligible when the centrifugal
in the community than the others. In this section, all such solu- force becomes dominant by increasing the linear distance from
tion-processing techniques are discussed and critically com- the spinning center, achieved by placing the substrate off-center,
pared. The different processing prerequisites, necessary fluidic rather than at the center of the rotating chuck.[23] Though the
properties of the inks, limitations, and advantages that can dif- advantages of the spin-coating process include uniformity of
ferentiate each of the technique are summarized. films, reproducibility, low cost, etc., and the major drawbacks
Notably, whenever the articles have demonstrated working are large waste of inks/resources (as the bulk fraction of ink
transistor devices, primarily only the semiconductor layer has is thrown out of the stage), inability to cover uneven, complex
been solution processed/printed. Though there are occasional structures with 3D features, and most importantly, being a batch
examples of printed gate insulators/dielectrics, barring printed process the method cannot be scaled up as a large-throughput
CNT transistors, examples of all-printed devices (i.e., including technique. Often-encountered poor device performance and
the passive electrodes) have been particularly rare in the case reduced on-currents/mobility values owing to inhomogeneous
of inorganic semiconductor–based thin film transistors (TFTs). layer formation or the presence of pores and pinholes, etc., can
Consequently, it is evident that most of the techniques or probe resolved by spin coating of multistacked active layers as has
cesses that are discussed in this section are merited based on been followed by several research groups;[24–26] a multipass spin
the processed semiconductor layers only. Figure 2 shows sche- coating necessarily increases the homogeneity of the coated
matics of the most popular solution-processing and printing semiconductor layer, thereby improving the positive bias stress
techniques that are considered in this section. stability and the mobility of the TFTs. In contrast, Theissmann
et al.[27] have shown that optimal solution formulation can result
in highly homogeneous and defect-free thin films, even with
2.1. Solution-Processing Techniques film thickness as low as 7 nm; such ultralow thickness can help
to realize high on–off current ratio (≈106) and reach reasonable
Here, we discuss the solution-based processing techniques that device performance at very low annealing temperatures (125 °C).
are typically used to coat the entire substrate or a substantially
large part of it. In other words, following these methods, high-
resolution structuring at sub-millimeter level is generally not 2.1.2. Dip Coating
possible.
Dip coating is also a low-cost processing method, however, in
contrast to spin coating, and it is more efficient to coat irregular
2.1.1. Spin Coating and complex structures. The process involves immersion of a
substrate into the coating solution, and its subsequent removal
Spin coating is a widely used technique to obtain uniform with a controlled vertical speed. The equilibrium between the
thin films on various substrates. Here, a given liquid/solution viscous drag of the liquid, the gravitational forces, and the sur-
is spread over the entire substrate using high angular motion; face tension at the liquid meniscus adjacent to the moving sur-
the film morphology and thickness are defined by the balance face determines the film thickness. The film thickness can be
between the strong centrifugal force due to the rotation of the varied by the viscosity of the solution, the number of coating
stage (chuck) and the frictional force resulting from the vis- cycles, and also with the withdrawal speed; faster withdrawal
cosity of the fluid. Consequently, the electrical performance of generally leaves more liquid on the surface and increases the
TFTs can be altered by controlling the spinning speed or the thickness of the coating. In this regard, Pal et al.[28] have shown
viscosity of the solution.[22] The uniformity of the film is some- an increase in mobility (7.2 cm2 V−1 s−1) of zinc oxide (ZnO)
times disturbed by the formation of edge beads due to surface FETs with increasing film thickness achieved by multiple
coatings (up to eight coating cycles); here, with an increase in uniform and free from pinholes as the substrate is always in
the film thickness, actually the ZnO crystallite size increases contact with the solution.[33]
with the standard annealing routine, resulting in a fewer CBD can be compatible with glass substrates to produce
number of grain boundaries along the transistor channel, fully transparent electronics; it can easily produce thin films
which then contributes to the better performance and higher (≈10 nm)[34] at low temperatures; Redinger and Subramanian[34]
mobility. have also made use of an additional advantage of the CBD pro-
cess, by changing the surface properties of the substrate they
could grow ZnO thin films only at selective sites, thus allowing
2.1.3. Spray Coating structured deposition. In CBD, the bath temperature also plays
a major role; Subramanian et al.[35] fabricated ZnO transistors,
The process of spray coating is mainly used to coat nonplanar and investigated the effect of varying pH and deposition tem-
structures, such as steps, trenches, and stacks on semicon- peratures of the bath; interestingly, with a nominal increase in
ductor chips. In this case, an atomizer or nebulizer is used bath temperature from 50 to 70 °C, the precipitate formation
to create fine droplets from a low viscous coating solution, within the bath could be avoided, resulting in an increase in the
which are then carried into the coating chamber by a carrier mobility value from 0.2 to 1.6 cm2 V−1 s−1.
gas; owing to a combined effect of gravity and the applied
electrostatic field, the charged droplets are guided and finally
deposited onto the electrically grounded substrate. The quality 2.1.5. Bar Coating
of the coating depends on the size of the droplets, which
decreases with viscosity of the solution. It is one of the sim- Bar coating or wire bar coating is a simple, versatile, and scal-
plest and least expensive methods that uses a minimal quan- able process to produce high-quality ultrathin films. Here, a
tity of metal oxide precursor to grow thin films over a large thin metal wire is wound over a movable bar; when the bar
area; the other advantage of the process is easy doping and rolls over the substrate with ink droplets, the ink gets smeared
creation of multicomponent oxide films,[29] as one may easily by the wire, thereby providing a very thin (few nanometer
blend different precursor solutions prior to deposition. Adamo- thick) film. Various factors, such as solution rheology, surface
poulos et al.[30] have demonstrated the versatility of spray tension, bar-pulling rate, etc., may affect the uniformity and
coating by fabricating low voltage–operated ZnO TFTs with thickness of the films (e.g., the film thickness increases with
the subsequent deposition of ZnO semiconductor channel, an increase in the bar-pulling rate). Unlike the traditional spin-
as well as the high-k polycrystalline yttrium oxide (Y2O3) or coating process that leads to a substantial material loss, the bar
amorphous aluminum oxide (Al2O3) gate dielectrics, while coating is a high yield, low waste technique and requires very
maintaining a uniform thickness and low surface roughness little quantity of solution to cover a large substrate area.[36,37]
over large areas. Spray coating is also found to play a major Yoon et al. have compared the performance of spin-coated
role in the fabrication of silicon nanocrystal FETs,[31] by pro- and bar-coated aluminum oxide dielectric films for indium–
viding a proper control over thickness with multiple spray- gallium–zinc–oxide (IGZO) semiconductor channel FETs,[38]
coating cycles (here identical results are not possible with spin where the latter demonstrated a substantially superior elec-
coating as it leaves large agglomerates and uncovered areas) trical performance, for example a turn-on voltage of only 0 V,
and homogeneity in nanocrystalline thin films. Moreover, both as opposed to −1 V for the spin-coated TFTs. Likewise, Lee
thickness and homogeneity have been essential parameters et al. have reported bar coating as a technique to produce large
to study percolation effects and the hopping charge transport scale, highly dense, and ultrathin dielectric layers which have
mechanism. a smooth surface topography and a very high areal capacitance
(≈0.33–0.53 µF cm−2).[36] The TFT arrays processed by self-
patterned amorphous IGZO semiconductor layer on top of the
2.1.4. Chemical Bath Deposition (CBD) bar-coated AlOx dielectric resulted in a field-effect mobility of
6.0 cm2 V−1 s−1 at an operating voltage of only 2 V. Next, Hong
CBD is a partially scalable technique, which involves the et al.[37] could demonstrate cost effective, large-area coverage
immersion of the substrate in a solution of precursors, fol- in the case of poly(acrylic acid)-decorated multiwalled carbon
lowed by a heterogeneous surface reaction. The basic steps nanotube TFTs with minimal ink requirement, however, with
that are involved in this process are generation of ionic spe- uncompromised device mobility values up to 7.34 cm2 V−1 s−1.
cies, their transport through a medium, and finally ion–ion In Table 1, different solution-processing techniques have been
condensation of these species onto the substrate.[32] Thin films compared with respect to their characteristic features and
can be produced by having a proper control of precipitation of required ink properties.[39–55]
the required compounds through a series of reactions between
positive and negative ions to form neutral atoms. The thickness
and quality of the growing films depend on the duration of dep- 2.2. Printing Techniques
osition, type of the substrates, solution composition, and tem-
perature, thereby providing possibilities for either large-area 2.2.1. Jetting Type
batch processing or continuous deposition of thin films. CBD is
a relatively simple process, which offers superior quality, stable, Although controlled by distinct jetting events, these printing
uniform, and hard films; the thickness of the films remains techniques are similar in the sense that in every case the
Table 1. Comparison of characteristic features and ink properties of different solution- (with a thickness of the order of 35 nm) of
processing methods. indium–zinc–tin–oxide. At the next level,
Layani et al.[61] have printed interconnected
Method/feature Spin coating Dip coating Spray coating Chemical bath Bar coating coffee-ring patterns of metal nanoparticles,
deposition
which can be considered as an easy and
Ink viscosity [cP] 1–5200[39,40] 2–35[41] 0.1–10[42] – <100[36] straightforward approach to obtain a printed,
Film thickness [nm] ≥5[43] 10–2500[44,45] 10–600[46,47] 40–300[48,49] 6–40[36,38] large-area transparent conductor, where the
Film roughness [nm] 0.08[50] 15[51] 60[52] 4[53] 0.08 [36] interconnected coffee rings form tracks for
electrical conductance and the empty cen-
Coating speed – 0.01–15 mm 5–100 mm 6–1800 nm 10–90 mm
s−1[41,54] s−1[46,47] h−1[48,55] s−1[36,38] tral regions ensure high transparency of the
printed substrate.
Downscaling of device dimensions is one
prepared ink must pass through the printing nozzles (which of the major challenges in printed electronics. In this regard,
defines the allowable range of ink viscosity and particle/ using self-aligned inkjet printing, Noh et al.[62] have demon-
agglomerate size in the ink). Typically, they are noncontact strated inkjet-printed TFTs with channel lengths down to 100–
processes, thereby generating least contaminations, which is 400 nm and observed a maximum cutoff frequency of 1.6 GHz;
actually ideal for printing of electronic components. The digital taking it a step further, very recently, Grubb et al.[63] have fab-
nature of these printing techniques ensures easy selection and ricated inkjet-printed CNT-based FETs, with a channel length
change of print patterns, which makes them highly popular ranging from 300 nm to 2 µm, following identical self-align-
among researchers working on printed electronics. ment of the printed electrode material. Here, they observed
Inkjet Printing: Essentially a print head and an ink reser- an on/off current ratio of 106 and exceptionally fast switching
voir comprise a generic inkjet printer. Typically, the print head capabilities with a cutoff frequency up to 18.21 GHz (Figure 3).
has nozzles of micrometer size through which the ink fluid is Aerosol-Jet Printing: Aerosol-jet printing uses either a
ejected;[56] the ejection can be continuous or drop-on-demand pneumatic or an ultrasonic aerosol generator to produce an
type. Based on the driving force behind the fluid ejection, intermediate material state before film formation, known as
inkjet printing can be subdivided into thermal and piezoelectric aerosol, which is in fact a colloid of solid particles or liquid
inkjet printing. The major parameters that can control effective droplets in a gas. The pressure built-up in the atomizer, with
printability are formulation of the ink, which includes its fluid the help of a carrier gas, ensures the ejection of aerosolized par-
dynamic properties, substrate/nozzle temperatures, nozzle ticles toward a target substrate by aerodynamic focusing. The
diameter, etc. The higher the nozzle diameter, the easier the high-velocity particle stream, assisted by a sheath gas (which
printing experience is (especially true for colloidal and particu- shields the aerosol particles from the inner walls of nozzles
late inks), however, at the expense of a lower printing resolu- of a print head), remains focused during its travel to the sub-
tion. One of the major problems associated with inkjet printing strate, thus ensuring high-resolution features down to <5 µm
is the tendency to form the so-called “coffee-ring” patterns, and at the same time scalability to support high-volume pro-
where contrary to homogeneous film formation, the bulk of ductions. Aerosol-jet printing may also be suitable for micro/
the printed materials eventually end up forming a ring-shaped nanoparticle-based inks, as it ejects very small droplets of about
pattern upon drying. One way to minimize “coffee-ring” effects 0.0001–0.0005 pL in volume; these droplets contain only a few
is to maintain a high substrate temperature so that the solvent nanoparticles, and the remaining solution evaporates in short
can evaporate before it can actually hydrodynamically spread to time, thus eliminating the possibility of coffee-ring formation,
form the coffee ring. In addition, the coffee-ring effect may also which is often the limitation in inkjet printing technology.[64]
be counterbalanced by inducing a Marangoni flow (surface ten- Though the nozzle clogging problem is also present in aerosol-
sion gradient driven flow) by the addition of a minor solvent jet printing of nanoparticulate inks, especially at high particle
having high boiling point and low surface tension as compared loading, however, an adjustment in the solid phase leads to suc-
to the major/main solvent; this minor solvent addition retards cessful printing, as has been demonstrated for nanoparticulate
the evaporation at the contact edge and diminishes coffee-ring silver inks in many occasions.[65–67] Owing to its versatility of
effect.[57] Likewise, another effective approach to minimize printing different functional inks, Cao et al.[68] could fabricate
the coffee-ring effect can be the use of a surfactants such as completely hysteresis-free, all aerosol jet–printed, carbon nano-
polyethylene glycol (PEG) or sodium dodecyl sulfate, i.e., a vis- tube TFTs by making both the metallic and dielectric ink fully
cous polymer solution, which yields a uniform multiring pat- compatible with this printing technique. Similarly, complete
tern over a droplet area due to the repeated pinning-depinning aerosol jet–printed p- and n-type electrolyte-gated FETs (with
effect (which directly affects the motion of the contact line) low operating voltage and high electron and hole mobility) have
during the evaporation.[58] Contrary to the above discussion, been reported by Hong et al.[69] using different electrode mate-
Liang et al.[59] have shown that coffee-ring effect can actually be rials with their own respective advantages.
beneficial for TFT fabrication, as they have obtained thin, uni- Electrohydrodynamic (EHD) Jet Printing: Limited printing res-
form, and smooth ZnO active layers at the central region of the olution, droplet deviation, and unwanted flow of large volume
“coffee ring” which when used as the active channel resulted in of printed inks on the receiving substrate are the major draw-
a high device performance. Likewise, Avis et al.[60] have adopted backs for both thermal and piezoelectric inkjet printing; these
the same strategy of using the central part of the coffee ring shortcomings have actually driven the development of high-
to obtain a pore-free and homogeneous amorphous thin film resolution electrohydrodynamic jet printing that can produce
Figure 3. a) Frequency of transition ( fT) of different organic semiconductors printed with conventional printing versus the self-aligned printing tech-
nique. Reproduced with permission.[62] Copyright 2007, Nature Publishing Group; b) similar strategy when followed for CNT transistors, resulted in a
cutoff frequency of ft of 18.21 GHz. Reproduced with permission.[63] Copyright 2017, Nature Publishing Group.
sub-micrometer-sized features. In this case, the ink is supplied technologies, as any change in the given pattern will require
by a syringe pump to the nozzle, which is in fact a capillary creation of a new engraved cylinder and would lead to high-
glass tube coated with metal films in order to ensure conduc- cost investments. The factors that affect the printing process,
tivity. Here, an electrohydrodynamic flow is created by applying in this case, can be physical (viscosity and wettability of inks)
an electric field between the conducting support substrate and mechanical (printing speed and impression force).[74] On
and the nozzle; the potential applied between the substrate the other hand, gravure can handle inks with larger particle
and the nozzle is altered to control the jetting frequency and size (in micrometer range) and higher viscosity as compared
the droplet diameter in the printing process, thus resulting in to the jetting techniques, e.g., inkjet; in addition, with opti-
either a series of droplets of controlled ink volume or a con- mized impression force, the quality of films, their thickness,
tinuous stream of ink getting ejected from the nozzles.[70] and morphological homogeneity can be quite high, typically
Consequently, the EHD jet printing process offers superior superior to inkjet. Moreover, the best attainable printing reso-
control over the size of droplets or pixels, thus enabling high- lution in this case can be about 5 µm, again superior to that of
quality, high-resolution patterns. A minimal printing feature inkjet technology.
size of 0.1 µm and a narrowest line width down to <1.5 µm Flexography: Flexography is another replication-type printing
have already been demonstrated.[71] However, on the downside, method, which is less expensive than gravure and highly suit-
the EHD printing process is rather slow and not suitable for able for printing on polymers or papers, used in packaging
ultralarge-area printing. industry. In this case, just opposite to gravure, the ink is placed
onto the printing plates (made out of flexible polymers), where
the printing plates or image areas are raised as compared to the
2.2.2. Replication Type nonimage areas. As a result, the inks that are used in flexog-
raphy are less viscous than gravure (however, viscosity is more
Jetting-type printing techniques, such as inkjet or aerosol- than inkjet printing).[56] The readers may refer to the article by
jet printing, are advantageous as they are digital techniques Leppäniemi et al. for a detailed schematic illustration of the
and generate no additional cost when printing patterns are process.[75] When compared with other replication-type printing
modified; however, they typically suffer from rather low scal- techniques, flexography requires very small contact pressure,
ability/throughput. In this sense, the roll-to-roll printing pro- which allows transfer of ink from the printing plates to the
cesses, such as gravure, flexography, and screen printing, have substrate.[76] As one of the first reports, recently, Leppäniemi
a leading edge in terms of high-throughput production. et al.[75] have shown flexography-printed indium oxide (In2O3)
Gravure Printing: Similar to engraving, gravure printing TFTs on flexible polyimide substrates, obtaining very thin
(also known as rotogravure printing) belongs to the intaglio (<20 nm) continuous nanocrystalline semiconductor layers.
printing category,[56] which has the ability to produce high- Superior film morphology and thickness control have been
resolution patterns with very high throughput, at the same achieved with low viscosity and low solid content in the pre-
time. In gravure printing, a metal cylinder, having recesses cursor ink; with multiple layers of flexographic printing, device
on it, gets filled with ink at the valleys and the same ink is mobility as high as 8 cm2 V−1 s−1 has been achieved.
transferred to the substrate, which is placed in between the Screen Printing: The process of screen printing involves the
inked cylinder and the impression roller (supplies the neces- use of a mesh to transfer inks onto the receiving substrate. It
sary force for the transfer of the ink to the substrate); a blade can be extremely versatile in terms of choice of substrates and
is provided after the substrate to remove any excess ink. A also ink formulation over a large viscosity range. This tech-
detailed schematic of the process can be found elsewhere.[72,73] nique is also most inexpensive (uses low-cost fabric or stainless
This process is rather suitable for industries or for mature steel masks) among all the replication-type printing techniques;
in addition, it may be possible to print multilayer structures by transfer printing, have shown extremely high mobility values
by proper mask alignment.[77,78] Given the above-mentioned (1300 cm2 V−1 s−1, on glass substrates). For large-area graphene-
advantages, Cao et al. have reported, for the first time, a based integrated circuits, a typical way to provide graphene-
fully screen printed single-wall CNT-array TFTs on rigid (Si on-demand is by cut-and-pick (cut and exfoliate high-quality
wafers) as well as flexible (polyethylene terephthalate, PET) graphene from graphite) transfer printing, which has been
substrates[77] and later the same group has also reported fully introduced by Liang et al.,[85] where instead of placing graphene
screen printed active matrix electrochromic displays with CNT- all over the substrate, it has been selectively transferred onto
array TFTs.[78] the active area of each device. The graphene-based FETs thus
Reverse Offset Printing: Reverse offset printing is a method, fabricated have demonstrated a hole and an electron mobility of
which offers highest precision among the available printing 3735 and 795 cm2 V−1 s−1, respectively. Likewise, in an identical
technologies, making use of specialized low-viscous inks and approach proposed by Rogers and co-workers (later followed
a silicone (usually polydimethylsiloxane (PDMS)) repellant by other researchers), the so-called microstructured Si flakes
blanket. A cliché patterned with required line and space pat- (single crystalline) have been transfer printed onto receiver sub-
terns acts as a base onto which comes a blanket where the strates in order to obtain mobility value up to 500 cm2 V−1 s−1
ink is deposited all over the surface. Next, the blanket is made and maximum oscillation frequency of ring oscillators as high
to roll over the cliché with an optimum pressure to obtain an as 7.8 GHz.[86–94] The characteristic features and ink properties
impression of the line/space patterns on the blanket, which necessary for all the jetting and replication-type printing tech-
can then be transferred on the required substrate.[79] The pro- niques that are discussed above have now been summarized in
cess can be termed as a type of subtractive transfer printing; Table 2.[95–127]
the blanket absorbs the solvents of ink, thereby making it
easier to transfer a semidried film onto the substrate without
much spreading. Several factors that affect the printing 3. Semiconductor Materials
method are ink-cliché adhesion, ink-blanket adhesion, con-
tact angle between the cliché and blanket, ink cohesion and 3.1. Oxides
its rheological properties, etc. Reverse offset printing has been
successfully adopted by Han et al.[80] to print photolithography- 3.1.1. Crystalline Oxides
free copper (Cu) source/drain electrodes for solution-pro-
cessed ZTO-based FETs; the authors of this article have also In ionic metal oxides, oxygen accepts ns and (n − 1)d electrons
provided a detailed schematic illustration of the process.[80] of the metal atoms into its 2p-electron shell to form closed shell
In reverse offset printing, there is always a possibility of gen- configuration. Therefore, when stoichiometric, i.e., all oxygen
erating contact defects when the blanket reaches the bottom atoms have O2−, the metal oxides should typically be insu-
depths of the cliché and where the pattern is wide or shallow lating, which is the case for Al2O3 or TiO2. However, some of
enough. This can be avoided by following a “push–pull” pro- the oxides are nonstoichiometric by their very nature, as they
cess suggested by Kusaka et al.,[81] where a negative printing possess oxygen vacancies or extra interstitial metal atoms.
pressure is applied by pushing the blanket roller to make a con- These oxides (ZnO, In2O3, and SnO2), when nonstoichiometric
tact with the cliché, and then the roller is pulled back to prevent (here having oxygen vacancies), have valence electrons that are
any blanket indentation into the grooves of the cliché. loosely bound with the respective metal atoms and thus can
easily be ionized and act as donors. Interestingly, the concentra-
tion of such donors can be quite high, resulting in a large car-
2.2.3. Dry Transfer Printing rier concentration (>1019 cm−3 for In2O3 and 1018–1019 cm−3 for
SnO2),[128,129] however, at the same time with >100 cm2 V−1 s−1
Dry transfer printing differentiates itself from all the previ- carrier mobility,[130] thereby making them one of the ideal
ously mentioned liquid ink–based direct printing techniques in semiconductor materials of choice for modern-day alternative,
the manner that it can transfer/print structures for which ink nonsilicon, electronics. Likewise, nonstoichiometric excess
formulation can be difficult, for example, aligned nanowires, oxygen or cation deficiency in Cu2O makes it a hole conducting
whiskers, flakes, etc. It uses the principle of surface adhesion p-type semiconductor. There are dedicated review articles
force and transfers materials based on difference in adhesion based on oxide semiconductors and devices that can be found
between the donor and the receiver substrates.[56] Transfer elsewhere.[19,131–136]
printing can provide high-quality complex patterns, and as pre- In this present section, we would discuss the binary electron
viously mentioned, it is best suited for the fabrication of large- and hole conducting oxides which are predominantly crystal-
area nanowire FETs, where the single-crystalline nanowires are line; however, they may also be amorphous, at least partially,
transferred with controlled orientation and density.[82,83] Ori- when the solution-processed films are annealed at consider-
ented nanowires can be achieved by sliding the donor substrate ably low temperatures. Nonetheless, such examples would be
with the nanowires, against the receiver substrate, where the consciously avoided here and only be considered in the next
van der Waals interactions of the receiver surface transfer the section.
nanowires, in aligned conditions, in the direction of sliding. A n-Type Oxides—Zinc Oxide (ZnO): ZnO is a well-known
report published by Ishikawa et al.[84] used dry transfer printing wide bandgap (3.3 eV) n-type oxide semiconductor due to
to fabricate single-wall CNT TFTs for high-performance trans- its tendency to form oxygen vacancies and/or zinc intersti-
parent electronics. The single-wall nanotube transistors, aligned tials.[137] Some authors have also suggested that unintentional
Table 2. Comparison of characteristic features and ink properties used in different printing techniques.
Method/feature Inkjet Aerosol jet Electrohydro Gravure Flexography Screen Reverse offset Dry transfer
dynamic jet
Printing form Digital, Digital, direct Digital, electric Engraved cylinder Printing plates Mesh blocked Ink blanket on Difference in
Piezocontrolled writing using an field driven ink with ink filled in with a pattern with stencils cylinder rolled on surfaces tension
aerosol spray printing the cells rolled on wrapped around transfers ink onto cliche of substrates
a substrate a cylinder, rolled substrate used to transfer
over a substrate ink
Resolution [µm] 2[95] 10[96] 2[97] 2[73,98] 1[99] 100[100] 1[101] 2 µm[102]
Ink viscosity [cP] 1–30[103,104] 1–1000[96,105] 1–10 000[106,107] 100–12 000[72,98] 2–500[75,76] 30–12 000[108,109] 1.5–70[80,110] 150–500[102]
Substrate Polymer, plastic, Polymer, plastic, Plastic Plastic, paper Polymer, plastic Polymer, paper, Plastic Plastic, glass,
glass, paper, textile glass plastic, glass polymer
Film thickness 100–500[95,103] 30–150[105,111] 20–180[97,107] 10–400[72,112] 5–50[75,99] 14 000–25 000[109,113] 90–400[101,114] 1000–2000[102,115]
[nm]
Line width [µm] 2–8[116] 10[96] 2[97,107] 35[72] 3[99] 40[113] 2[110] 3.2[102]
[117] [118] [117] [117] [117]
Throughput Low–medium Low Low High Medium–high Medium–high Medium –
[m2 s−1]a)
Printing speed 1.25–7000[95,119] 0.1–10[96,120] 0.2–8[107,121] 5–1000[98,122] 200–830[75,99] 50–300[77,100] 0.8–200[101,123] 3–13[82]
[mm s−1]
Alignment ±2[124] 1–2[120] ±1[107] ±10[125] ±10[126] ±10[127] 1–2[123]
accuracy [µm]
Low (<0.01 m2 s−1); medium (0.01–1 m2 s−1); high (>1 m2 s−1).

a)
incorporation of hydrogen (which acts as a donor) can be ZnO can easily be prepared in different morphologies, such
responsible for n-type conductivity in ZnO; their argument as nanoparticles (NPs),[142] nanorods,[143] nanowires,[144] and
relies on the fact that hydrogen is abundant and difficult to be thin films (following precursor routes in the case of solution
removed from the crystal growth environment. It may form processing).[145–149] Among these, precursor routes have been
strong bond with oxygen, relaxing the crystal lattice and the widely popular owing to their simplicity and reproducibility
resulting O–H groups may be regarded as a new type of dopant coming from typical good film morphology; moreover, precur-
atom.[138] The most stable structure of ZnO, at ambient con- sors are also compatible to almost every solution-processing
ditions, is wurtzite, which is formed by two interpenetrating or printing techniques. However, on the downside precursor
hexagonal close-packed sublattices, where four atoms per unit routes usually require high process temperatures (200–500 °C),
cell are present in each sublattice. However, ZnO crystals have thereby, limit the choice of flexible substrates. In this regard,
deviation from ideal wurtzite structure due to different axis there is a specific advantage of certain Zn precursors over the
dimensions (e.g., c/a ratio). Interestingly, depending on the other oxide semiconductors as they can decompose at very low
concentration of oxygen vacancy, ZnO may either be nearly temperatures. For example, Lin et al. have reported extremely
insulating or semiconducting or even metallic. The highest low temperature–processed (80–180 °C) ZnO FETs using
charge carrier density of 10²¹ cm−3 has been reported for ZnO·xH2O, soluble in ammonium hydroxide, as the pre-
ZnO and a maximum Hall mobility of 300 cm2 V−1 s−1 (using cursor.[145] The spin-coated precursor films have been annealed
Monte Carlo simulations) has also been estimated (notably, so in different atmospheres, air, and N2; the films annealed in
far, a maximum mobility value of 205 cm2 V−1 s−1 can only be N2 have shown superior (by an order of magnitude higher
achieved experimentally for the single crystal ZnO grown by mobility) performance as compared to the air annealed ones;
a vapor-phase transport method[139]). ZnO plays a dual role in in this case, with solution-processed AlOx/ZrOx bilayer die-
the field of oxide semiconductors, both as a widely studied and lectric, device mobility as high as 11 cm2 V−1 s−1 has been
important n-type crystalline semiconductor material and as an reported. On the other hand, when ammine-hydroxo zinc
indispensable part in most of the well-known and well-charac- (Zn(OH)x(NH3)y(2−x)+) solutions have been used as the metal
terized amorphous oxides, such as In–Ga–Zn–O (IGZO), Zn– precursor inks, the 150 °C annealed devices have shown a
Sn–O (ZTO), In–Zn–O (IZO), etc. Although ZnO is originally mobility of 1.8 cm2 V−1 s−1.[146] It has also been observed that
an n-type semiconductor, several attempts have been made to the decomposition temperatures can be reduced by increasing
convert ZnO to a p-type variant, for example, by doping with the pH values, which lowers the energy barriers of conversion
different acceptor elements. Following such efforts, numerous of the hydroxo ligands of Zn precursors. In contrast, the acidic
publications have reported p-type ZnO FETs with a wide range precursor solutions consisting of hydrated zinc salts undergo
of semiconductor performances, however, later it has been several intermediate reactions and thereby require higher
realized that those devices are neither reliable nor reproduc- decomposition temperatures. In this regard, Moon and co-
ible.[140,141] Therefore, p-type ZnO FETs are not discussed fur- workers have demonstrated that the devices prepared with basic
ther in this review. pH solutions show FET performance with a device mobility of
0.42 cm2 V−1 s−1 at low process temperatures, down to 150 °C,
whereas the devices prepared with acidic solutions do not
show any transistor behavior unless they are annealed at least
at 400 °C or above.[148] Notably, low temperature–processed
oxide FETs have also been fabricated using microwave
annealing. For example, once again, Moon and co-workers have
prepared ZnO FETs following conventional thermal (on a hot
plate) and microwave annealing, and compared the perfor-
mance. The devices prepared at 140 °C for 30 min using micro-
wave annealing have shown superior performances (mobility
of 1.75 cm2 V−1 s−1) compared to the conventionally annealed
ones at the same temperature (0.32 cm2 V−1 s−1), due to better
crystallinity, lower concentration of residual hydroxyl groups,
higher oxygen vacancies, etc.[149]
On the other hand, reports suggest that an improvement in
FET performance may also be obtained by doping with suitable
elements (interstitial[29,150,151] or substitutional[152–154]) that can
improve crystallinity, charge carrier concentration, and may
also reduce defects. For example, Chang et al.[150] have prepared
undoped and fluorine (F)-doped ZnO FETs and found that the
device performance (µFET = 1.3 cm2 V−1 s−1 for undoped ZnO
FETs vs 2.6 cm2 V−1 s−1 for 10 mol% F-doped ZnO FETs) and
electrical bias stress stability have significantly improved with
F-doping. The F− ions can substitute oxygen atoms and may act
as donors, which naturally increases carrier concentration. Fur-
thermore, F− can occupy oxygen vacant sites and thus reduce
trap states, which in turn improves mobility and bias stress sta-
bility. Additional doping with alkali metal ions, such as Li, Na,
K, etc., are found to improve the FET performance even further.
The device mobility of Li-codoped F:ZnO FETs (6.9 cm2 V−1 s−1)
is found to be superior to the F:ZnO FETs. Here, Li improves
the crystallinity and acts as an interstitial dopant, generating
additional charge carriers and increasing both bias stress sta-
bility and lifetime. Adamopoulos et al.[29] have also studied the
effect of Li doping on ZnO FETs (Figure 4a,b) to conclude that
Li can act as interstitial dopants up to the Li:Zn molar ratio
of 1:1 and can increase the crystallite size, thereby improving
the device performance (mobility up to 54 cm2 V−1 s−1 has
been observed). On the other hand, at even higher concentra-
tion, Li may contribute as substitutional dopants and decrease
the crystallite size and so the performance. Later, the same
group has used solution-processed dielectric (ZrO2) for Li-
doped ZnO FETs (Figure 4c–f) (processed at 400 °C by a
spray pyrolysis technique) and found that mobility improved
significantly (85 cm2 V−1 s−1) compared to the undoped ones
(32 cm2 V−1 s−1).[151] The authors have inferred that the higher
performance with lithium doping can be related to an increase
in crystalline size. On the other hand, in contrast to the common
belief that a substitutional doping decreases the crystallite size,
an increase in performance has been observed by Park et al.[152]
for up to 5.4% Ga doping in ZnO, which the authors have
ZnO-FETs with ZrO2 gate dielectric; b) output characteristics of the same

device; c) linear (VD = 0.2 V) and saturated (VD = 3.5 V) transfer character-
istics of bottom-gate, top-contact Li-doped ZnO FETs with ZrO2 gate dielec-
tric; d) output characteristics of the same device. a–d) Reproduced with
permission.[151] Copyright 2011, Wiley. e) Linear (VD = 2 V) and saturated
(VD = 40 V) transfer characteristics of bottom-gate, top-contact ZnO FETs
Figure 4. ZnO transistor characteristics: a) linear (VD = 0.5 V) and satu- with optimum [Li+1]/[Zn+2] = 1% molar mass ratio; f) output characteristics
rated (VD = 3.5 V) transfer characteristics of bottom-gate, top-contact of the same TFT. e,f) Reproduced with permission.[29] Copyright 2010, Wiley.
explained in the light of flatter and smoother semiconductor believed that this unusually high device performance can be
surfaces, providing superior interfaces with the dielectric; the due to the electrolytic top gate geometry that may easily fill the
identical observation has also been reported for substitutional trap states at the semiconductor surface.
Al doping, where the device mobility increased for early addi- Interesting results have also been reported for zinc oxide
tion of a small amount of Al and later decreased because of where the processing/annealing procedures provide close con-
scattering events at the segregated Al-rich, resistive oxide trol over the device performance. For example, preferred ori-
phases along the grain boundaries.[153] It is also well known entation, as opposed to polycrystalline ZnO films, have been
that ZnO is highly photoconducting and electronically unstable obtained when the coated precursor films are entered directly
in ambient conditions; both these effects arise from large den- into the furnace at 500 °C as opposed to furnace heating, where
sity of surface defects and localized states within the bandgap. the temperature of the film gradually raised to 500 °C. Strik-
To resolve this particular issue, researchers have also explored ingly different device performance has been observed between
different doping strategies; the approach has been to stabilize the preferred orientation films (5.25 cm2 V−1 s−1) and the poly-
ZnO FET performance by doping with elements that can sup- crystalline ones (0.23 cm2 V−1 s−1).[162] The effect of substrates
press oxygen vacancies and trap states. Jun et al.[155] have made has been reported by Benlamri et al.[163] where the authors
such an attempt by doping ZnO with yttrium (Y), which has found that ZnO films grown on Si3N4 have better crystallinity
much higher affinity for oxygen than Zn. Although the observed (bigger grains, lower residual strain) and lower interface traps
mobility value slightly decreased (from 2.07 cm2 V−1 s−1 compared to the films on SiO2 substrates; the substrate effect
for undoped ZnO vs 1.81 cm2 V−1 s−1 for 1% Y-doped ZnO has been apparent with the performance difference observed
FETs) with the addition of this carrier suppressor, the negative between the respective devices (33 and 13 cm2 V−1 s−1).
bias stress stability has been found to improve significantly. In comparison with the precursor-derived ZnO FETs, the
In addition to suitable doping, novel high-k dielectrics[156–158] examples of transistors prepared from printed ZnO nano-
and electrolytic insulators[159–161] have also resulted in particles are rare; in fact, the obtained device performances
high-performance FETs at low operation voltages. Typically, are also rather poor. The advantage of using nanoparticle dis-
these devices have shown superior semiconductor–dielec- persion rests on the fact that the devices can be processed at
tric interface (resulting in low interface scattering effects) lower temperature on a wider range of substrates. Moreover,
and reduced trap states. There are various examples of solu- very high temperature annealed, highly crystalline, and elec-
tion-processed oxide dielectrics, for example, Yoon et al.[156] tronically superior primary nanoparticles can be chosen to
have compared polymeric and polymer/oxide composite form the nanoink. Nanoparticulate-based ZnO FETs typically
dielectric in terms of their gating efficiency; while pure poly- require addition of various stabilizers in order to obtain stable
imide as the dielectric material resulted in a mobility value of nanoinks; however, in most cases these semi-insulating sta-
only 0.1 cm2 V−1 s−1 for Li:ZnO channel FETs, nearly 50-fold bilizer molecules have not been entirely removed at the later
increase in mobility value (4.9 cm2 V−1 s−1) has been observed processing stages, which compromised the device performance
for YOx/polyimide composite dielectric. In another publication, considerably. For example, Okamura et al.[164] have used com-
even higher performance has been observed for solution-pro- mercially available surfactants such as TEGO750, TEGO752
cessed (spray coated) HfO2 (40 cm2 V−1 s−1); in this case, the and poly (4-vinylphenol) (PVPh) and heated the devices only to
high performances has been related to semiconductor (ZnO)/ 150 °C, which is certainly not sufficient to remove the said sur-
dielectric (HfO2) superior lattice matching.[157] Later, the same factants; as a result, FET mobility of 10−5 to 10−3 cm2 V−1 s−1 has
group found another novel dielectric material in Nd2O3, which only been observed. Similarly, Halik and co-workers.[165] have
found to offer even closer lattice match to the basal plane of obtained a device mobility of 2.5 cm2 V−1 s−1 when 2-ethylhex-
hexagonal ZnO, and indeed a further improved device perfor- anoate and poly(vinylpyrrolidinone) (PVP) have been used as
mance (mobility of 65 cm2 V−1 s−1 and on/off ratio of 107) has the polymeric stabilizer and dielectric, respectively.
been recorded.[158] n-Type Oxides—Indium–Oxide (In2O3): In2O3 is another
High device mobility has also been reported for ZnO well-explored n-type semiconductor. It has cubic bixbyite struc-
FETs gated with electrolytic insulators, such as ionic liquids ture, in which two types of crystallographically nonequivalent
or ion gels. Although the devices reported by Frisbie and co- indium atoms (In1 and In2) and one type of oxygen atoms
workers[159] (ZnO FETs have been gated with ion gel (PS-PMMA- are present. The coordination number of both indium atoms
PS triblock copolymer and [EMIM] [TFSI] ionic liquid in ethyl is 6, and for the oxygen atoms, it is 4. The unit cell of In2O3
acetate)) have demonstrated a rather low mobility value of comprises 16 formula units, i.e., 80 atoms per unit cell.[166,167]
1.6 cm2 V−1 s−1, however, most likely this observation is only In2O3 has high bandgap (3.75 eV),[168] very high carrier con-
due to the inhomogeneous ZnO layer with voids that are side centration (1018–1020 cm−3),[169] and also high Hall mobility
effects of printing. In contrast, Bong et al.[160] have obtained a (270 cm2 V−1 s−1)[170] values. It becomes a degenerate semicon-
device mobility of 12.1 cm2 V−1 s−1 using an identical ion gel ductor when doped with Sn, which is known as indium–tin–
(based on gelation of poly(styrene-b-methylmethacrylate-b-sty- oxide (ITO). Given the above-mentioned attractive features,
rene) triblock copolymer in 1-butyl-3-methylimidazolium hex- many researchers have chosen In2O3 as the solution-processed/
afluorophosphate [BMIM] [PF6] ionic liquid). In this regard, printed semiconductor material for transistor applications.
ion gel–gated ZnO FETs with particularly high semiconductor Similar to solution-processed ZnO FETs, where most of
quality and device mobility has been reported by Zaumseil the reports describe the use of a suitable precursor solu-
and co-workers.[161] Here, they used cellulose-based ion gels tion, followed by an annealing step at elevated temperatures,
and have obtained a device mobility of 75 cm2 V−1 s−1. It is In2O3 films may also be prepared from various indium salts
(e.g., chlorides, nitrates, acetates, etc.) dissolved in suitable In2O3 FETs (19.5 cm2 V−1 s−1).[179] Here, the improvement in
solvents (water, alcohols, etc.) with or without an addition of performance can also be attributed to the increase in In–O
a stabilizing agent. One important processing-related issue coordination and reduction of impurities (hydroxyl groups).
has been observed by several research groups that most of The advantage of high-k dielectrics or highly polarizable
the In-precursors actually yield films with a large fraction of electrolytes has again been apparent.[180–185] For example,
hydroxyl groups and/or less coordinated metal–oxygen–metal Kim et al.[180] have used a self-assembled nanodielectric (SAND)
(MOM) bonds; these hydroxyl groups actually behave as and obtained a mobility of 43.7 cm2 V−1 s−1 with an on/off
charge traps and can affect the electronic transport proper- ratio of 106; the obtained mobility value has been 60 times
ties and device performance quite adversely, where the per- higher than the SiO2 dielectric–based In2O3 devices prepared
formance deterioration includes poor bias stress stability as in the same study. High-performance In2O3 FETs have also
well.[171–173] It has been found that annealing of the precursor been reported using solution-processed AlOx dielectrics. AlOx
films in oxidizing conditions can reduce hydroxyl groups sig- films that have been annealed at 350 °C show the presence of
nificantly. For example, Han et al.[171] have reported the effect higher fraction of hydroxyl groups (Al–OH) compared to high-
of annealing atmosphere (air and O2/O3) on the performance temperature annealed layers. It has been proposed that Al–OH
of In2O3 FETs. The precursor films that are annealed in air groups at the interface oxidize indium oxide and improve the
have shown more hydroxyl groups and less coordinated mobility value significantly (127 cm2 V−1 s−1).[181] Likewise, Xu
indium sites, whereas the films that are annealed in O2/O3 et al. have also reported solution-processed Al2O3 dielectric and
have resulted in fully coordinated indium sites and accord- the effect of hydroxyl groups. The prepared devices (processed
ingly stable device performance. The mobility values of FETs at 250 °C) show a mobility value of 30 cm2 V−1 s−1, which is
that are prepared by annealing at 300 °C either in air or in found to decrease with an increase in the process tempera-
O2/O3 atmospheres have provided device mobility value of ture of the amorphous alumina due to the decomposition of
3.8 and 16.8 cm2 V−1 s−1, respectively. On the other hand, wet hydroxyl groups and formation of more AlO bonds. On the
(high relative humidity > 90%) annealing conditions have also other hand, the low temperature–processed amorphous alu-
shown similar effects. Kim et al.[172] demonstrated that wet mina–gated devices have shown frequency-dependent capaci-
annealing at 350 °C decreases hydroxyl groups and improves tance values, owing to the fact that the hydroxyl groups, in fact,
oxidation of annealed films, thereby also performance; a satu- behave as charge traps at higher frequencies.[183] Once again,
ration mobility of 8.7 cm2 V−1 s−1 has been obtained with wet ethylene glycol (EG) incorporated Al2O3 dielectric (processed
annealing, compared to only 3.5 cm2 V−1 s−1 for the dry one. at 250 °C) has been used along with spin-coated In2O3, and a
Alternatively, it has been shown that an addition of a suitable frequency-dependent capacitance and device performance have
oxidizing agent to the precursor solution may also provide been observed which further deteriorates at higher frequen-
similar effects. In this regard, Chen et al.[173] investigated the cies; the as-reported dc mobility value in this work has been
effect of an addition of HClO4 to the indium chloride pre- 46.2 cm2 V−1 s−1.[184]
cursors. The precursors with and without HClO4 have been High-capacitance electrolytes[185,186] have also been used for
annealed at identical temperature (250 °C) to conclude that the In2O3 FETs. The best device performance (µFET = 126 cm2 V−1 s−1)
devices from precursors involving HClO4 show better perfor- has been achieved for the FETs that are annealed at 400 °C; the
mances (including a mobility of 8.8 cm2 V−1 s−1 and a superior formation of single-phase indium oxide with large crystallite
bias stress stability) as opposed to the devices without HClO4 size and conformal In2O3/solid polymer electrolyte interface
(µFET = 0.44 cm2 V−1 s−1). can be attributed to the high performance observed (Figure 5).
Once again, analogous to ZnO FETs, doping strategies have High process temperature is one of the major limitations for
also been adopted for In2O3 devices to tune electronic trans- oxide semiconductors, which can preclude their use alongside
port, carrier mobility, and device stability. Though both substi- inexpensive and flexible polymer substrates. In this regard, sev-
tutional[174–178] and interstitial[179] doping elements have been eral researchers have explored different processing methodolo-
considered, in contrast to ZnO channel FETs, the effect of gies that may lower the precursor decomposition as well as oxide
substitutional dopants has generally been found to be adverse phase formation temperatures;[187] accordingly processing tech-
for indium oxide films in terms of crystallinity, charge trans- niques, such as combustion synthesis,[188] photochemical acti-
port, and transistor performance. For example, an addition of vation method,[189] etc., have been proposed and explored. It has
Ga (10–40 at%) suppressed carriers, at the same time, deterio- been shown that indium nitrate dissolved in water can decom-
rated crystallinity of In2O3 films and so the device performance pose to amorphous indium oxide at lower temperatures, com-
(gradually from µFET = 3.1 to 0.35 cm2 V−1 s−1).[174] Likewise, pared to 2-methoxyethanol solution. FETs processed at 200 °C
gadolinium (Gd)[176] doping resulted in inferior crystallinity and show a device mobility of 2.62 cm2 V−1 s−1; at the next step, it
device mobility (15.9 cm2 V−1 s−1 for undoped In2O3 FETs vs has been found that vacuum annealing can enable working
9.7 cm2 V−1 s−1 for Gd-doped FETs). However, the positive bias In2O3 FETs (with a mobility value of 2.42 cm2 V−1 s−1) at process
stress stability is found to improve along with the reduction in temperature as low as 125 °C.[187] The vacuum annealing step
free carriers. On the other hand, interstitial doping is found supposedly removes the impurities and promotes condensation
to increase carrier concentration and carrier mobility without reaction to form indium oxide. Combustion synthesis is a
affecting the crystallinity. For example, Li-doped In2O3 FETs method for low temperature processing of oxide films, first
have shown significant improvement in performance; the In2O3 proposed by Kim et al. and demonstrated on In2O3 films and
film that has been doped with 13.5 mol% Li shows a mobility FETs.[188] Later on, the process became very popular for amor-
of 60 cm2 V−1 s−1, which is well above the mobility of undoped phous oxide layer processed at low temperatures, hence the
Figure 5. High-performance inkjet-printed In2O3 TFTs: a,b) transfer and output characteristics of typical In2O3 FETs with solid polymer electrolyte
gating, demonstrating mobility of 126 cm2 V−1 s−1. Reproduced with permission.[185] Copyright 2013, American Chemical Society. c) Transfer character-
istic curves of the In2O3 TFTs, fabricated with AlOx dielectric prepared at different temperatures and showing device mobility as high as 127 cm2 V−1 s−1.
Reproduced with permission.[181] Copyright 2013, AIP.
details of this method will be explained in the next (amorphous have also been reported, benefiting from a superior crystalline
oxides) section. Briefly speaking, the approach involves addi- order compared to the spin-coated films. The spray-coated FETs
tion of an oxidizer and a fuel to the metal precursor solution/ that are annealed at 252 °C have shown a device mobility of
ink in order to initiate exothermic reactions, while heating, and 40 cm2 V−1 s−1 which is found to be 8 times higher than for the
thus requiring low external thermal inputs (Figure 6a). In fact, identical spin-coated FETs, annealed at 300 °C.[46]
the precursor temperature may rise above the supplied tem- In line with the above discussions, the incentive for using
perature (temperature noted at the hotplate display), locally, nanoparticulate dispersions/inks becomes quite obvious; in
up to the required values that is necessary for the decomposi- this case, on the one hand, high-quality, high-temperature
tion of the precursor and the formation of the high-quality annealed and well-crystalline primary nanoparticles can be con-
oxide phase; the advantage here is that during the whole pro- sidered for the ink formulation; on the other hand, the process
cess the entire substrate is not exposed to any temperature that temperature can be lowered even down to room temperatures,
would be substantially higher than the supplied value. Using thereby making the processed FETs compatible to any polymer
combustion synthesis, Kim et al. could achieve a mobility of or cellulose substrates.[190–193] However, on the downside, a
0.81 and 3.37 cm2 V−1 s−1 with the hot plate temperatures set nanoparticulate film, processed via spin coating or printing of
at 200 and 250 °C, respectively. Next, indium oxide films pre- nanodispersions, may result in a highly porous form, thereby
pared by photochemical activation (use of high energy photons reducing the device performance.
to form oxides from precursors) method have resulted in a In fact, a highly porous film morphology has been obtained
mobility value of 3.6 cm2 V−1 s−1, where the maximum unin- when indium oxide nanodispersions have been stabilized
tentional temperature rise up to 150 °C is recorded during electrostatically (in order to avoid any postheating step that is
the treatment.[189] Utilizing spray-coating methods and the so- typically necessary to remove polymeric stabilizers); as a result,
called Leidenfrost effect (levitation of liquid droplets, on a hot the demonstration of a completely room temperature–pro-
surface, due to the formation of insulating layer between the cessed, printed oxide FETs has been possible; however, the FET
substrate and droplets) high-performance indium oxide FETs mobility value has only been 0.8 cm2 V−1 s−1.[190] Subsequently,
Baby et al.[191] have put forward an idea where
polymeric stabilizers can be used in the
nanoinks, thereby allowing higher particle
load in the inks (with a reasonable shelf life
of several months). The stabilizing ligands
can again be removed without requiring an
annealing step, following a process, which
the authors have termed as chemical curing.
In this approach, a certain concentration
of halide ions present in the nanoink can
remove the ligands from the oxide nano-
particles’ surface. Therefore, a noncritical
concentration of such halide ion additives,
Figure 6. Approaches adopted to reduce process temperature of FETs: a) schematic showing present in the ink, can safeguard necessary
the principle and advantages of combustion synthesis process over conventional annealing.
shelf life of the ink; on the other hand, when
Reproduced with permission.[188] Copyright 2011, Nature Publishing Group. b) Schematic rep-
resentation of chemically curing of nanoparticles to obtain spontaneous stabilizer removal and concentration reaches a critical value during
dense film formation during the ink drying process. Reproduced with permission.[191] Copyright the ink drying process, the ligand molecules
2015, American Chemical Society. get automatically removed (the process is
schematically shown in Figure 6b). Following this approach, a the nanowires channel FETs are not discussed in detail in the
mobility of 12.5 cm2 V−1 s−1 has been achieved for completely present review. Here, a comprehensive summary of processing
room temperature–processed In2O3 nanoparticle-based FETs. and performance parameters of solution processed/ printed
In an alternative approach by the same research group,[192] two n-type crystalline oxide TFTs are presented in Table 3.[216–225]
different photonic curing methods (UV–vis pulses and contin- p-Type Oxides: Fabrication of logic electronics demands com-
uous-wave UV laser) have been used to remove the same sta- plementary metal oxide semiconductor (CMOS) technology,
bilizer molecules and device mobility of 8 and 12 cm2 V−1 s−1, and thereby requires both n-type and p-type semiconductors.
respectively, have been achieved, once again at a very low sub- Although it is possible to prepare circuits using either only
strate temperature, not exceeding 60 °C. p- or n-type semiconductors, there are certain shortcomings
n-Type Oxides—Tin Dioxide (SnO2): SnO2 is another well- in such a practice, for example, high power consumption, low
investigated, n-type oxide semiconductor with a direct bandgap signal gain, low noise immunity, and in addition substantial
in the range of 3.5–3.7 eV. It forms in rutile structure with a design complexity.[226] In the previous section, we have dis-
tetragonal unit cell containing four oxygen and two tin atoms. cussed high-performance n-type oxide semiconductors; how-
The Hall mobility (at 300 K) of SnO2 is found to be quite high ever, unfortunately it is nontrivial to find an equally good p-type
(150–260 cm2 V−1 s−1).[129,194–196] On the other hand, analogous semiconducting oxide. In the case of oxide semiconductors,
to indium oxide, its position of Fermi level and carrier con- generally the valence band is formed by oxygen 2p orbitals with
centration (1018–1019)[129] brings it close to being a degen- high electronegativity; consequently, small band dispersion
erate-type semiconductor. Nevertheless, there are numerous and deep energy levels cause low hole mobility in oxides.[227]
examples where SnO2 has been used as a semiconducting Nonetheless, there are certain p-type oxides, in which the hole
channel material in FETs and logics; though most have used mobility is substantially higher than for amorphous silicon.
ultrahigh vacuum (UHV) processing techniques,[197,198] there Therefore, these p-type oxides can very well be used in circuit
are also countable examples of SnO2-based solution-processed fabrication and elsewhere, in diode-based devices, such as in
transistors.[199–202] solar cells. Examples of well-known p-type oxide semiconduc-
Similar to other n-type oxides, most of the reported solu- tors will include binary oxides, such as Cu2O, CuO, SnO, NiO,
tion-processed SnO2 FETs are derived from suitable Sn and delafossite oxides (e.g., CuMO2, M = trivalent cation), such
precursor followed by an annealing at high temperature. as CuAlO2, CuGaO2, CuInO2, etc. Among these, delafossites
Though Si/SiO2 back gate devices have shown lower device have high carrier concentration but lower mobility values;
mobility, a remarkable improvement in device performance in addition, they are typically not compatible with solution-
has been noticed for solution-processed high-k dielectric top processing/printing techniques due to very high process tem-
gate devices. For example, Zhang et al.[199] have used spray peratures (800–1200 °C).[228,229] Therefore, here we primarily
pyrolysis to prepare SnO2 FETs on the Si substrate. When focus on binary p-type oxides only.
the devices are cured at 450 °C, the obtained mobility has p-Type Oxides—Cuprous Oxide (Cu2O): Cu2O is arguably
only been 0.19 cm2 V−1 s−1, whereas at higher processing the best-known binary p-type oxide semiconductor with very
temperature (e.g., 550 °C) the SnO2 channel is found to be high intrinsic mobility, of the order of 100 cm2 V−1 s−1, and
highly conducting at zero gate and a significantly negative a large carrier diffusion length ranging up to several micro
threshold voltage of −18 V has been observed. In contrast, meters.[230,231] It possesses cuprite-type crystal structure, where
a solution-processed ZrO2 dielectric (processed at 500 °C) the oxygen atoms represent themselves in a body-centered
and top gate geometry have resulted in a strikingly different cubic (BCC) structure and the copper atoms form a tetrahedron
observation with a mobility value of 40 cm2 V−1 s−1. Here, around each oxygen atom. The p-type conductivity of Cu2O
the high mobility devices obtained using high-k dielectrics originates from the copper vacancies, which form an acceptor
can be related to filling of localized states, thereby leading level at 0.3 eV above the valence band; the bandgap of Cu2O
to a band-like transport.[200] Likewise, literature reports also is around 2.1 eV. The valence band of Cu2O is created by the
include examples where solution-processed Al2O3 (processed hybridized oxygen 2p and copper 3d orbitals; hence, unlike
at 450 °C) gated SnO2 FETs have shown a mobility as high as other p-type oxides, the holes are not so strongly localized in
96.4 cm2 V−1 s−1.[201] Cu2O.[232,233] It is a semiconductor well known for decades; in
Not only precursor-derived films but as an alternative SnO2 fact, it was under study and use in early solid-state devices even
nanobelts have also been utilized as semiconducting channel before the onset of silicon era;[234,235] presently, Cu2O is largely
material. Arnold et al.[202] have deposited SnO2 nanobelts by used in solar cell applications because of its high light absorp-
thermal evaporation of SnO2 powder and then dispersed them tion coefficient.[231,236]
in ethanol. The deposited nanobelts are then annealed at a very Cu2O FETs from spin-coated precursors have been reported
high temperature of 800 °C for about 2 h. The prepared devices by Kim et al.; the spin-coated films are first annealed at 400 °C
have shown a maximum mobility of 125 cm2 V−1 s−1. in N2, followed by annealing at 700 °C in different oxygen par-
Furthermore, there is a large number of reports available tial pressures. These special annealing routines supposedly
in the literature on SnO2 nanowire FETs from the group of control the film composition as well as the film morphology.
Lu,[203,204] Wan,[205–207] Ju,[208,209] and many others,[210–215] which The optimized devices, which are annealed at 0.05 mbar oxygen
are sometimes even partially solution processed or aligned using partial pressure, have shown a mobility value of 0.16 cm2 V−1 s−1
solution-based techniques. However, owing to the fact that the with an on/off ratio of 102.[237] Likewise, devices reported by Yu
progress in single nanowire or nanowire array FETs is yet not et al. have been annealed in vacuum at somewhat similar tem-
sufficient for them to be considered for large-area electronics, perature ranges (400–700 °C) and have shown identical device
Table 3. An overview of processing parameters and performance (field-effect mobility, on/off ratio, and subthreshold swing) of solution-processed/
printed n-type crystalline oxide semiconductor TFTs.
Semiconductor Dielectric Substrate Processing route Process Field-effect On/off ratio Subthreshold Year
temperature mobility swing [V per published
[°C] [cm2 V−1 s−1] decade]
Hf:ZnO SiO2 Si wafer Spin coating 400 4.2 2.5 × 106 0.95 2017[154]
450 19 2 × 106 0.95
ZnO Nd2O3 ITO-coated glass Spray coating 400 65 106–107 – 2017[158]
Al:ZnO SiO2 Si wafer Spin casting 120 >3 107 – 2016[153]
7
ZnO HfO2 Glass Spray coating 380 40 10 – 2015[157]
7
F:ZnO SiO2 Si wafer Spin coating 300 2.6 10 – 2015[150]
F:ZnO:Li 6.9 107
F:ZnO:Na 5 107
F:ZnO:K 4.6 107
Li:ZnO Polyimide ITO-coated glass Spin coating 300 0.1 1.1 × 105 2.8 2014[156]
Polyimide/YOx 4.9 7.2 × 106 2.3
ZnO Cellulose ion gel Si wafer Spray coating 400 60.5 104 – 2014[161]
ZnO SiO2 Glass Spin casting 180 11 103 0.10 2013[145]
PEN 160 4–5 >104 0.10
ZnO (electrolyte Ion gel Kapton film Aerosol-jet 250 1.6 2.2 × 105 0.081 2013[216]
gated) printing
ZnO NPs AlOx Si wafer Spin coating 100 0.38 7 × 103 – 2012[217]
Y-ZnO SiO2 Si wafer Spin coating 350 1.8 6.4 × 106 0.74 2011[155]
ZnO SiO2 Si wafer Spin casting 140 1.7 107 – 2011[149]
ZnO SiO2 Si wafer Spin coating 150 0.42 106 – 2011[148]
ZnO SiO2 Polyimide Spin coating 200 0.35 106 – 2010[147]
ZnO Ion gel Si wafer Spin coating 500 13.4 1.1 × 105 – 2010[160]
Si wafer 400 14.8 1.5 × 105
Polyimide 280 3.4 104
ZnO NPs SiO2 Si wafer Spin coating 150 8 × 10−3 – 2010[164]
Li:ZnO SiO2 Si wafer Spray pyrolysis 350 54 106 – 2010[29]
ZnONPs Poly-4-vinylphenol Glass Spin coating 100 2.5 106 – 2009[165]
6
ZnO SiO2 Si wafer Spin coating 300 3.1 10 – 2008[146]
Aluminum oxide 150 1.8 106
phosphate
Ga:ZnO SiNx Glass Spin coating 400 1.63 4.2 × 106 1.25 2008[152]
ZnO ATO Glass Spin coating 490 5.2 6.7 × 105 – 2008[218]
Drop coating 490 4.9 3.6 × 105
ZnO ATO Glass Spin coating 500 5.25 1.7 × 105 – 2007[162]
In2O3 SiO2 Si wafer Inkjet 150–200 4.3 106 – 2017[219]
InOx AlOx Si wafer Inkjet 250 19 107 0.15 2017[220]
In2O3 SiO2 Si wafer Spray pyrolysis 252 40 2017[46]
In2O3 Al2O3 Heavily doped Si Spin coating 250 31 ± 10 104 0.24 2017[183]
Gd:In2O3 AlOx Glass Spin coating 400 9.74 108 0.079 2017[177]
In2O3 SiO2 Glass Spin coating 350 3.5 3 × 107 0.36 2016[172]
Li:In2O3 ZrO2 Si wafer Spin casting 250 59.8 ± 0.2 6× 108 0.18 2016[179]
In2O3/Cu2O CSPE ITO-coated glass Inkjet printing Room 12.5 >106 0.078 2015[191]
(CMOS invertor) temperature
In2O3 Al2O3 Glass Flexography 300 8±4 106 0.4 ± 0.1 2015[75]
InOx SiO2 Heavily B-doped Spin coating 250 10 >107 0.92 ± 0.2 2015[173]
Si wafer
Table 3. Continued.
Semiconductor Dielectric Substrate Processing route Process Field-effect On/off ratio Subthreshold Year
temperature mobility swing [V per published
In2O3 Ethylene glycol Si wafer Spin coating 250 46 105 0.28 2015[184]
and AlOx
In2O3 ZrO2 Si wafer Spin coating 500 10 106 0.3 2015[193]
In2O3 AlOx Glass Inkjet printing 300 60 – 2014[182]
SnO2 74
In2O3 SiO2 Si wafer Spin coating 200 2.62 ± 0.25 >109 0.3 ± 0.06 2013[187]
PEN 200 3.14 >109 0.158
Ga-doped In2O3 SiO2 Si wafer Spin coating 500 12.68 108 0.78 2013[175]
In2O3 CSPE ITO-coated glass Inkjet printing 400 126 2× 107 0.068 2013[185]
In2O3 AlOx Si wafer Spin coating 350 127 106 0.14 2013[181]
In2O3/IGO SiO2 Si wafer Spin coating 300 2.6 108 – 2013[221]
Mg:In2O3 SiO2 Si wafer Spin coating 500 2.03 1.2 × 105 – 2012[178]
Ca:In2O3 1.64 2.5 × 105
Sr:In2O3 1.08 1.5 × 105
In2O3 CSPE PEN Inkjet printing Room 0.8 2 × 103 – 2011[222]
temperature
In2O3 SiO2 Si wafer Spin coating 500 55.26 107 – 2011[171]
Ga:In2O3 SiO2 Si wafer Spin coating 500 3.6 9.9 × 107 0.9 2011[174]
In2O3 SAND Si wafer Spin coating 400 43.7 ± 4.8 106 0.3 2008[180]
SnO2 SiO2 Si wafer Spin coating 500 0.23 106 – 2016[223]
SnO2 SiO2 Si wafer Spray pyrolysis 450 0.19 103 – 2015[224]
SnO2 Al2O3 ITO-coated glass Spin coating 450 96.4 2.2 × 106 0.26 2014[225]
SnO2 ZrO2 ITO-coated glass Spin coating 450 100 104–105 0.3 2013[200]
performances (mobility of 0.29 cm2 V−1 s−1 and on/off ratio of hybridized oxygen 2p and copper 3d orbitals form the valance
104).[238] band minimum (VBM), due to the interaction of charge carriers
The chosen gate insulators have been found to play a cru- (holes) with magnons and phonons,[244,245] the hole mobility in
cial role in the case of Cu2O FETs as well. Liu et al. have this case is reported to be very low (0.01–1 cm2 V−1 s−1, using
explored different dielectric possibilities for solution-processed Hall-effect measurements). Nonetheless, CuO has widely
CuxO FETs; the devices prepared (at 250 °C) with SiO2 and been used as a p-type semiconductor in transistors and logics.
Al2O3 gate dielectrics have shown mobility values of 0.32 and Although the majority of CuO-based FETs have been processed
2.7 cm2 V−1 s−1, respectively.[239] using UHV techniques,[246] countable reports on solution-
Similar to other p-type oxide semiconductor variants, reports processed FETs are also present.
on FETs fabricated using nanoparticle dispersions are quite Spin-coated CuO FETs have been reported by Jang et al. on
scarce. Baby et al. have reported Cu2O FETs based on nanopar- thermally oxidized silicon wafer, where Si/SiO2 back gate struc-
ticulate inks. In that report, dense nanoparticulate films have ture has been used.[247] The as-deposited precursors have been
been obtained owing to the adopted novel chemical curing sintered at different temperatures (200–500 °C). The phases
technique (halide salts are used to remove the stabilizers/ with lower oxidation state of Cu, namely Cu and Cu2O, are
organic ligands from the nanoparticle surface while drying the found to be present in the lower temperature annealed pre-
nanoparticulate film at room temperature). The devices have cursors, which eventually oxidize to single-phase CuO at
demonstrated a saturated drain current of 0.4 µA with an on/ higher temperatures (500 °C). The prepared FETs have shown
off ratio of around 103; however, the mobility value has not a mobility value of 0.01 cm2 V−1 s−1 only. Somewhat superior
been reported.[191] performances have been reported when solution-processed
p-Type Oxides—Cupric Oxide (CuO): Interestingly, cupric dielectrics have been used. For example, Garlapati et al. have
oxide (CuO) is also a p-type semiconductor and it is again the reported electrolyte-gated p-type CuO FETs.[186] The devices are
copper ion vacancies responsible for the hole conductivity. prepared using the inkjet printing technique and have shown
CuO has monoclinic crystal structure with the space group a mobility of 0.22 cm2 V−1 s−1. On the other hand, with water-
C2/c having four formula units of CuO per unit cell and four- induced high-k dielectrics Liu et al. have achieved a mobility
fold coordination between the copper and oxygen atoms. The of 0.8 cm2 V−1 s−1 using solution-processed scandium oxide
bandgap of CuO is in the range of 1.2–1.9 eV.[240–243] Although (ScOx) as the gate dielectric for CuO FETs.[248] Amorphous
lithium oxide (LiOx) has also been used as a gate dielectric by water-based precursors, whereas the misleading results can be
the same group and the devices have shown a mobility value avoided when all the measurements are carried out at mois-
of 1.72 cm2 V−1 s−1 in that case.[249] Furthermore, the process ture-free controlled atmosphere. Therefore, the transistors and
temperatures (300 °C) and the operating voltages (≤2 V) of the capacitors characterization must be performed at identical con-
devices have been substantially low. However, considering the ditions (atmosphere) and the parameter extractions should be
water-induced synthesis of the dielectrics, the possibility of carried out carefully from measurements at identical frequen-
adsorbed moisture and surface hydroxyl groups offering a weak cies. For example, an erroneous mobility value of IGZO TFTs
electrolyte like effect cannot be excluded. In this case, an under- can be obtained as 50–75 cm2 V−1 s−1, which reduces to only
estimation of the dielectric capacitance and thereby an overesti- 6 cm2 V−1 s−1, when the capacitance calculation has been per-
mation in the calculated mobility value are possible. formed cautiously.[260]
p-Type Oxides—Nickel Oxide (NiO): Stoichiometric NiO is p-Type Oxides—Tin Monoxide (SnO): Tin monoxide (SnO)
considered to be a Mott insulator; however, nonstoichiometric has PbO-type layered pyramidal structure, where Sn occu-
NiO is a p-type semiconductor due to Ni vacancies. The bandgap pies apex sites and oxygen occupies square base sites Here,
of Ni-deficient, p-type NiO is 3.6 eV; it possess cubic rocksalt the VBM is assumed by hybridized Sn 5s and O 2p orbitals,
structure.[250–252] NiO has traditionally been used in several which therefore leads to delocalized charge carriers (holes).
applications such as smart windows, photodetectors, OLEDs, The p-type conductivity is due to Sn vacancies, which form
and also in FETs.[253–255] Solution-processed p-type NiOx FETs shallow acceptor levels. The bandgap of SnO is in the range
have been reported by Liu et al. Here, spin-coated precursors from 2.5 to 3.4 eV, depending on the preparation conditions
are annealed at 500 °C to obtain crystalline NiOx films. Ther- and carrier doping.[227,261] In addition to the above-mentioned
mally grown SiO2 has been used as the gate dielectric and the attractive features, SnO has certain limitations as well, such
devices have shown a device mobility of 0.14 cm2 V−1 s−1.[256] as metastability in ambient conditions; in fact, it also requires
The hole mobility of NiOx can be enhanced by suitable doping absolutely stringent atmospheric control during the preparation
elements; Lin et al. have made such an attempt and have shown from solution phase (for example, during the annealing/curing
an improved device performance compared to undoped NiOx. process). Although the initial reports on functional devices/
Here, tin-doped NiOx FETs are prepared by a spin-coating FETs based on SnO thin films have only utilized UHV fabrica-
method; the Ni:Sn ratio has been maintained at an atomic ratio tion techniques,[234,262–265] recently, researchers have also made
of 100:5 in the precursors. Sn-doped devices have shown higher attempts to prepare p-type FETs using solution-processed SnO.
performances (mobility of 0.97 cm2 V−1 s−1) compared to the For example, solution-processed (spin-coating) p-type SnO
undoped ones (0.36 cm2 V−1 s−1).[257] FETs have been reported by Okamura et al. In this work, tin
On the other hand, Liu et al. have also reported NiOx chloride precursor is spin coated and annealed at different tem-
FETs that are annealed at different process temperatures peratures (200–600 °C in N2/H2 atmosphere) after exposing to
(150–350 °C); in addition, the suitability of different gate insula- NH4OH. The films have shown single SnO phase up to 450 °C
tors has been investigated (thermally grown SiO2 vs spin-coated and have subsequently decomposed to Sn and SnO2. The best
Al2O3,annealed at 250 °C). The devices (processed at 250 °C) performance (0.13 cm2 V−1 s−1 and on/off ratio of 85) has been
with solution-processed Al2O3 as the gate dielectric show way achieved for 0.1 m concentration films that are annealed at
superior performances (mobility value of 4.4 cm2 V−1 s−1, on/ 450 °C owing to their smooth surface and homogeneity.[245]
off ratio of 105, and SS of 250 mV per decade) compared to sil-
icon back gate SiO2 insulator–based devices (0.07 cm2 V−1 s−1,
104, and 2.3 V per decade).[258] However, here again a process 3.1.2. Amorphous Oxides
temperature of 250 °C may not yield pure Al2O3 films. In fact,
it has been shown by Nayak et al. that at low temperatures the The well-known n-type oxide semiconductors, such as ZnO,
films consist of hydroxyl groups.[181] Therefore, once again, it is In2O3, SnO2, etc., are crystalline in nature and they have shown
possible that the absorbed moisture or hydroxyl groups work nearly identical device performance when solution-processed/
as a weak electrolytic gate insulator, and a frequency-dependent printed as compared to their counterpart TFTs prepared by
polarization and transistor performance study may also shed physical vapor deposition techniques. For example, printed
light into this. In2O3 FETs with >125 cm2 V−1 s−1 have been reported by var-
Here, one may note that the use of solution-processed ious research groups.[181,185] However, on the one hand, solu-
low-temperature annealed dielectrics have always resulted in tion-processed crystalline oxides typically require high process
high mobility PMOS transistors, be it Cu2O,[239] CuO,[249] or temperatures to ensure good crystallinity and well-coordinated
NiOx;[257] likewise, substantially high mobility values have also MOM bonds, necessary for high carrier mobility; on the
been reported for various n-type oxide semiconductors,[248,259] other hand, large crystallite sizes bring about nonuniformity
when such low-temperature annealed oxide dielectrics are when printed over large areas. On the other hand, upon ana-
used. However, one needs to be careful here while extracting lyzing the device performance of every n-type oxide semicon-
device parameters, as has been demonstrated by Banger ductor covered in the last section, a general conclusion can be
et al.,[260] either due to the presence of impurity, incomplete drawn that nearly every high-performance solution-processed
precursor condensation, or mostly due to proton migration, TFT that has been reported, involving crystalline oxide semicon-
such low-temperature annealed dielectrics can show high die- ductors, has used top gate device geometry. In other words, the
lectric constant at low frequencies. The possibility of proton bottom gate devices have failed to provide high performance due
migration increases when the dielectrics are prepared from to large interface trap densities at the dielectric–semiconductor
interface resulting from highly inhomogeneous/rough (or at the end of this section); by varying the doping concentration
even porous) interface quality. In contrast, a large-area spatial of Ga, the carrier density can be optimized so that a positive
homogeneity is an intrinsic quality of organic semiconduc- threshold voltage, low on-currents leading to high on/off ratio,
tors and the same may also be true for the inorganic amor- and sufficiently high carrier mobility can be achieved at the
phous semiconductors. For example, amorphous silicon can same time.
be quite homogeneous across large area, which eases its use Indium–Gallium–Zinc–Oxide: In the first report of amor-
in liquid crystal display (LCD) backplanes; however, silicon, phous oxide FETs by Hosono and co-workers (it is the first
being a covalent compound, is highly directional, and its amor- report where transistor performance and advantages of AOSs
phous form loses carrier mobility down to 0.5 cm2 V−1 s−1,[266] have been discussed, otherwise amorphization of oxide
from the impressive 200–300 cm2 V−1 s−1,[12,13,267] commonly semiconductors was known before), a-IGZO has been pre-
observed in its polycrystalline form. In this regard, Hosono pared by pulsed laser deposition and a transistor mobility of
and co-workers have made an important observation, back in 6–9 cm2 V−1 s−1 has been reported.[270] With the realization of
2004, where they proposed that the performance deterioration potential amorphous oxide semiconductors, many researchers
can be significantly mitigated in amorphous oxide semiconduc- soon tried to prepare amorphous oxides, especially a-IGZO,
tors (AOSs) owing to their large spherical ns orbitals that pos- using solution-processing techniques.[189,272–276] However, in
sess no directional preferences.[268] For example, in amorphous the beginning, the success has rather been limited. Kim et al.
In–Ga–Zn–O (a-IGZO) the conduction band minimum (CBM) found crystalline phase of IGZO (InGaZn2O5) and very low
is formed by heavy metal cations, (n − 1)d10ns0, where n ≥ 5, transistor mobility of 0.96 cm2 V−1 s−1, when they annealed
with large spherical ns orbitals that overlap and are insensitive the precursor at 450 °C. Nevertheless, soon reasonably good
to distortions in chemical bonds. Consequently, band transport device performance (comparable to PVD grown TFTs) has been
of electrons is facilitated irrespective of arbitrary bond direc- reported by various groups. For example, Banger et al. pro-
tions upon amorphization. Interestingly, in a-IGZO, electron posed and demonstrated a novel method, termed as “sol–gel on
mobility increases with an increase in electron concentra- chip” to achieve high-performance a-IGZO devices.[275] In this
tion, due to an increasing probability of band overlap, which method, MOM frameworks form at low temperatures due
is a strikingly different trend when compared to the crystalline to enhanced hydrolysis and condensation reactions of metal
oxide semiconductors (refer to Figure 7a). Furthermore, the alkoxide precursors exposed to aqueous environments. The
density of subgap states is also low, which leads to superior a-IGZO FETs prepared at 275 and 350 °C have shown mobility
electrical stability.[269–271] The long list of attractive features may values of 4.05 and 6.12 cm2 V−1 s−1, respectively. Here, the pro-
also include the fact that, thanks to their amorphous nature, the cess temperature influences the device performance, however,
AOSs can be fabricated at somewhat lower temperatures, com- not as significantly as it is the case in conventional methods.
pared to their crystalline counterparts; on the other hand, the Of course, many researchers have utilized photonic curing to
amorphous phases are also found stable up to a notably high reduce process temperatures.[189,276–278] One of the early and
temperature of 450 °C. The AOSs are transparent due to large significant reports involves use of mercury-based deep UV
bandgap (3.4 eV) and can be formed by combining In and Zn lamp (major peak is at 253.7 nm) to obtain very high energy
precursors, for example. However, the concentration of oxygen photons (180–201 J cm−2) to drive the hydrolysis and condensa-
vacancies in that case is rather high, which may lead to high tion reactions of metal alkoxides to form MOM bonds;[189]
zero gate currents and negative threshold voltages. Therefore, the fabrication of FETs on both rigid (glass) and flexible sub-
a small fraction of a strong oxygen binder (Ga) can be added strates (polyarylate) have been demonstrated. A longer curing
to suppress oxygen vacancies (in fact, a wide range of carrier time is found to improve (30 and 120 min) the device perfor-
suppressors have been considered, which will be summarized mance (0.7 and 2.3 cm2 V−1 s−1, respectively).
Figure 7. The electron mobility and carrier concentrations obtained from the Hall effect measurements for the amorphous and crystalline thin films
(number in the parenthesis denotes carrier concentration (×1018 cm−3)) (left) and the amorphous and crystalline region of the In2O3–Ga2O3–ZnO
phase diagram (right). a,b) Reproduced with permission.[279] Copyright 2006, Elsevier.
The chemical composition, i.e., the relative ratio of the metal has been shown that annealing (at 400 °C) in a saturated water
cations (In:Ga:Zn), is important for amorphization, film mor- vapor oxidizes the precursor film efficiently, which improves
phology, and electronic performance.[279–283] As it can be noted MOM bond formation and decreases the fraction of MOH
from Figure 7b, a large amorphous region is present in this bonds, resulting in a decrease in annealing time necessary
ternary system; the Hall mobility is found to increase with from hours to 5 min, alongside a substantial increase in device
an increasing indium content due to the large ionic radius of mobility from 19.2 cm2 V−1 s−1 observed in the case of conven-
indium;[279] however, a too high percentage of indium initi- tional air annealing to 27.9 cm2 V−1 s−1 for annealing in satu-
ates crystallization at lower annealing temperatures, increases rated water vapor.[287] Likewise, UV/O3 treatment has also been
film roughness, and also shifts the threshold voltage to nega- reported to result in an improvement of the film quality.[288]
tive values and thereby forces the device operation to depletion Even though the spatial homogeneity and insignificant sur-
modes.[280] A similar effect of composition has been observed face roughness of the amorphous semiconductors should pro-
by Lee et al., where mobility value increased with an increase vide excellent semiconductor–dielectric interfaces in every case,
in In content and a higher concentration of Ga lowered the off- however, again superior device performance has been reported
currents due to suppression of free carriers.[281] On the other for solution-processed high-k dielectric-gated FETs.[289–291]
hand, an increase in Zn concentration has also been found to Using a combination of solution-processed dielectric zirco-
have a negative effect on the device performances; the tran- nium aluminum oxide ((Zr,Al)2Ox) and a cosolvent catalyst
sistor mobility of a-IGZO decreased from 5.8 to 1.6 cm2 V−1 s−1 formamide (formamide can accelerate the condensation reac-
with increasing Zn content from 3:1:1 to 3:1:3 of molar ratio of tion and facilitate MOM bond formation with very little
In:Ga:Zn.[282] hydroxide content) in the amorphous oxide precursor, a tran-
Processing conditions are found to play a significant role in sistor mobility of 50 cm2 V−1 s−1 has been observed.[291] Like-
determining the composition, morphology, and defect densi- wise, Everaerts et al. have used solution-processed hafnia-based
ties in the films, particularly for solution-processed amorphous SAND as the gate insulator and achieved a device mobility of
oxides, which are not as densely packed as the sputtered ones. 50 cm2 V−1 s−1 (Figure 8).[289]
The surface pores can adsorb oxygen, which in turn changes Often the solution-processed IGZO FETs have been found to
carrier concentration and work functions.[284–288] For example, suffer from bias stress instability.[271,292] However, it has been
IGZO films prepared by electrolysis of aqueous mixed metal reported that by lowering the defect densities and interband
nitrate salts resulted in much denser morphology as com- states, one can overcome the adverse bias stress effects. For
pared to sol–gel films, as reflected in device performance example, it has been shown that an annealing in air at higher
(8.9 cm2 V−1 s−1 vs 2.2 cm2 V−1 s−1, respectively).[285] In addition, temperatures can reduce the surface density of states (DOS)
a thin interfacial layer of solution-processed and amorphous and also annihilate shallow defects reducing the hysteresis in
ITZO film intentionally placed in between the IGZO and the the FETs. Naturally, the annealing conditions may also help;
dielectric layer has been found to annihilate structural defects for example, as previously mentioned, annealing in wet oxygen
and pores, thereby resulting in a device mobility improvement promotes oxidation of IGZO and reduces the defects as well
up to ≈30 cm2 V−1 s−1. An increase in annealing temperatures as weak chemical bonds such as Zn–O, thereby resulting in
of precursor films from 300 to 600 °C could increase oxygen improved bias stress stability.
vacancies, improve film morphology, and as a consequence the Indium–Zinc–Oxide: Following the momentous work by
transistor mobility increased from 3 × 10−3 to 6.4 cm2 V−1 s−1.[286] Hosono et al.[268] that introduced amorphous semiconductors
However, at such high temperatures, the semiconductor in the form of IGZO, researchers have realized that amorphous
has not been fully amorphous and a certain fraction of oxide phase formation may also be possible without Ga addition
nanocrystals has been observed. Identical to crystalline In2O3, it and the amorphous phase comprising In–Zn–O can be stable
Figure 8. a) Transfer curve and b) comparative average mobility of different dielectric-gated and inkjet-printed IGZO transistors. Reproduced with
permission.[289] Copyright 2013, American Chemical Society.
up to 500 °C.[293] However, without the carrier suppressor Ga, could increase the mobility value up to 7.8 cm2 V−1 s−1 owing
the price to pay in this case is the rather high carrier concen- to negligible Zr diffusion into the channel.[304] On the other
tration, which sometimes may lead to negative threshold and hand, alongside solid-state electrolyte sodium beta alumina
depletion mode operation of FETs. The structure of IZO has a (SBA), FET mobility values of 12.25 and 8.1 cm2 V−1 s−1 have
resemblance to the bixbyite structure of indium oxide, where been observed for devices that are processed at 830 and 200 °C,
the amorphous nature of IZO is enhanced by the tetrahedral respectively.[305]
Zn sites, which prevents the octahedral ordering of indium As the electrical stress stability is always an issue to be con-
atoms.[294–296] IZO falls within the transparent amorphous sidered with seriousness, the formation of well-oxidized pure-
oxide semiconductor category with a bandgap of >3.1 eV. phase materials and oxyanion doping has been found effective
Solution-processed IZO films, in general, can be prepared to stabilize the device performance. For example, Singh et al.
by combining precursor solutions of indium and zinc. The have used UV–ozone treatment prior to thermal annealing,
early reports have been focused on finding the suitable com- which removed the carbon-based impurities resulting in a sig-
position of precursors, process conditions (annealing tem- nificant rise in mobility (35 cm2 V−1 s−1), and a VT shift of only
peratures), etc.[297–300] For example, Kim et al. have studied the 2 V (with an operating voltage spanning 80 V).[306] On the other
effect of different zinc precursors (acetate and nitrate) on the hand, Park et al. have incorporated oxyanions such as SO42−,
transistor performance and observed that both precursors can PO43−, BO33−, etc., which reduce oxygen vacancies and decrease
form IZO at 250 °C; however, the residual impurities are more MOH bonds.[307] As a result, although the FET mobility is
abundant in the case of acetate precursors.[297] Similarly, ace- found slightly lower (8.1 cm2 V−1 s−1) compared to the undoped
tate, chloride, and their mixture have been tested by Lee et al. a-IZO (20.3 cm2 V−1 s−1), the trap states reduced significantly,
to obtain mobility values of 2.83, 4.37, and 1.45 cm2 V−1 s−1, resulting in an excellent bias stress stability (VON shift of 0.7 V
respectively.[298] Although the mobility is low for the combined as opposed to 4.9 V for undoped IZO FETs). In a subsequent
precursor-based IZO FETs, the bias stress stability is found to report, Park et al. have also shown that a prolonged heating at
be superior. The effect of annealing temperature and precursor a low temperature of 250 °C can recover the VT shift to original
concentration has been studied by Haeming et al. to conclude values by releasing the trapped charges at the semiconductor–
that a higher annealing temperature improves mobility due to a dielectric interfaces.[308]
delocalization of the metal ns orbitals and increased charge per- Zinc–Tin–Oxide: The amorphous IZO and IGZO films
colation paths.[299] On the other hand, a decrease in precursor typically have superior properties among AOSs due to their dis-
concentration is found to increase device mobility. persed band structure. However, the expensive and scarce ele-
Similar to other oxides, the researchers have also tried to ments such as indium and gallium have motivated researchers
reduce the processing temperature of IZO.[188,189,275,301,302] to look for alternative amorphous oxides, such as zinc–tin
The combustion synthesis, by Kim et al., approach has also oxide. ZTO is inexpensive, nontoxic, and environmentally
resulted high-performance IZO transistors. The authors have stable; it has the advantages of both ZnO (transparency and
reported a-IZO FETs also on polymer (AryLite polyester) sub- stability in hydrogenated environments) and SnO2 (stability in
strates; however, the devices prepared at lower temperatures acidic and basic solutions).[309] The bandgap of ZTO is around
(225 °C) have shown an FET mobility of only 0.32 cm2 V−1 s−1 3.6 eV; somewhat high mobility is also possible with ZTO due
as compared to 9.78 cm2 V−1 s−1 obtained for FETs treated at to large spherical ns orbitals of Sn.[310,311] Amorphous ZTO
400 °C.[188] On the other hand, Kang et al. have utilized self- can be stable up to high temperatures (≈500 °C) after which it
combustion reaction, in which along with fuel and oxidizer, a transforms to crystalline phases, such as ZnSnO3 or ZnSnO4,
pH controlling agent (NH4OH) has also been added to improve etc.[312] Although the initial reports of ZTO-based FETs have
the metal cation coordination number.[301] An average mobility mostly used PVD techniques, recent reports on high-perfor-
of 1.17 cm2 V−1 s−1 has been achieved upon annealing at 250 °C, mance solution-processed/printed ZTO FETs have sometimes
which increased to 8.7 cm2 V−1 s−1 with an increase in the pro- exceeded the performance of the average PVD-grown TFTs.
cessing temperature to 350 °C. Another novel method, sol–gel Studies involving the effect of precursor compositions,
on chip, has been used to prepare a-IZO FETs at 250 °C and the annealing temperatures and annealing atmospheres have been
devices have shown a maximum mobility of 14 cm2 V−1 s−1. The carried out by various research groups.[313–318] For example,
devices have also demonstrated superior bias stress stability Kim et al.[313] have systematically studied the effect of Zn:Sn
and found to be comparable to the FETs prepared by sputtering ratio on the performance of ZTO FETs ranging from zinc to tin
methods.[275] On the other hand, a-IZO FETs that are prebaked ratio of 13:1 to 1:13, to conclude that the maximum mobility,
at 230 °C, followed by a microwave annealing, have shown as well as superior bias stress stability, can be achieved with a
mobility values of 6.9 cm2 V−1 s−1.[302] Complete photonic Zn to Sn ratio of 1:1. Lee et al.[315] have investigated the effect
curing (without conventional heating), however, resulted in a of annealing temperature (300–500 °C) on the performance of
maximum device mobility of 1.2 cm2 V−1 s−1 only.[189] ZTO-based FETs and observed a rise in the measured device
Unlike IGZO, there are not many reports where solution- mobility from 0.18 to 4.75 cm2 V−1 s−1 with an increasing
processed dielectric layers have resulted in a large perfor- annealing temperatures, which can be due to an increase in
mance boost for a-IZO. An FET mobility of 3.4 cm2 V−1 s−1 has oxygen content (MOM bonds) and better removal of impu-
been obtained using amorphous magnesium–titanium–oxide rities and carbonaceous contaminations present in the precur-
(MTO);[303] amorphous AlOx resulted in improved performance sors. Similarly, Kwack and Choi[316] have also obtained high-
(µFET = 3.4 cm2 V−1 s−1) owing to diffusion of Al into the semi- performance TFTs (transistor mobility of 4.39 cm2 V−1 s−1
conductor layer, likewise a multilayer AlOx/ZrOx dielectric and on/off ratio of 107) using 1:1 Zn:Sn precursor and
electrohydrodynamic jet printing; here again the high perfor- (from 5.2 to 6.2 cm2 V−1 s−1) upon 20 weeks of air exposure,
mance has been attributed to fully oxidized metal cations (Zn which they have explained by assuming an improved stoi-
and Sn) resulting in low trap densities. Next, Seo et al.[318] have chiometry and higher MOM bond formation as a result
used zinc acetate and tin chloride as precursors (1:1 ratio), and of atmospheric oxygen adsorption.[329] In this report, the as-
obtained high performance (device mobility > 14 cm2 V−1 s−1 prepared FETs have shown stable performance under red and
and on/off ratio > 108) upon annealing the films at 500 °C. green lights; however, due to photogenerated free carriers, vast
Not only the annealing temperatures but also an additional instability has been observed for blue light exposure. Bias–tem-
prebaking step at a suitable temperature and duration is found perature–illumination stability studies on fluorine-doped ZTO
to have profound effects; Lee et al. performed a systematic (F:ZTO) FETs have been performed by Jeon et al.,[330] where
prebaking at 80 and 100 °C for different durations to find a methacryl-oligosilixane has been used as the passivation layer.
maximum mobility of 16.2 cm2 V−1 s−1 for a prebaking at 100 °C Upon simultaneous exposure to electrical bias (20 V), temper-
for 30 min.[319] Toward lowering the process temperature, ature (60 °C), and light (wavelength of 400–650 nm), a shift
a-ZTO devices have been prepared using combustion synthesis in the threshold voltage by only 1 V has been observed, which
at different temperatures (225 and 400 °C) to obtain transistor is then attributed to the recombination of free electrons with
mobility of 0.29 and 7.34 cm2 V−1 s−1, respectively.[188] photogenerated holes.
The attempts to dope a-ZTO with a third metallic element Amorphous Indium–Tin–Oxide (a-ITO): As has earlier been
has not been particularly successful.[320–322] La addition is found mentioned, indium oxide has cubic bixbyite structure, which
to be worthwhile only at low concentrations (due to its high is similar to fluorite structure except that the MO8 coordina-
electronegativity at lower concentrations it may act as electron tion units have to be replaced with the units that have missing
generator);[320] at a higher percentage its oxygen binding ability oxygen atoms either at body or at face diagonal. Hence, it forms
and carrier suppressing tendency have been found to domi- MO6 coordination groups with indium atoms in two different
nate. In fact, a suitable fraction of La:Zn:Sn has been found positions. Here, it is possible to obtain amorphous indium
to be 0.5:1:5, where a mobility of 5.78 cm2 V−1 s−1 has been oxides by distorting these MO6 coordination units. The prepara-
achieved. On the other hand, for Si addition, the performance tion conditions and doping with different elements can affect
of FETs has been found to deteriorate all the way from 1.95 to the crystallization and result in amorphous phase formation. A
1.09 cm2 V−1 s−1 for a Si:Zn:Sn ratio of 0:1:1 to 0.06:1:1, respec- widely used element for this purpose is Sn and amorphization
tively, which may again be related to the oxygen affinity and car- can easily be induced by tuning different process parameters
rier suppressor behavior of Si.[321] during the physical vapor deposition process.[331]
Contrary to general expectations, a-ZTO devices have shown Though Sn-doped In2O3 (ITO) is usually known as a
tremendous improvements in device performance when solu- degenerate semiconductor or as the best-known transparent
tion-processed dielectrics alongside top-gate device geometry conductor, several researchers have shown that it is pos-
have been used.[305,323–328] In this regard, solution-processed sible to obtain solution-processed, amorphous, and semi-
ZrO2 dielectric has resulted in a mobility of 27.3 cm2 V−1 s−1,[323] conducting ITO by varying the doping concentration as well
whereas amorphous zirconium aluminum oxide, ZAO, has as the preparation conditions.[332–336] In general, the perfor-
reportedly shown a mobility value that is even higher, as high mance of a-ITO devices varies with the In/(In+Sn) ratio and
as 37 cm2 V−1 s−1.[324] Next, solution-processed amorphous AlOx the annealing temperatures; a change in indium concen-
along with spin-coated and inkjet-printed ZTO have yield FET tration can alter the amount of oxygen vacancies, which in
mobility of 33 and 24 cm2 V−1 s−1, respectively.[325] The highest turn modifies the device performance. Following systematic
mobility of a-ZTO has been reported by Zhao et al.,[326] where studies, it has been concluded that a very low concentra-
solution-processed Al2O3-gated a-ZTO FETs have resulted tion of In lowers the FET mobility, whereas a too high con-
78.9 cm2 V−1 s−1; however, in this case, the authors have centration renders the films highly conducting and a field-
noted inhomogeneity in the a-ZTO films and the presence of effect cannot be observed.[332,333] For example, Jung et al.
a considerable fraction of nanocrystalline phases in the amor- have achieved the maximum performance (3 cm2 V−1 s−1) at
phous matrix. Ceramic solid electrolytes have also been tested an In:Sn ratio of 5:1 and no transistor behavior at all, at a
along with a-ZTO; sodium beta alumina have yielded mobility ratio of 9:1, which is typically the concentration in commer-
of 28 and 10 cm2 V−1 s−1, respectively, when the annealing tem- cial transparent conductor, ITO.[332] On the other hand, Kim
perature of the novel dielectric has been varied from 830 to et al. have reported the optimum In:Sn molar ratio to be
200 °C, respectively.[305] The same group has later tested Li- and 7:3.[333] Partial replacement of Sn with other elements, such
K-doped beta alumina as well and have found identical perfor- as Al, may also reduce carrier concentration and promote
mance range, with mobility value of 19.6 and 16.1 cm2 V−1 s−1, amorphization. Jeon et al.[334] have investigated Al-doped ITO
respectively.[327] However, in this study the authors have found films (Al2O3)x(In2O3)0.9-x(SnO2)0.1 for an Al concentration
that the electrical performance of the FETs decreases with tem- of x = 0–0.6; the optimal doping level has been found to be
perature which indicates that the moisture adsorbed in these x = 0.3, which resulted in a mobility value of 13.3 cm2 V−1 s−1.
ceramic solid electrolyte also plays a significant role in the The effect of high-k novel dielectrics and a superior interface
double layer formation. quality on a-ITO-based FETs is essentially identical to other
a-ZTO can be stable in the ambient conditions and typi- oxide semiconductors. Compared to SiO2, the use of self-assem-
cally shows better electrical stress stability than a-IGZO FETs. bled nanodielectric could increase the FET mobility from 2.2 to
However, often they show photosensitivity. In this regard, 20 cm2 V−1 s−1.[333] Similarly, with ferroelectric gating (using a
Nayak et al. have actually observed an increase in mobility stack of (Bi,La)4Ti3O12 (BLT) and Pb (Zr,Ti)O3 (PZT)) field-effect
Table 4. An overview of processing parameters and performance (field-effect mobility, on/off ratio, and subthreshold swing) of solution-processed/
printed amorphous oxide semiconductor TFTs.
Semiconductor Dielectric Substrate Processing Annealing Field-effect On/off ratio Subthreshold Year
route temperature mobility swing [V per published
IGZO SiO2 Si wafer Inkjet printing 300 6 105 – 2016[337]
8
IGZO SiO2 Si wafer Spin coating 200 0.3 10 – 2015[276]
IGZO SiO2 Si wafer Spin coating 300 30 106 – 2015[285]
IGZO SiO2 Si wafer Spin coating 400 20.1 4.7 × 105 1.9 2015[287]
IGZO SiO2 Si wafer Drop coating – 10.5 3× 105 2 2015[278]
IGZO SiO2 Si wafer Spin coating 400 0.97 5× 107 0.58 2014[292]
IGZO SiO2 Si wafer Spin coating 600 7.4 107 0.22 2014[288]
IGZO Hf-SAND Si wafer Inkjet Printing 300 20 107 0.19 2013[289]
IGZO SiO2 Si wafer Spin coating 450 1.1 – 1.29 2013[338]
IGZO SiO2 Si wafer Spin coating 350 1.4 – – 2013[281]
IGZO SiO2 Si wafer Spin coating 400 10.4a) – – 2013[339]
IXZO SiO2 Si wafer Spin coating 300 5.4 (Ga) 8 2013[283]
10 –
2.6 (Sc) 108
2.4 (Y) 107
1.8 (La) 107
IGZO Poly-4-vinyl phenol Glass Spin coating <300 2.04 1.5 × 106 0.84 2013[277]
IGZO SiNx Glass Spin coating 500 0.07 – 0.69 2012[340]
IGZO Al2O3 Glass Spin coating 150 8.76 ± 0.98 108 0.096 2012[189]
Polyarylate film 3.77 ± 1.02 108 0.096 ± 0.021
IGZO SiO2 Si wafer Spin coating 230 10 >108 <0.5 2011[275]
IGZO SiO2 Si wafer Spin coating 300–600 0.003– 6.415 4.5 × 104 3.9 × 107 2.39–2.3 2011[286]
IGZO Aluminum ITO-coated glass Spin coating 400 5.8 6× 107 0.28 2010[282]
titanium oxide
IGZO YHfZnO Si wafer Spin coating 600 0.29 105 1.26 2010[290]
IGZO SiO2 Si wafer Spin coating 400 0.75 105 – 2010[284]
IGZO SiO2 Glass Spin coating Laser annealing at 7.65 2.9 × 107 – 2010[341]
95 °C
IGZO SiNx Glass Gravure 550 0.81 1.3 × 106 0.85 2010[74]
IGZO SiO2 Si wafer Spin coating 500 0.5–2 >107 1.5 2010[280]
IGZO SiO2 Si wafer Dip casting 300 0.05–0.2 >106 1 2009[342]
IGZO SiNx Si wafer Spin coating 400 1.25 4 × 106 1.05 2009[274]
IGZO SiNx Glass Spin coating 450 0.96 106 1.39 2009[272]
IGZO SiNx Glass Spin coating 450 0.96 2× 105 – 2008[273]
IZO SiOx Si wafer Spin coating 280 0.14 3.6 × 106 – 2017[343]
IZO SiO2 Glass Spin coating 200 4.44 4.3 × 106 0.79 2015[300]
IZO ZrOx/AlOx bilayer Glass Spin coating 350 7.8 3.5 × 106 0.21 2015[304]
Al:IZO Aluminum-doped Glass Spin coating 300 6.03 106 0.73 2015[344]
zirconium oxide
IZO SiO2 Si wafer Spin coating 300 35 106 – 2014[306]
IZO SiO2 Si wafer Spin coating 350 20.3 105 0.78 2014[307]
IZO SiO2 Si wafer Spin coating 425 6.7 ± 1 – – 2014[299]
IZO Mg0.6Ti0.4O Glass Spin coating 450 3.4 6 × 106 0.32 2014[303]
IZO SiO2 Si wafer Spin coating 350 13.8 108 – 2014[301]
IZO SiO2 Si wafer Felxography 450 2.4 5.2 × 107 – 2014[76]
Table 4. Continued.
Semiconductor Dielectric Substrate Processing Annealing Field-effect On/off ratio Subthreshold Year
route temperature mobility swing [V per published
IZO SiO2 Glass Spin coating 350 (dual active 2.89 1.4 × 107 0.59 2013[297]
layer) 250 (nitrate 0.21 3.7 × 106 0.52
precursor) 250 0.05 6.1 × 105 1.09
(acetate precursor)
IZO SiO2 Si wafer Spin coating 450 1.45 1 × 105 1.83 2013[298]
F:IZO SiO2 Si wafer Spin coating 200 4 4× 108 0.20 2013[345]
IZO Poly-4-vinylphenol Polyimide Spin coating Microwave heating 7 >1 × 106 – 2010[302]
(2.45 GHz)
IZO SiNx Glass Spin coating 250 6.6 109 0.15 2010[308]
ZTO ZAO (1:2) Si wafer Spin coating 500 37 1.5 × 105 0.10 2016[324]
ZTO Al2O3/ Si wafer Spin coating 500 107 0.40 2016[322]
Ni-nanocrystals/
SiO2
ZTO SiO2 Si wafer Spin coating 500 13–14 108 0.30 2015[346]
ZTO SiO2 Si wafer Spin coating 450 4.3 4.1 × 107 0.4 2014[310]
ZTO SiO2 Si wafer Spin coating >106 1.0 2014[347]
La:ZTO SiO2 Si wafer Spin coating 500 0.51 9.5 × 106 1.09 2013[320]
ZTO SiO2 Si wafer Electrohydrody- 400 4.9 107 0.44 2013[316]
namic jet spraying
Si:ZTO SiO2 Si wafer Spin coating 500 1.9 1.7 × 107 0.38 2013[321]
ZTO Al2O3 ITO-coated Glass Spin coating 450 78.9 105 7.27 2013[326]
ZTO Potassium ITO-coated glass Spin coating 500 16 5 × 10 3 0.29 2013[327]
β-alumina 19.6 2 × 104 0.2
Lithium β-alumina
ZTO:F SiO2 Si wafer Spin coating 350 11.52 107 0.76 2012[330]
ZTO SiO2 Si wafer Spin coating 500 4.75 >108 – 2012[315]
ZTO SiO2 Glass Inkjet printing 300 1.8 107 0.29 2011[314]
ZTO ATO ITO-coated glass Spin coating 500 6.2 107 2011[329]
ZTO AlOx Glass Spin coating 300 33 108 0.096 2011[325]
ZTO ZrO2 Glass Spin coating 350 27.3 >107 0.122 2010[319]
ZTO ZrO2 Glass Spin coating 500 >20 – – 2010[323]
ZTO SiO2 Si wafer Spin coating 500 14.1 >108 0.4 2009[318]
ZTO SiO2 ITO-coated glass Spin coating 500 1.02 107 0.52 2009[328]
ZTO Sodium ITO-coated glass Spin coating 28 2× 104 – 2009[348]
β- alumina
a)
With 50% formamide and 50% ZAO dielectric.
mobility of 6.5 cm2 V−1 s−1 and a large nonvolatile memory of which InZnO turns highly conducting and the TFTs tend to
window of output voltage of the order of several volts have been operate in depletion mode with negative threshold voltages.
achieved.[335] A summary of processing as well as performance However, the replacement of Ga with smaller cations, such as
parameters of various solution-processed/printed amorphous Al (µFET = 0.58 cm2 V−1 s−1)[349] or Mg (µFET = 0.27 cm2 V−1 s−1),[350]
oxides TFTs are presented in Table 4.[337–348] has resulted in rather limited performance; somewhat better
Other Amorphous Oxides: Beside the above-mentioned com- outcome has been recorded for larger cations, for example,
positions, there have been numerous attempts to find better La (µFET = 2.64 cm2 V−1 s−1),[351] Y (µFET = 3.5 cm2 V−1 s−1),[352]
suited alternatives, either by a replacement of Ga in IGXO Zr (µFET = 3.8 cm2 V−1 s−1),[353] or Ba/Sr (µFET = 26 cm2 V−1 s−1).[354]
(where X is different rare earths) or an exchange of In by a lower A comparative study of different oxygen suppressors has been
cost and nontoxic element. As has been mentioned before, in performed by Hennek et al.[283] the oxygen getter effect of various
InGaZnO, Ga is added as the carrier suppressor, in the absence (where X = Ga, Sc, Y, and La) FETs are investigated; and again Ga
is found to be the most suitable (µFET = 5.4 cm2 V−1 s−1) as Ga process temperature of 250 °C or above which is higher than
can promote superior MOM lattice formation; Sc, Y, and La the glass transition temperature of most of the inexpensive and
having larger ionic radii than Zn or In result in higher disorder transparent polymer substrates. Hence, it may be stated that
in the structure and so reduce device mobility. In somewhat the quest for reduction in process temperature for solution-
contraction to the above report, later in 2015, Smith et al.[355] processed oxide electronics is still very much continuing.
have also compared various group 3B cations, i.e., Sc, Y, and La
as the oxygen getter material to report that the highest mobility
(µFET = 9.7 cm2 V−1 s−1) can be obtained for 5% La addition. 3.2. Carbon Nanotubes
Here, the rationale has been that the higher ionic radii dopants
lead to an easy amorphization at lower atomic percentages and Single-walled carbon nanotubes (SWCNTs) can be viewed
can yield higher device mobility. On the other hand, replacement as direct derivatives of graphene. Their cylindrical walls are
of Ga with group 4A elements (such as Si or Sn) has been inves- formed from rolled-up and seamlessly connected, 2D, hon-
tigated by Chong et al. Though the observed device mobility of eycomb sheets of carbon atoms. As a result, SWCNTs inherit
InSiZnO has been reasonably high (21.6 cm2 V−1 s−1),[356] strik- most of the superior characteristics of graphene such as
ingly higher µFET values of 104[357] or 110 cm2 V−1 s−1[358] have extraordinary electrical properties, outstanding thermal con-
also been reported recently for Sn-doped IZO (ZITO) FETs; ductivity, mechanical robustness, and flexibility. On top of that,
however, in these cases, the presence of small nanocrystals in SWCNTs reveal additional physical phenomena by the very fact
the amorphous matrix can be the underlying reason behind of being wrapped, which imposes extra boundary conditions
such high mobility values. These values are well beyond the on the electronic band structure. The carbon sheets are rolled
mobility of any other amorphous oxide semiconductor FETs, in discrete crystallographic directions defined by the so-called
reported till date, even when they are physical vapor deposited. chiral indices (n, m). Ultimately, the combination of the rolling
On the other hand, attempts to replace In have mostly resulted direction and nanotube diameter determines the electronic
in comparatively lower device performance as has also been properties of a particular SWCNT. The most dramatic effect dif-
seen in the case of ZnSnO (ZTO). For example, Jeong et al.[359] ferentiating SWCNT from pure graphene is the opening of a
have demonstrated GSZO-based TFTs with bias stress stability bandgap (in the range of a few hundred meV) for certain com-
superior to ZTO, however, with a field-effect mobility of only bination of (n, m) indices. The remaining SWNCTs are nomi-
1.2 cm2 V−1 s−1. nally metallic but usually show narrow bandgaps (in the range
At the end, when the field-effect mobility of various high- of a few meV) introduced by an interplay of curvature and
performance crystalline and amorphous oxides are compared strain. Natural extensions of the SWCNT class are multiwalled
together (Figure 9), a decisive trend can be observed where carbon nanotubes (MWCNTs) that consist of two or more rolled
mobility values of both crystalline and amorphous semiconduc- layers of graphene and also exhibit either metallic or semicon-
tors have increased with process temperature. Although count- ducting characteristics.
able examples are present, where a device mobility of about Since the first report of carbon nanotubes back in 1991 by
10 cm2 V−1 s−1 or a little higher has been recorded for process Iijima,[360] numerous different applications for these materials
temperature <100 °C (mostly for nanoparticulate FETs[191] have been envisioned and pursued. Moreover, immediately
though), which can be compatible to any plastic/cellulose sub- the research community realized that the wealth of accessible
strate, however, real high mobility transistors (has been high- electronic properties in CNTs is a mixed blessing. Depending
lighted with red and blue ellipses in the figure) have required on the synthesis process, the CNTs have shown an assort-
ment of completely different properties and behaviors. As a
consequence, semiconducting and metallic CNTs have to be
sorted out before they can be put in good use. Indeed, the cost
of sorted semiconducting CNTs has been so far a main hin-
drance for applications in large-area electronics. Though most
of the MWCNTs have metallic conductivity, the SWCNTs are
often semiconducting (depending on the chirality, i.e., (n, m)
indices).[361] The use of carbon nanotubes as channel material
requires sorting and alignment as a mandatory step as the elec-
tric resistivity changes with the chirality of the SWCNTs, from
metallic to semiconducting with a large range of tunable band-
gaps.[362,363] Consequently, the sorting techniques should be
capable of separating the CNTs according to their chirality.[361]
A detailed discussion of the sorting techniques may actually be
out of the scope of this review. However, the reader can follow
the subsequent citations to learn more about the prominent
sorting techniques, for example, dielectrophoresis,[361] density
gradient ultracentrifugation,[364] chromatography,[365] and selec-
Figure 9. Field-effect mobility versus process temperature for various tive dispersion with conjugated polymers.[366,367] In addition to
crystalline (In2O3, SnO2, ZnO, both precursor- and nanoparticle-based sorting, “cloning” techniques for specific CNTs to synthesize
FETs) and amorphous oxides (IGZO, IZO, and ZTO). identical structures has also been pursued.[368] Though very
good transistor performance has been achieved with aligned top-gate transistors with silver electrodes and inorganic high-k
CNT channel FETs, the alignment techniques are difficult to be dielectrics have been gravure printed onto flexible substrates
implemented into a fully printing-based fabrication procedure using semiconductor-enriched SWCNTs as the ink material
and, typically, require an additional post-treatment. Especially (Figure 10).[377] A mobility of ≈9 cm2 V−1 s−1 has been obtained
the scale-up of alignment techniques for nanotubes, e.g., based and the electrical performance has not been affected signifi-
on electrophoretic processes,[369–371] would be difficult to match cantly after systematic bending tests with bending radius down
any high-throughput operation. Consequently, in this section, to 1 mm. Similarly, Lee et al.[378] have observed that perfor-
following the main course of the review, we would solely center mance can be improved by increasing the number of printed
our attention to the scalable printed nanotube FETs, i.e., to the layers as they increase the density of CNTs in the channel and a
results obtained with printed/printable CNT-network channel substantially high mobility of 43 cm2 V−1 s−1 could be obtained.
transistors only. Similar to other inorganic materials, the performance of
In this regard, many groups have explored techniques such CNT FETs can be affected by the dielectric. More often than
as, to name a few, doping, dielectrophoretic aligning, sorting, not, electrolytes/ion gels have shown high-performance devices,
transfer to flexible substrates, etc., to improve the performance which is the case for CNTs as well. For example, Ha et al.[379]
of printed SWCNT transistors.[369,370,372,373] In multiple cases, have prepared ion gel–gated printed SWCNT FETs on a flexible
the inherent heterogeneity of as synthesized SWCNTs and polyimide substrate, and the devices have shown ambipolar (n-
the variation in diameter and chiral angle have led to a wide and p-type) nature and mobility of 17 and 31 cm2 V−1s−1 for n-
spread performance matrix for the fabricated devices. As an and p-type FETs, respectively. On the other hand, the devices on
attempt to overcome this recurring inhomogeneity problem, glass substrates have shown higher mobility values of 40 and
Arnold et al.[364] successfully sorted a nanotube mixture by 50 cm2 V−1 s−1 for electrons and holes, respectively.[380] The idea
density-gradient ultracentrifugation into fractions with dis- to use a conducting salt-containing polymer as the gating mate-
tinct diameter, bandgap, and electronic type. Carrier mobilities rial has also been used by Chen et al.[381] LiClO4 is added to
of ≈20 cm2 V−1 s−1 have been reached by separating only the polyethylenimine (PEI) and this composite is utilized as gating
semiconducting SWCNTs. Similarly, Lee et al.[374] have followed material. Both back- and top-gated devices are built and then
this approach to remove metallic nanotubes, which reduce the a fully printed SWCNT thin film transistor circuit for OLED
on/off ratio of the FETs. In this effort, although the FETs have control and display has been developed. It has also been shown
shown lower mobility values of 1.5 cm2 V−1 s−1, their on/off that top-gated devices are more effective than the back-gated
ratio has been improved by an order of magnitude. The authors ones. With this concept, mobility of up to 10–30 cm2 V−1 s−1 has
attributed the lower mobility to shorter lengths of the SWCNT been obtained.
resulting from the specific synthesis techniques which leads to Generally, SWCNTs show ambipolar nature; however,
higher number of inter-SWCNT contacts. polarity can be altered by doping with either electron donors
Large-area techniques, such as printing, has also been used or acceptors. Many groups have explored this concept to tune
for CNTs, for example, Beecher et al.[375] have used inkjet threshold voltages of FETs, and to prepare CMOS logics, ring
printing to prepare SWCNT TFTs. To counteract inkjet printer oscillators, flip flops, etc., which we discuss thoroughly in Sec-
nozzle clogging problem, the amount of SWCNTs per volume tion 5 where printed logics and circuits are discussed.
has been adjusted and the viscosity of the SWCNT inks has
been controlled to suitable values. However, the field-effect
mobility, extracted from the linear regime of the Shockley equa- 3.3. Graphene and Other 2D Semiconductors
tion, has been quite low with a value of 0.07 cm2 V−1 s−1. The
authors have attributed this to the carrier hopping between the Graphene—the 2D sheets of carbon atoms—can be regarded as
loose SWCNTs arranged in a random network. In contrast, a the most celebrated representative of a 2D class of materials,
large improvement in the mobility could be shown, when thanks to its unique physical properties.[384] These physical
SWCNTs are in direct contact to the source and drain elec- properties, such as excellent electric and heat conductivity,
trodes. In this regard, Ishikawa et al.[376] have used transfer extraordinary mechanical robustness, etc., are a direct conse-
printing to assemble thin film transistors with aligned SWCNTs quence of graphene’s geometry and character of its chemical
as channels on both flexible and rigid substrates. The aligned bonding. The graphene lattice is made of hexagons, with carbon
SWCNTs have been prepared using CVD process and transfer atoms occupying the corners, forming a honeycomb network.
printed with an adhesive tape. Most of the nanotubes here are Three carbon triangular sp2 orbitals hybridize with the nearest
bridging the source and the drain electrodes, hence, the nano- neighbors creating strong and rigid covalent bonds giving the
tube–nanotube junctions and carrier hopping could be avoided. material strength and flexibility. The remaining out-of-plane
The TFTs in this work have been prepared below 130 °C and p orbitals also do overlap, thereby leading to the formation of
have shown impressive mobility of ≈1300 cm2 V−1 s−1. This case half-filled electronic bands. The hallmark feature of the gra-
study has identified that nanotube–nanotube contacts severely phene electronic band is the appearance of charge carriers with
impeding channel conductivity and as the actual bottleneck in zero mass resulting in record carrier mobility. However, at the
the case of printed CNT FETs. same time graphene is considered as a zero-gap semiconductor
One of the major advantages and expectations of printing because its valence and conduction bands meet at the Dirac
technologies is the prospect of material deposition on flexible points.[385–387] Consequently, in the context of application of
substrates. Channels made of SWCNTs have been printed on graphene, the research community faces conflicting demands.
various materials like PET or even on clothes. Fully printed On the one hand, exceptional carrier mobility and natural
Figure 10. a) Optical image of CNT network transistors; b) demonstration of stretchabiltiy, twisted between tweezers (left), conformally wrapped
around a glass rod (right). a,b) Reproduced with permission.[382] Copyright 2014, American Chemical Society. c) Typical transfer characteristics of p-type
(blue) and n-type (red) transistors; d) IDS–VG characteristics of p-type and n-type CNT network transistors in semilog plot; e) structure and output
characteristics of CMOS NAND and NOR logic gates. Reproduced with permission.[383] Copyright 2011, American Chemical Society. f) Fully gravure-
printed SWNT TFTs on mechanically flexible PET substrates; g) variability studies with 66 SWNT TFTs; h) field-effect mobility histogram; i) optical image
showing mechanical flexibility studies; j) time and operation stability of the fully printed TFTs after 1, 10, 100, and 1000 bending cycles. Reproduced
with permission.[377] Copyright 2013, American Chemical Society.
downsizing potential promise ultrafast and energy efficient limited number of processing steps with precisely controlled
transistors, and on the other hand, the lack of a bandgap pre- deposition of materials. An illustrative example, capturing typ-
cludes the transistor from switching off or to offer a reason- ical features of printed FET with graphene-flake channel, has
able and technologically viable on–off current ratio. In order to been reported by Torrisi et al.[409] In this case, a graphene ink
work around this dilemma, scientists have followed two major has been prepared by ultrasonication (LPE) of bulk graphene in
strategies. One way is to open an energy bandgap in graphene N-methylpyrrolidone (NMP) solvent and subsequent sorting by
using processes or strategies, such as chemical doping,[388–392] centrifugation. To adjust the rheological parameters for single
oxidation,[393,394] hydrogenation,[395,396] quantum confinement droplet formation (nozzle diameter 50 µm), ethylene glycol has
(nanoribbons),[397–399] substrate induction,[400,401] etc. The been added to the solution (EG\ink = 20\80 or 80\20). The for-
second thrust has been boosted by the seminal work demon- mulated ink obtained by such a manner has been used to print
strating the first MOSFETs with single-layer MoS2[402] channel transistor channels on HDMS-treated Si/SiO2 substrate serving
that immediately opened possibility of research beyond gra- as a bottom gate. The HDMS treatment has been found nec-
phene to some rediscovered or completely novel 2D materials. essary to avoid detrimental coffee-ring formation. After fine-
To realize printed or, more generally, solution-processed tuning of other parameters—film thickness (25 nm), interdrop
digital electronics based on 2D materials, three standard distance (40 µm), and annealing temperature of 170 °C—a
development steps have to be followed. The first step entails printed graphene-channel FET has yielded a device mobility of
tailoring and optimization of the intrinsic properties of the 95 cm2 V−1 s−1 and an on/off ratio of around 10 (Figure 11).
2D component. In the case of graphene and its derivatives, In this successful attempt at graphene-channel printing, the
it includes techniques for opening of the energy gap while generic limitations of printed, purely graphene-based FETs are
simultaneously maintaining reasonable carrier mobility. In the evident. An apparent characteristic is the very low on/off cur-
second step, which is linked to the third stage by the choice rent ratio, usually much less than 10, which is an obvious con-
of a suitable printing technique, functional inks have to be sequence of the energy gap–less electronic band.
formulated. Of course, these three stages are not necessarily On the other hand, charge carrier mobility, the other most
sequential; for instance, intrinsic property optimization can important figure of merit, has been orders of magnitude lower
be performed during the ink processing or later by a targeted than in pristine, single crystal graphene; of course, there can
post-treatment of the printed elements. Presently, printing and be many potential sources of mobility degradation, such as
solution processing of 2D-based electronics is still very much most conspicuous, scattering at the flake edges, internal flake
in its infancy, primarily revolving around ink development. So imperfections, and impurities or charged defects at graphene/
far the most successful methods leading to 2D ink formula- gate-oxide interface. An example of an effort toward mobility
tion have taken advantage of a liquid-phase exfoliation (LPE) enhancement has been reported by Wang et al.[410] They have
of the pristine parent crystals.[403] LPE is a scalable, noncova- tried to reduce the intra- and internal graphene sheet carrier
lent solution-phase method that can yield significant quanti- scattering by expanding the lateral size of individual flakes
ties of defect-free 2D sheets. An exhaustive evaluation and from usual sub-micrometer scale to tens of micrometers. In
progress assessment of 2D inks has been given, for example, this particular, and in numerous similar efforts,[411] graphene
in the review article.[404] The authors have covered LPE tech- sheets have been produced from graphene oxide (GO). Usu-
niques, solution stabilization of 2D crystals, sorting methods, ally, the process starts with the synthesis of graphite oxide
and some examples of coating and printing techniques. Some using modified Hummer’s method.[412] Parent graphite oxide
typical examples of LPE ink preparation and its characteriza- contains hydroxyl and epoxide functional groups in between
tion one can be found in articles.[405–408] With regard to actual the carbon planes, thereby weakening the C intersheet bonds.
printing of FETs based on 2D materials, particularly transistors The presence of these functional groups also makes graphite
with 2D flakes as channels, there is still a lack of systematic oxide sheets strongly hydrophilic, resulting in their comfort-
progress in this area. At present it seems that the most vigor- able solubility in aqueous media. Consequently, only low-
ously followed technique is inkjet printing, which involves a energy ultrasonification is needed to exfoliate GO sheets and
Figure 11. a) Output and b) transfer characteristics of inkjet-printed graphene FET. a,b) Reproduced with permission.[409] Copyright 2012, American
Chemical Society; c) mobility enhancement of all-carbon graphene TFTs in different NaF concentrations. Reproduced with permission.[410] Copyright
2010, American Chemical Society.
form stable aqueous dispersions. GO can also be chemically wafer to form the transistor channel. In the next step, using
functionalized, for example with isocyanate, in order to make photolithography, electron-beam evaporation, and metal lift-
it soluble in organic solvents, such as dimethylformamide off processes, Au source and drain contacts have been formed.
(DMF).[413] Subsequently, these single GO sheets may later be The transistors show a very low on/off ratio of about 1.3, but
chemically reduced to graphene either directly in solution or their hole and electron mobility are of the order of 3735 and
after deposition onto a substrate. Wang et al.[410] applied careful 795 cm2 V−1 s−1, respectively, which definitely reflect the good
gradient separation and minimized the number of sonication quality of the directly exfoliated graphene flakes.
steps to avoid further breaking up of the GO flakes. The GO Summarizing it up, the efforts toward printing of field-
suspension is then printed onto the SiO2/Si substrate and the effect transistors involving graphene as the active channel
reduction to reduced graphene (rGO) is carried out at 1000 °C. component are hampered by two factors. First, there has been
In a similar manner, the drain and source electrodes made out the lack of an appreciable bandgap in graphene for which
of thickly stacked rGO sheets have been prepared. After the its usefulness as a semiconductor is severely impeded; so
optimization, mainly with regard to the conductivity and con- far there has been no report on any deliberate work aiming
tact resistance of the all carbon channel–drain–source contacts, to open graphene energy gap in printed transistors. Second,
an improvement in both hole and electron mobility (365 and there has been a conspicuous scarcity of the graphene-channel
281 cm2 V−1 s−1, respectively) has been accomplished. Yet this transistors with field-effect mobility reflecting the graphene’s
achievement is again moderated by the very low on/off current superiority.
ratio hovering barley above 1. In an interesting, but a debat- The very success in realization of an ideal 2D material, gra-
able, approach the authors have spectacularly increased car- phene, with hitherto unimaginable carrier mobility but at the
rier mobility up to 5000 cm2 V−1 s−1 and on/off ratio to 10 by same time limited semiconducting properties, has prompted
the screening of charged impurities on the SiO2 surface using research into other 2D materials. Many of them have actually
high ionic strength solution on top of the channel. The con- been reinvented, such as the well-studied family of the layered
troversy may stem from the double role of the electrolyte cov- metal dichalcogenides (MDC). Early transition metal dichalco-
ering the FET channel. On the one hand, the electrolyte may genides with stoichiometry MX2 (M = Ti, Zr, Hf, V, Nb, Mo,
screen the charged impurities enhancing the carrier mobility W; X = S, Se, Te) crystallize into structures in which the hex-
as intended; however, on the other hand, the electrolyte can agonally packed MX6 octahedra or the trigonal prisms build the
be treated as an extra, floating gate. It is clear that the charge 2D layers. The atoms forming each MX6 layer are covalently
induced in the graphene channel by the polarized floating elec- or ionically bonded with their neighbors, while the weak van
trolytic insulator has not been accounted for (i.e., the extra elec- der Waals forces connect adjacent sheets of chalcogen atoms,
trolytic capacitance has not been considered), so the mobility thereby forming the 3D crystal.[415] Here, taking advantage of
calculations may have yield grossly overestimated values. Next, the small van der Waals energies holding together the MDC
a quite indigenous method to print potentially all-carbon tran- crystals, the usual mechanical or liquid-solution–chemical tech-
sistors has been proposed, taking advantage of a coffee-ring niques could be used to exfoliate good quality single-crystal
effect, which is normally considered as a detrimental factor MDC flakes. In MDC crystals, the transition-metal d-electron
in the case of inkjet printing.[414] Again the whole fabrication states are split into two bands separated by an appreciable
process is based on the GO ink preparation and its subse- energy gap. Depending on the transition metal or, in other
quent reduction to rGO. However, in this case the transistor words, the degree of filling of the covalent d-bands, the MDC
channel, drain and source have been printed in one step; by compounds can either be a semiconductor or a metal. The
the functionalization of the substrate (Si/SiO2) and accordingly intensively investigated graphene competitors, such as MoS2,
adjusted drying processes coffee-ring patterns have been cre- MoSe2, WS2, and WSe2, are semiconductors because their
ated. The thickly stacked GO edges make a drain and source valence d-bands are completely filled. The price for their appre-
electrode while thin layer of leftover material between consti- ciable energy gaps, ranging from 1 to 2.5 eV, is their reduced,
tutes the channel. The conversion of the GO to rGO has been compared to graphene, carrier mobility. The reported mobilities
effectively performed by rapid photoreduction using intense for single MDC layers can reach values above 200 cm2 V−1 s−1 at
pulsed white lights. However, the performance characteristics room temperature.[416] However, it always takes a considerable
of the optimized transistor have shown the typical shortcom- effort to get these record numbers even in good quality atomic
ings of printed graphene; the carrier (hole) mobility is in the sheets of MDCs. For example, in the first demonstration of the
range of 10−2 cm2 V−1 s−1 and the maximum on/off ratio is of well-performing MoS2 field transistor an extra high-k dielectric
about 25. As it has been the case in other instances, it seems had to be used to screen charged impurities to boost the device’s
that the main inherent factors lowering the carrier mobility mobility from a few to 200 cm2 V−1 s−1[402] and to obtain an off/
in graphene transistors printed from graphene derivatives are on current ratio of 108. The commonly accepted origin of the
incomplete reduction of GO and formation of structural defects relatively low carrier mobility in atomically thin layers of MDC
after its reduction to rGO. In order to make a point on the is their natural vulnerability to the surface contaminations
role of the intrinsic structure quality of the printed graphene, and unintentional doping; especially detrimental effect is the
one can refer to the reports where the transistor channels Coulomb scattering from the charged impurities and defects.
have been printed using a dry transfer printing or stamping Indeed, the surface contamination and uncontrollable doping
technique. Liang et al.[85] have used a stamp to exfoliate good have upset an attempt to print a bottom-gate MoS2 transistor
quality, micrometer-sized, graphene sheets from graphite. by Li et al.[417] In this report, the solvent exchange and polymer
Then, the graphene flakes have been transferred onto a Si/SiO2 stabilization techniques, previously developed for graphene
dispersions, have been combined; small MoS2 nanosheets have suspensions of nanosheets of graphene, MoS2, MoSe2, WS2,
been exfoliated in DMF by sonication of MoS2 powders, which and WSe2 by the LPE technique. Next, the nanosheet disper-
have been then stabilized by a small amount of polymer, ethyl sions have been sprayed onto flexible substrates to form porous
cellulose (EC). Next, the solvent DMF has been exchanged with networks. Then ionic liquid has been used to provide top-gate
high-viscosity (≈40 cP at 20 °C) terpineol through distillation. transistor geometry poured onto the channel and penetrating
Mixing with ethanol, the rheology of MoS2/terpineol disper- the porous MDC flake network. This time the resultant devices
sions could be tailored to facilitate effective inkjet printing. have shown transistor characteristics with a current on/off ratio
The MoS2 flakes have been then printed on a SiO2 substrate of 103. This relatively low on/off current ratio could again be
serving as a transistor bottom gate. However, at the end, the associated with the unwanted doping resulting from the selec-
resultant on/off current ratio has been around 2 and actu- tive ion binding in ionic liquid. The estimated carrier mobility
ally the output characteristics have always shown an Ohmic of less than 1 cm2 V−1 s−1 has been attributed to the carrier scat-
behavior. The outcome of this study illustrates the inherent tering at the intersheet junctions (Figure 12).
problems of the liquid phase exfoliation, which often results in Strictly speaking the usefulness of 2D materials in printed
an unintentional carrier doping; in this case it has been p-type electronics has yet to be experimentally and practically proven;
doping even though the pristine MoS2 is typically n-type semi- definitely, there are big numbers of experimental reports
conductor. Another common problem here, which is discussed toward the development of inks based on 2D materials.
in detail in the next section, is the limited gating efficiency of There are also many examples of printed conducting passive
the traditional solid-state dielectrics, especially when it comes structures, particularly made out of graphene. However, one
to nonuniform semiconductor morphologies. Indeed, the most can certainly notice a scarcity of reasonably performing elec-
recent example of an efficient electrolyte gating approach is tronic devices, e.g., transistors, fully utilizing the advantages of
presented in the report on all-printed 2D material–based FETs 2D materials. Of course in the case of graphene there is a fun-
by Kelly et al.[418] damental impediment of its intrinsic metallicity and difficulties
In their work the authors have combined advantages of good with the controllable energy gap opening. On the other hand,
metallic conductivity of graphene and semiconducting prop- the other fundamental property of graphene, i.e., its intrinsic
erties of MDC flakes to print passive and active structures. high mobility, has yet to be harnessed, especially in solution-
The fabrication process has started with the preparation of processed network transistors. However, no doubt, one can find
Figure 12. a) 2D dichalcogenide dispersions (C ≈ 0.2 mg mL−1); b) typical scanning electron microscopy images of WSe2 nanosheets; c) conductivity
with respect to inverse temperatures; d) schematic of a TFT gated with ionic liquid 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide
(EMIm TFSI); e) examples of transfer characteristics of TFTs fabricated from WS2 and MoSe2 nanosheets; f) network mobility (µNet) plotted versus
nanosheet mobility µNS. All panels reproduced with permission.[418] Copyright 2017, AAAS.
very appealing concepts of all-printed FETs made of compatible

2D metallic (graphene, metallic MDCs) and semiconducting
MDC components, which can be all solution-processed main-
taining the high electronic performance of each component.
3.4. Silicon
Silicon, an indirect bandgap semiconductor, has naturally been

gifted with a large set of favorable properties that have made
it, by far, the most suitable choice of material for the semi-
conductor industry and CMOS technology. It is nontoxic and
abundant; easy techniques are available to extract, to purify,
and to grow large dimension single crystals. On the one hand,
the bandgap in silicon is moderate (1.12 eV) to result in a car-
rier density of only 1010 cm−3, thereby ensuring small leakage
currents; on the other hand, identical DOS of the order of
1019 cm−3 in valance and conduction bands enable heavily
doped n- and p-type variants. In addition, the maximum sol-
ubility of n- or p- type dopants in the covalent lattice are also
befittingly high, of the order of 1021 cm−3, giving rise to the fact
that the ionization (or doping efficiency) of only 1% dopants,
at the highest doping concentration, would be sufficient to fill
the available states. However, the key aspects of silicon, which
has made it the unmatched semiconductor material, is first the
excellent and natural Si/SiO2 interface, next the quality of SiO2
as the gate insulator (with low leakage and high breakdown
voltages), and most importantly, the identical mobility values
of electrons and holes have enabled realization of NMOS and
PMOS devices with similar performances, and thereby facili-
tating high gain, high speed, and low-power CMOS technology.
However, silicon crystallizes in a diamond cubic covalent lat-
tice with a high degree of directionality; therefore, it is inher-
Figure 13. High-performance transfer printed microcrystalline Si TFTs:
ently brittle and often requires high process temperatures, and
a) fT and fmax dependence on Vds and b) fT and fmax dependence on Vgs.
complex and expensive ultrahigh vacuum processing tech- a,b) Reproduced with permission.[420] Copyright 2007, AIP.
niques, in order to retain its excellent electronic properties.
Consequently, the efforts directed toward solution processing/ excellent device performance obtained via the transfer printing
printing of silicon electronics (FETs) are found to be quite method has largely been due to the precise orientation of the
laconic and isolated. Though individual groups have developed µs-Si strips in the predefined device area, thereby ensuring
distinct process technologies, widespread activities based on transport nearly within a single µs-Si strip. It would be quite
any of such process techniques have been practically absent. unlikely to obtain such preferable positioning of the µs-Si strips
One of the very interesting approaches has been proposed with any solution casting/liquid printing techniques. On the
and developed by Rogers and co-workers,[86–92,94,419] which other hand, owing to this perfect orientation of a single-crys-
involved creation of micro- or nanoscale single crystal silicon talline Si strip, the electronic transport in thus obtained TFTs
objects from silicon-on-insulator (SOI) wafers and direct phys- is in fact comparable to UHV-grown devices. Though the first
ical transfer printing of those onto predefined positions on report announced an effective mobility of 180 cm2 V−1 s−1, in
polymer substrates. In the first report, published in 2004, the the course of the research it slowly grew up to 500 cm2 V−1 s−1
authors coined the material as microstructured silicon (µs-Si). and a response speed over 500 MHz has also been demon-
In this case, the process utilized large-area lithography and strated by the same group.[90] Later, a group led by Ma[420] dem-
multiple etching steps in order to prepare transferrable single- onstrated TFTs on polymer substrate with a cutoff frequency
crystal silicon strips; the SiO2 layer of the SOI wafers have ( fT) of 2.04 GHz and a maximum oscillation frequency ( fmax) of
been used as the sacrificial layer to produce the freestanding 7.8 GHz, while using the same transfer printing of single-crys-
Si strips. In fact, as lithographically designed, any geometric talline Si stripes (Figure 13). At the next level, by incorporating
size/shape of the µs-Si material can be prepared in this manner complex substrate design processes (where individual mechani-
with smallest dimension given by the lithographic resolutions. cally neutral plans carrying the TFTs are placed parallel onto the
Although a solution casting process has also been proposed in substrate and are connected with wavy, serpentine structural
the first report,[86] by collecting a large quantity of these µs-Si configurations so that the TFTs can endure extremely large
materials, and subsequently dispersing them in a suitable sol- strain) highly foldable and stretchable silicon-integrated circuits
vent, such a process has never been demonstrated. In fact, the have also been demonstrated.[94,419] Hence, it may be stated that
the described technology is able to retain most of the advan- nanometer-sized Si nanocrystals that worsen the device perfor-
tages of silicon electronics; however, the fabrication method mance drastically. In this regard, the same has been observed
still requires large-area lithography and multiple etching steps by Shimoda et al. for laser-irradiated polycrystalline Si, as dis-
and relies on dry transfer printing. Therefore, while it is highly cussed in the last section, where an increase in the oxygen
successful in providing high-performance, easy-to-fabricate level by a factor of less than two (for example, due to a slight
flexible Si TFTs, the technology not being compatible to liquid failure to control the O2 level in the controlled atmosphere)
printing processes is not suitable for really large-area roll-to-roll in the Si matrix resulted in a fivefold decrease in the device
manufacturing/printing processes. mobility values.
Another intriguing approach has been reported by Shimoda There has also been report on gravure-printed Si-nanowire
et al., in which the so-called “liquid silicon” or a silicon pre- FETs where a substantially large value of device mobility of
cursor (cyclopentasilane) has been used to solution cast the 17 cm2 V−1 s−1 is obtained.[429] In this case, the novel concept
TFT active material.[421] Here, monomers of a hydrogenated is to disperse the silicon nanowires in a polar solvent and place
cyclic silane have been synthesized, which after long UV expo- them onto a microengraved substrate. The idea is to obtain
sure–induced photopolymerization turn into a whitish solid; an evaporation-assisted alignment of the nanowires inside the
the white solid is then dissolved in a mixture of cyclopentasi- grooves of the engraved substrate, which would then be picked
lane monomer and an organic solvent. After solution casting, up using a PDMS stamp to be placed onto a receiver substrate
it can convert into amorphous silicon (a-Si) with a curing of where the FETs are to be fabricated.
2 h at 540 °C. However, the a-Si-based TFTs show field-effect
mobility only in the 10−3 to 10−4 cm2 V−1 s−1 range, and only an
irradiation with 308 nm XeCl excimer laser converts the a-Si 3.5. Chalcogenides
to high-performance polycrystalline silicon, which can demon-
strate mobility values up to 108 cm2 V−1 s−1. Upon optimizing The most common examples of metal chalcogenides that have
the process conditions, later, superior performances could have been used in semiconductor devices are binary II–VI semi-
been demonstrated[422,423] including a relatively lower tempera- conductors (e.g., CdS, CdSe, CdTe, ZnSe, ZnS, and ZnTe),
ture (350 °C) processing on polyimide substrates and 460 and binary IV–VI semiconductors (e.g., PbSe, PbS, PbTe, SnS, and
121 cm2 V−1 s−1 electron and hole mobility, respectively. Very SnTe), and ternary or quaternary compounds, such as CdZnTe,
recently, an approach has also been aimed at where the curing HgCdTe, HgZnSe, Cu(In,Ga)Se2, etc. The partial covalent
step is completely omitted and a direct laser treatment routine nature of the bonds leads to interesting electronic properties,
is followed to convert the silane precursor directly to polysilicon for example, high electron mobility, and thus enables its uti-
on a paper substrate, thereby, allowing only 150 °C as the max- lization in various active and passive electronic components/
imum substrate temperature.[424] As a result of direct conver- devices. On the other hand, the very covalent nature also brings
sion to polysilicon at a lower maximum allowable temperature, in high directionality and makes their realization in solution-
the electrical performance of the TFTs has of course suffered processed/printed devices difficult. Though many different
considerably compared to the earlier reports. solution-processing techniques to prepare chalcogenide sheets
Next, we discuss an obvious approach to fabricate solution- have been investigated, it is to be noted that the charge car-
processed Si TFTs using presynthesized well-crystallized Si rier mobility of a fabricated sheet is largely influenced by the
nanoparticles to form a nanoink that may later be easily solu- method of its preparation.
tion cast or printed.[425–428] A typical advantage of this nano- The II–VI compounds crystallize in either zinc blend or
particulate approach is that here high process temperatures wurtzite structures with tetrahedral coordination of atoms
are often not required. In 2009, Härting et al. reported screen- reflecting strong sp3 hybridization. This covalent bonding,
printed Si nanoparticle-based TFTs with 0.3 to 0.7 cm2 V−1 s−1 however with strong ionic character, results in the formation
device mobility values. In this case, the transistors are pro- of a band structure having a direct energy gap of more than
duced on paper substrate, at room temperature, and without 1.5 eV. In contrast, the binary IV–VI compounds having crys-
any postprocessing steps.[425] However, a 20 wt% acrylic screen tallographic structure with octahedral ion coordination have
printing polymeric binder material is added to form a print- very small energy gaps in spite of their higher ionicity. Conse-
able paste, which remained along with the Si nanoparticles in quently, a wide spread of the accessible energy gaps in metal
the final device; the role of this binder material in the elec- chalcogenides facilitates bandgap engineering via solid solution
tronic transport has not been fully explained. Later, Holman mixing in ternary and quaternary compounds.
et al. reported both Ge and Si nanocrystal TFTs with device One of the first examples of solution-processed inorganic
mobility of 0.02 and 0.006 cm2 V−1 s−1, respectively[426]; while semiconductor TFTs has been from Ridley in 1999, who
Weis et al.[427] demonstrated the effect of encapsulation in con- deposited CdSe nanocrystals on SiO2 substrates.[430] The
trolling the hysteresis in Si-nanoparticulate TFTs, the reported CdSe nanocrystals are first synthesized by a metathesis reac-
mobility value in this case is no higher than 10−5 cm2 V−1 s−1 tion of Na2Se and CdI2. The whole reaction has been car-
though. Incidentally, Gresback et al.[428] have also reported ried out in pyridine, which served as a weak capping agent
identical low performance for both n- and p-doped Si for the nanocrystals and hindered agglomeration. The
nanocrystals (10−6 to 5 × 10−4 cm2 V−1 s−1). Therefore, it may nanocrystal solution is then drop coated and encapsulated by
be noted that the reports on Si nanocrystal–based TFTs have a photocurable polymer. The fabricated (at 150–350 °C) CdSe
not been highly inspiring; the main reason behind this could nanocrystal–based FETs have shown a field-effect mobility of
probably be the strong oxygen/moisture sensitivity of a few 1 cm2 V−1 s−1. Later, much higher performance devices have
been demonstrated by several groups, especially using the complexes ((N2H5)4Sn2S6 and (N2H4)3(N2H5)4Sn2Se6), which can
CBD technique. For example, Froment and Lincot[431] have be processed at or below 300 °C to assemble TFTs with semicon-
prepared CdS, ZnS, and CdSe semiconductors and Gan and ducting SnS1.8 or SnS1.5Se0.5. To circumvent the low solubility
Shih[432] have developed CdSe and CdS films. Gan and Shih of binary and ternary chalcogenides in hydrazine, an excess of
have used Na2SSeO3 and Cd(NH3)4 as precursors to form the sulfur has been added to the solution, which converts the metal
CdSe film, which is then annealed at 400 °C. The CdSe thin chalcogenides to soluble species
films prepared by this method have shown mobility values
between 5 and 15 cm2 V−1 s−1. 5N 2H4 + 2S + 2SnS2 → N2 + 4N2H5 + Sn 6S64 −
As mentioned earlier, low process temperature devices can be
prepared by using nanocrystals and chalcogenides are no excep- With this judicious trick, it has been possible to spin coat
tion to this. For example, Chung et al.[433] have demonstrated these solutions and use thermal decomposition (≈300 °C) of
high-performance devices (mobility of 10.2 and 12.8 cm2 V−1 s−1 these complexes to form continuous crystalline semiconducting
for the saturated and linear regime, respectively) at low tem- films with thicknesses down to 50 Å. The obtained mobility
peratures (maximum of 200 °C) using In2Se42− and S2− as cap- is in the range of ≈10 cm2 V−1 s−1; however, high operating
ping ligands for CdSe nanocrystals. Further improvement in voltages are required (85 V). This approach can be expanded
mobility (30 cm2 V−1 s−1), due to removal of ligands, has been to an n-channel FET using In2Se3 and higher synthesis tem-
observed after thermal curing at higher temperatures (300 °C). peratures, but reducing the operating voltages to below
CdS is the next valued member of the wide-gap semicon- 8 V,[441] and p-type FETs using a ternary CuInTe2 (mobility of
ducting materials as it shows quite high intrinsic mobility of 7.0 and 11.8 cm2 V−1 s−1 for the linear and saturated regimes,
up to 200 cm2 V−1 s−1. Hence, high-performance CdS FETs respectively).[442,443] Later, the route using hydrazine as a com-
can be obtained easily. For example, Seon et al.[434] have pre- plexing agent has been employed for synthesis of many other
pared xerogel CdS films and achieved mobility values as high semiconducting materials.[444–446]
as 48 cm2 V−1 s−1. Later, Walker et al.[435] further increased the The influence of hydrazine on semiconducting particles
mobility of CdS thin films by using cadmium thiolate that has also been explored for PbSe nanocrystals. PbSe belongs
decomposes at 300 °C into semiconducting CdS films and have to the class of thoroughly investigated IV–VI semiconduc-
shown mobility value up to 61 cm2 V−1 s−1. Nevertheless, when tors, which show ambipolar behavior depending on the treat-
exposed to air for 1 h, owing to depletion of charge carriers by ment during synthesis. For example, Talapin and Murray have
oxygen absorption, the drain current of devices has been found prepared nanocrystalline PbSe films, which after treatment
to decrease by several orders of magnitude.[436] with hydrazine have shown n-type behavior with a mobility of
Similar to CdSe, low process temperature devices using dif- 0.95 cm2 V−1 s−1. Interestingly, when the hydrazine is being
ferent precursors have been reported for CdS films as well. slowly removed, the FET switches over from n- to p-type
Kwon et al.[437] have prepared CdS films, with a complexing behavior. It may here be concluded that hydrazine helps to
agent ethylenediaminetetraacetic acid (EDTA), using the CBD reduce the interparticle distance, and can control the exchange
technique at 80 °C. In this report, TFTs are prepared at 60 °C coupling energy, Coulomb charging energy, and trap density of
process temperature; however, the obtained mobility has only the PbSe nanocrystals.[447]
been 0.1 cm2 V−1 s−1. However, when the same film is heated Ion gel gating for PbSe FETs has been introduced by
at 350 °C in air, the crystallinity of the CdS layer improved Kang et al.[448] However, the achieved electron and hole mobility
and the carrier mobility increased to 5.07 cm2 V−1 s−1. On values have been substantially low, 0.4 cm2 V−1 s−1 for elec-
the other hand, Mejia et al.[438] have used cadmium chloride/ trons and 0.02 cm2 V−1 s−1 for holes. Somewhat superior per-
sodium citrate/thiourea precursor system (maximum pro- formance has been reported by Bisri et al.[449] where ion gel
cess temperature of 100 °C) and obtained a mobility of gating resulted a mobility value of 1.91 cm2 V−1 s−1, at a pro-
7.1 cm2 V−1 s−1. Again the importance of reducing trapped cess temperature below 200 °C, which can be compatible to
oxygen in the CdS films could be shown by annealing the TFT flexible substrates. In order to investigate the p-type inorganic
in forming gas (90% N2/10% H2) at 150 °C for 1 h; after this semiconductor, Carrilo-Castilo et al.[450] developed a low-tem-
annealing step the threshold voltage has drastically decreased perature synthesis route to enhance the field-effect mobility for
to ≈2 V. Annealing in vacuum, however, has failed to decrease p-type PbS semiconductors by using the CBD method. Here,
the oxygen impurities, in fact it reduces the mobility to an annealing in forming gas at 150 °C has resulted in a car-
<1 cm2 V−1 s−1, which the authors attribute to the diffusion of rier mobility of 0.14 cm² V−1 s−1. By reducing the trap states
the trapped oxygen into the CdS–electrode interface. Later the at the interface, Nugraha et al.[451] increased the mobility to
authors refined their results by showing that the CBD method, 0.2 cm2 V−1 s−1.
based on their synthesis procedure, can produce CdS on glass
substrates, which show mobility of up to 18 cm2 V−1 s−1 even
when prepared at a low temperature of 115 °C.[439] However, 3.6. Hybrid Semiconductors
the mobility value is found to decrease to 10 cm² V−1 s−1 when
prepared on PET because of the stress exerted by the polymer In this section, printed FETs and logics (based on CMOS tech-
substrate. nologies) using hybrid semiconductors, i.e., semiconductors
A different approach to solution processing of thin film chalco- from nonidentical material class, will be discussed. Physical
genides is the usage of hydrazine as solvent for metal chalcoge- properties are material specific and defined by their chemical/
nides. Mitzi et al.[440] used hydrazine to form soluble chalcogenide electronic structure; hence, it is difficult to obtain required
properties and performance in a material class that will simulta- allotropes (either CNTs[464–468] or graphene[469]) to solution-pro-
neously be suitable for various application areas. In this regard, cessed oxide semiconductors. The idea behind such attempts is
organic materials are easily printable, can be processed at low the controlled tuning of the band structure of the oxide semi-
temperatures and possess high spatial homogeneity; however, conductors to modify/enhance their charge transport, altera-
their electronic transport properties (e.g., carrier mobility) tion in their optical properties, carrier concentration, threshold
and environmental/electrical reliability is not sufficient in voltages, etc. Moreover, the aim may include gaining somewhat
many cases for device applications. Next, the p-type variants of mechanical flexibility, at least superior to the parent materials.
organic semiconductors are considerably superior compared to In this regard, Lee et al.[464,465] have found that an addition of
the n-type ones, which results in a large performance mismatch a small amount (0.04 wt%) of SWCNTs to IGZO can improve
when they are combined in CMOS technology. On the other its carrier concentration and Hall mobility (from 6.9 for IGZO
hand, oxide semiconductors possess high intrinsic mobility, to 22.6 cm2 V−1 s−1 for the composite films). Furthermore, the
however, typically require high process temperatures and suffer same group[465,466] has reported that these composite films are
from limited mechanical strain tolerance. On top of that, be it very sensitive to UV light, due to an increase in defect densi-
crystalline or amorphous, the n-type semiconductors only dem- ties in the SWCNT part, and hence can be useful for UV-photo
onstrate band-like transport and high carrier mobility, while the detector applications. On the other hand, Liu et al.[467] have
p-type oxides inevitably possess large fraction of fairly localized used amorphous IZO with little higher amount (1 wt%) of
states and thus render poor transistor performance. SWCNTs as the channel material and have observed a tremen-
Many researchers from different groups have tried to com- dous enhancement in device characteristics (1.9 cm2 V−1 s−1
bine the strengths of different semiconductor materials from for IZO FETs vs 140 cm2 V−1 s−1 for composite IZO/SWCNT
distinct material classes into hybrid logic units and have FETs). The mechanical tests performed on these devices have
actually achieved commendable success. First of all, obvious also shown lower performance degradation compared to the
attempts have been made to integrate high performing p-type pure oxide FETs. However, owing to the use of high conducting
organics with n-type oxide semiconductors. Numerous reports IZO and relatively larger weight fraction of CNTs, the channel
illustrate successful demonstrations of organic–inorganic conductance has been high resulting in high off-currents and
hybrid logics,[452–458] however, owing to our consideration to negative threshold voltages. In order to resolve this issue, the
restrict the present review to only solution-processed inorganic same group has incorporated cations of high oxygen affinity
semiconductors, we decide not to delve deeper into the articles (e.g., Mg+2) to suppress the carrier concentration.[468] Although
reporting organic–inorganic hybrid logics. FETs based on an amorphous zinc magnesium oxide (ZMO)/
Therefore, here we would first discuss the multilayer oxides SWCNTs composite have shown a lower performance (135
that have recently attracted attention from various research cm2 V−1 s−1), compared to their previous report, however, in
groups. The concept of 2D electron gas (2DEG) that forms at this case, a positive threshold voltages with impressive sub-
a heterojunction between semiconductors of different band- threshold slope have been observed. Next, the metal oxide/gra-
gaps has also been explored for oxides.[132,459] Significantly high phene composite films (ZnO/graphene composite) have also
Hall mobility values (700 000 cm2 V−1 s−1 at cryogenic tempera- shown excellent performance (mobility of 329 ± 16 cm2 V−1 s−1)
tures) have been demonstrated for MgxZn1-xO/ZnO multilayer, and an ambipolar behavior, which the authors have ascribed to
however, these films have been processed by molecular beam the overlap of the density of states in the bandgap of ZnO and
epitaxy technique.[460] Recently, this concept has been adopted linear dispersion of single layer graphene.[469]
by Anthopoulos group for In2O3, ZnO, and Ga2O3 solution- The most striking example of hybrid CMOS logics com-
processed heterostructure transistors, which have been bining inorganic semiconductors (i.e., p-type CNTs and n-type
processed at around 180–200 °C.[461] A tenfold improvement amorphous ZTO) has been reported by Kim et al.[470] The
in the performance (25–45 cm2 V−1 s−1) has been observed authors have built fully functional solution-processed CMOS
for multilayer oxide devices (In2O3/Ga2O3/ZnO/Ga2O3/ inverters and five-stage ring oscillators with the inverter’s
In2O3) compared to the single layer oxide channel transistors signal gain over 15 and the ring oscillators’ highest oscillating
(2–5 cm2 V−1 s−1). Next, the complex fabrication process of these frequency of 714 kHz. This may be the best reported ring oscil-
multilayer devices motivated the authors to consider relatively lator performance for printed logics and the results are a direct
simpler two layer channel morphologies; following this idea outcome of matching performance of the p- and n-type semi-
In2O3/ZnO and In2O3/Li-ZnO channel FETs have also demon- conductors that have been used in this report.
strated high device mobility of 45 and 11.4 (±1.7) cm2 V−1 s−1,
respectively.[462,463] Although the actual mechanism behind the
observed high performance is still under debate, the authors 4. Gating Concepts
have floated the concept that electron transfer and confine-
ment at the interlayer interfaces, due to the conduction band Along with solution-processed/printed semiconductors, it is
offset, could be playing a crucial role. Of course, the reported equally important to be able to provide printed, defect-free,
performances are not as high as the conventional high electron gate insulators maintaining equally high-quality standards and
mobility transistors (HEMT); however, these early reports may identical process constraints, for example, low and polymer
be exciting enough to initiate further investigations in this area substrate compatible process temperatures, mechanical reli-
of solution-processed high-performance multilayer oxide FETs. ability, etc. In this section, different class of solution-processed/
Next, we focus on composite semiconductor materials printable gate insulators, i.e., dielectrics, ferroelectrics and solid
that have been prepared by adding a small quantity of carbon electrolytes, their polarization mechanisms and suitability for
solution-processed inorganic semiconductor–based FETs are the presence of residual hydroxyl groups or adsorbed mois-
discussed. ture in the films. Nevertheless, the prepared devices, with AlOx
dielectric and In2O3 semiconductor, have shown a maximum
mobility of 21.7 cm2 V−1 s−1. The lattice matching between die-
4.1. Dielectric Gating lectric and semiconductor also plays a crucial role in defining
the performance. For example, Adamopoulos et al.[483] have pre-
A dielectric material can modulate the charge carrier density pared amorphous Al2O3 and crystalline Y2O3 as gate dielectrics
at the semiconductor–dielectric interface by inducing/accumu- for ZnO FETs and found that FETs prepared with Y2O3 as the
lating additional carriers as a result of an applied electrical field. gate dielectric have shown higher performance (34 cm2 V−1 s−1)
The important prerequisites of a gate dielectric material are compared to the devices with Al2O3 (7 cm2 V−1 s−1). The obser-
high polarizability, given by the relative permittivity or dielec- vation has been explained with the notion that Y2O3 and ZnO
tric constant (K), extremely high electrical resistance ensuring lattices have very little (approximately only 10%) mismatch.
low gate leakage currents and high breakdown voltages. Die- Likewise, amorphous AlOx dielectric used for In2O3 and IZO
lectrics can be divided into different categories based on their FETs and the devices have shown mobility values of 57.2 and
polarization mechanisms, i.e., electronic, ionic and orientation 10.1 cm2 V−1 s−1, respectively.[259] In this report, once again,
polarizations; interestingly, the polarizability at higher frequen- the prepared devices have shown different mobility values for
cies are distinctly different for these polarization mechanisms, different process temperatures of AlOx, due to incomplete
for example, the cutoff frequencies of electronic and orienta- decomposition of AlOx precursor. A process temperature of
tion polarizations can be 1016 and 1010 Hz, respectively.[471–473] 400 °C is found necessary to complete the formation of AlO
Further details on polarization mechanisms and different die- bonds and to eliminate hydroxyl groups. The higher mobility
lectric materials (low-k as well as high-k) that may potentially be values have been attributed to smooth interface quality and
suitable for printed electronics can be found elsewhere.[471–477] also low trap density. On the other hand, Rim et al.[484] have
Evidently, reports on solution-processed dielectrics are fewer used a direct light patterning (DLP) technique that creates the
than the physical vapor deposited ones; what is important to required device structures and forms metal oxides (e.g., IGZO)
note here is that primarily the high-k dielectric materials, such and Al2O3 dielectric simultaneously at low temperatures (200–
as Al2O3, ZrO2, and HfO2 have been preferred as solution-pro- 350 °C) on polyimide substrates. The devices show very high
cessed gate dielectrics.[181,478–480] and it is solution-processed performances (84.4 cm2 V−1 s−1). The authors have attributed
Al2O3 (either pure or doped) that has been extensively studied this high performance to the decrease in resistances of elec-
among the above-mentioned examples. In the next paragraphs, trodes/channel, which is due to high conduction band offset of
all solution-processed, and typically all-oxide (semiconductor Al2O3 dielectric. It is to be noted that the gate voltage require-
and dielectric) FETs will be discussed. Clearly the major aspects, ment in this case has been 20–40 V, which negates the possi-
determining the device performance would be the process tem- bility of adsorbed hydroxyl ion induced ionic gating. This in
perature of the dielectrics and the semiconductors. At the same turn ensures that DLP in combination with thermal curing can
time, defect density in the solution-processed dielectric layers remove the hydroxyl groups at lower temperatures.
along with density of interfacial trap states will be considered Alumina doped with different other elements has also been
for their decisive role in the performance. used as gate dielectric. For example, zirconium-doped AlOx die-
Process temperature is found to add a different level of lectrics cured with deep UV irradiation method has yield high-
complexity to Al2O3 dielectric–gated FETs; it determines the performance devices at low process temperatures (150 °C).
composition and defect levels in this oxide. When the process Zr incorporation increased the capacitance of AlOx dielectric;
temperature is typically ≤350 °C, nitrate ions have been found however, very high concentration caused large leakage cur-
in the Al2O3 film (when processed from nitrate precursors) and rent due to mobile Zr ions in the AlOx matrix. The optimized
these ions adsorbs moisture/water, which in turn converts the concentration has been found to be 5:95 of Zr:Al ratio. In this
oxide insulator into an ionic dielectric. In effect, the ion con- work, amorphous IGZO is used as a semiconducting channel
ducting moist Al2O3 operates by forming an electric double material and the prepared devices have shown a mobility of
layer at the semiconductor interface. This results in very high 11.78 cm2 V−1 s−1.[485] Amorphous LaAlO3 films have been pre-
capacitance and extremely low gate voltage requirement. As a pared by prompt inorganic condensation method and annealing
result, the mobility values calculated with typical dielectric con- in air at 600 °C and used as a gate-dielectric material for
stant or capacitance value of Al2O3 can be erroneously high. For a-IGZO FETs. These devices show a mobility of 4.5 cm2 V−1 s−1,
example, Park et al.[481] have demonstrated high mobility values however charge traps have been observed at the interface. In
of 46.9 and 44.2 cm2 V−1 s−1 for Li-ZnO and In-ZnO FETs, this case, the dielectric films annealed at reducing atmospheres
respectively, for the devices that have been processed at 350 °C. (in N2/H2 at 300 °C) improved the performance significantly
However, at higher process temperatures (500 °C) the Al2O3 (11.1 cm2 V−1 s−1) and decreased the operating voltages, which
films are devoid of nitrate ions, and the calculated mobility can be due to the reduction in the trap density at the interface
has been found to be lower, 3.4 and 2.34 cm2 V−1 s−1, respec- and also an improvement in the capacitance value.[486]
tively. Xu et al.[482] have reported different solution-processed Solution-processed ZrO2 dielectric has been used alongside
dielectrics (AlOx, ZrOx, YOx, TiOx) for In2O3 and IZO FETs. crystalline, amorphous oxide and chalcogenide semiconductors.
The process temperature of dielectrics is 300 °C; however, the Interesting results have been reported when ZrO2 has been
capacitance measurements have shown that the dielectrics used with ZnO semiconductors.[487] For the 500 °C annealed
have frequency-dependent capacitance, which again indicates dielectric layer, the observed mobility value has only been
1 cm2 V−1 s−1, however, at lower annealing temperature (300 °C), the semiconductor. However, in this case, an overestimation in
the performance improved significantly (20 cm2 V−1 s−1). The calculated mobility cannot be ruled out, which might be linked
surprising outcome has been ascribed to the density of elec- to the erroneous estimation of the dielectric thickness owing to
tron traps in ZrO2, when annealed at lower temperatures, its diffused interface with the semiconductor.[494]
which acted as extra source of carriers for ZnO and allowed Beside oxides organic gate dielectrics have also been exten-
steady state carrier density; however, here again the presence sively used in solution-processed FETs. Poly(methyl meth-
of hydroxyl groups can be suspected.[487] Doping with suitable acrylate) (PMMA) prepared by dip coating has been used for Al-
elements can reduce the defects. Park et al.[488] have made such doped (30 at%) indium–zinc–oxide (AIZO) FETs with reported
an attempt by doping zirconium oxide with boron (9 mol%) for device mobility value as high as 26.8 cm2 V−1 s−1.[495] In the
In2O3 FETs (processed at 250 °C). Boron has been selected as a case of organic dielectric, the process temperatures are typically
dopant because it forms dense films and reduces oxygen vacan- very low; e.g., the dip coated PMMA has been cured at 100 °C.
cies, thereby reduces leakage currents and increases polariz- However, due to low dielectric constant and interfacial inhomo-
ability. The prepared FETs on silicon substrate have shown a geneity the operation voltage of organic dielectric–gated FETs
mobility value as high as 39.3 cm2 V−1 s−1. In order to reduce are found to be relatively high. The required operation voltage
processing temperatures, photonic curing methods have been for PMMA coated AIZO FETs have been 10–15 V; in addition,
considered in place of conventional thermal annealing. Liu the devices show hysteresis in the transfer curves, arising from
et al.[489] have used UV–ozone treatment, followed by thermal the charge trap states at the semiconductor–dielectric interface.
annealing at 300 °C for zirconium oxide precursor films. The Identical reports on PMMA dielectric can be found in the lit-
UV–ozone treatment reduced the decomposition temperature erature; for example, lanthanum-doped zinc tin oxide (LZTO)
of precursor as well as formed homogeneous and smooth FETs have shown a device mobility of 3.07 cm2 V−1 s−1 and an
surface; consequently, the prepared In2O3 FETs have shown on/off ratio of 104, where the operating voltage have been even
high mobility of the order of 23.6 cm2 V−1 s−1. Similarly, solu- higher (30 V),[496] for ZnO nanorod FETs on flexible PET sub-
tion-processed ZrO2 has been used as the gate dielectric for strate (processed at <150 °C), a transistor mobility of 7.5 cm2
SnO2 semiconductor FETs (processed at 400 °C). The prepared V−1 s−1 have been recorded, after an additional oxygen plasma
ZrO2 and SnO2 films have shown very low roughness values treatment. However, the operation voltage of 20 V and a high
(<1 nm) and excellent interface quality, resulting in a mobility subthreshold slope of 2 V per decade indicates that the trap
value as high as 40 cm2 V−1 s−1.[200] On the other hand, Wang states are not completely annihilated.[497]
et al.[490] have integrated spray coating and combustion method On the other hand, organic high-k dielectrics, such as self-
to prepare high-performance solution-processed FETs at low assembled monolayers (SAMs), which are monomolecular
temperatures. With this method, the authors could prepare films that can be formed spontaneously on specific surfaces,
high-quality porosity-free films and thus could achieve high have also been used as gate dielectric in solution-processed
performances. The mobility values of IZO and IGZO devices FETs. The specific advantages of these monolayer dielectrics
(processed at 300 °C), with ZrO2 dielectric, are found to be 42.5 are very high dielectric constant values coupled with monolayer
and 32.5 cm2 V−1 s−1, respectively. Next, there have been reports insulator thickness, which together reduces the gate voltage
that involved chalcogenide semiconductors. ZrO2 (processed at requirement to only a few volts; on the other hand the break-
300 °C) is used as a gate dielectric for solution-processed chal- down voltage is appreciably high for such a thin insulator layer.
cogenide (CdS)-based FETs and the devices have shown signifi- In fact, their excellent dielectric behavior stems from highly
cantly high mobility value 48 cm2 V−1 s−1. The high performance conformal coverage with very little defect density. Solution-
in this case has been correlated with an effective charge accu- processed octadecylphosphonic acid (ODPA)-based SAM has
mulation at the interface between CdS and ZrO2.[491] been used as gate dielectric for MoS2 FETs; the MoS2 tran-
Beside alumina and zirconia, another high-k dielectric that sistor channel is prepared by mechanical exfoliation, followed
has been considered is HfO2. Amorphous HfO2 dielectric pre- by transfer printing process. Owing to low trap density at the
pared by solution processes, on plastic (PET) substrates, has MoS2/SAM interface, the devices show transistor mobility
been used along with solution-processed ZnO semiconductor. as high as 11.8 cm2 V−1 s−1 and subthreshold slope as low as
The devices have been processed at a temperature of only 91 mV per decade.[498] Solution-processed composite dielec-
150 °C and have shown mobility value of 1.17 cm2 V−1 s−1. trics (AlOx-SAM, self-assembled monolayer based on ODPA)
Although processed at extremely low temperature, the high have been used along with spray deposited ZnO semiconduc-
polarizability of the HfO2 layer could actually come from the tors. Here the FETs operate at very low voltages (1.5 V) and
residual hydroxyl groups, which in fact makes the devices demonstrate mobility of 8.3 cm2 V−1 s−1.[499] High-capacitance
sensitive to environmental conditions such as humidity, tem- (1.1 µF cm−2) inorganic–organic hybrid self-assembled nanon-
perature, etc.[492] Solution-processed amorphous hafnium lan- dielectrics (Hf-SAND) made of hafnium oxide and 4-[[4-[bis(2-
thanum oxide (HfLaOx) has also been explored for ZnO FETs to hydroxyethyl)amino]phenyl]diazenyl]-1-[4-(diethoxyphosphoryl)
yield a device mobility of 1.6 cm2 V−1 s−1.[493] Another example benzyl]pyridinium bromide (PAE) has been used to gate CNT
of complete solution-processed oxide FETs have been reported FETs. In this case, the FETs show exceptionally large mobility
by Song et al.[23] In this report, solution-processed yttrium oxide as high as 137 cm2 V−1 s−1; once again, this performance
(YOx), ZnO and ITO have been used as the dielectric, the semi- can be attributed to the excellent semiconductor–dielectric
conductor and the electrode, respectively. Here, an extraordinary interface.[500] Solution-processed organic-SAND dielectrics
mobility value of 135 cm2 V−1 s−1 has been reported, and has have also been used alongside In2O3 semiconductors, and
been attributed to low trap density and coherent interface with the device performance has been compared with bottom-gate
Si–SiO2–In2O3 FETs. The SAND-gated devices have shown fully printed stretchable CNT-based TFTs and logic circuits.[501]
substantially high mobility (43.7 cm2 V−1 s−1) compared to the Notably, the addition of organic dielectric material (added to
SiO2/In2O3 FETs (0.7 cm2 V−1 s−1). The comparison of the sub- impart high mechanical strain tolerance) to the inorganic fer-
threshold slope values for SAND and SiO2 as gate dielectric roelectric nanocrystals largely reduced the polarizability of the
stands at 0.3 and 5.7 V per decade, respectively, indicating neg- composite insulator, thereby requiring gate voltage of tens of
ligible trap density for the In2O3/SAND interface, as opposed to volts to fully saturate the FETs, in both the above-mentioned
the interface of SiO2 and In2O3.[180] cases.[377,501] On the other hand, organic ferroelectric polymers
(PVDF-TrFE, poly(vinyledene fluoride trifluoroethylene)) have
also been used to gate solution-processed zinc–indium–oxide–
4.2. Ferroelectric based nonvolatile memory transistors (NMT). In this case, the
devices have shown saturation mobility and memory window
Ferroelectrics are a subgroup of noncentro symmetric piezo- values of 3.3 cm2 V−1 s−1 and 9.6 V, respectively.[503] Once again,
electric materials and possess spontaneous polarization direc- the polarization of this polymer ferroelectric has been small
tions in the absence of electric field. These materials are also compared to oxide perovskites resulting in gate voltage require-
characterized by extremely high dielectric constants resulting ment of up to 30 V.
in huge polarization values (compared to the dielectric
materials) of the order of several tens of µF cm−2 and a sub-
stantial polarization hysteresis. Consequently, FETs with fer- 4.3. Electrolyte Gating
roelectric gating can store distinct charge states without an
external power supply and this phenomenon can be exploited Electrolyte gating is an unconventional gating mechanism, how-
to realize nonvolatile memory elements, commonly known as ever, particularly popular among scientists working in the field
ferroelectric random-access memory (FeRAM). However, so far, of printed electronics. It is a concept where typically a solid/
only countable examples of solution-processed ferroelectric gate gel electrolyte is used as an electronic insulator. The specific
transistors can be found in the literature, especially when only advantages here are easy device fabrication, room temperature
inorganic semiconductor channel FETs are considered. In 2004, processability of electrolytic insulators and high polarizability
Si channel PMOS devices have been reported by Aijawa et al. of electrolytes resulting in only a few volts operation voltage.
where complex SrBi2Ta2O9 and (Bi,La)4Ti3O12 ferroelectric films When an electrolyte is used in a fashion completely analogous
are synthesized following solution-based sol–gel synthesis.[502] to the orthodox inorganic oxide dielectrics, an electrostatic cou-
A year later, ITO channel FETs with Bi4−xLaxTi3O12 gate insu- pling between the electrolyte and the semiconductor layer is
lator with maximum device mobility of 9.1 cm2 V−1 s−1 have established and used for polarization and carrier accumulation/
been reported by Miyasako and co-workers where the ferroelec- depletion. In this case, the field-effect transistor device can be
tric layer is only solution-processed and the ITO semiconductor considered comparable to a two-electrode electric charge double
layer is sputtered.[510,511] Completely solution-processed lead layer (EDL) capacitor. The nature and the potential distribu-
zirconium titanate (PZT) [Pb(Zr, Ti)O3] gate, ITO channel FETs tion across this EDL layer has been explained through different
has been reported by Shimoda and co-workers.[512–514] Here, the models, such as Helmholtz model, Gouy–Chapmann model or
FETs have been prepared on STO substrates, the gate electrode Stern model,[515–517] where the latter is probably closest to the
is composed of solution-processed LaNiO3 (LNO), followed by actual scenario. Nevertheless, when dealing with electrolytes of
PZT ferroelectric layer and at the end the ITO source/drain sufficiently high concentration, an assumption of a sharp drop
electrodes and a semiconducting ITO layer as channel material of the applied potential very close to the semiconductor–electro-
completed the bottom-gate architecture. Following the selection lyte interface, i.e., the Helmholtz model, may actually be suf-
of gate electrode having close lattice matching with the chosen ficient for most of the calculations.
ferroelectric insulator, the authors could obtain epitaxial PZT/ The semiconductor–electrolyte interface can be identical to
LNO perovskite heterostructure with excellent interface quality. the semiconductor–dielectric interface, when electrochemical
After years of process optimization, the same researchers could leakage (electron transfer across interface), i.e., the faradaic cur-
demonstrate noteworthy device performance in the form of rents can be avoided. However, there are certainly many inter-
high on/off ratio, high field-effect mobility, and improved reten- esting conceptual differences as well.
tion time of the order of 109, 7.94 cm2 V−1 s−1, and 1 d, respec-
tively.[514] Interestingly, it is also possible to note that owing A. Considerations for the DC characteristics of an electrolyte-
to extremely high polarizability (of the order of 60 µC cm−2) gated field-effect transistor:
of the ferroelectric-gate, the gate voltage requirement, in the a. In order to ensure pure/predominant electrostatic cou-
above studies, has reduced to only a few volts. Fully printed pling, it is essential that the surface/interface chemistry
SWNT network transistor with device mobility of 9 cm2 V−1 s−1, and the Faradaic currents are kept at very minimal level.
nominal performance variability and high mechanical flex- This requirement actually necessitates careful selection of
ibility is reported from the group led by Javey. Here, composite the metal and semiconductor materials with maximum
high-k (≈ 17) dielectric comprising of barium titanate (BTO) possible electrochemical inertness (in this case, they are
and poly(methyl methacrylate) has been used to polarize the called ideally polarizable electrodes); on the other hand,
fully gravure-printed FETs on PET substrates.[377] Similarly, a this in effect also imparts restrictions on maximum
recent report illustrates an elastomeric polydimethylsiloxane allowable gate or drain voltages that can be safely applied.
mixed BTO as the composite dielectric/ferroelectric to gate The selection of the supporting electrolytes has to be
judicious as well; usually strong cations and anions show B. Considerations for the AC characteristics of an electrolyte-gat-
least adsorption tendencies at the electrodes. ed field-effect transistor:
b. An electrolyte-gated FET can be considered as a two- a. Among other practices and definitions, the AC perfor-
electrode electrochemical cell (drive electrodes along with mance of MOSFET devices can be given by the cutoff
the semiconducting channel is one and the gate electrode frequency, which when the contact resistances are not
is the other), consequently the DC performance of such considered can be simplified as
devices are independent of respective position of the
electrodes; in other words, an in-plane (or side gate, or dis- µFETV (3)
fT =
placed gate) transistor geometry is also possible in the case 2π L (L + ∆L )
of electrolyte-gated FETs.[111,190,336,518]
c. The displaced gate geometries are possible for electrolyte- From the above equation, it may be inferred that the
gated FETs because unlike dielectric gating where the operation frequency of transistors is proportional to the
dipolar polarization is unidirectional, in the case of elec- field-effect mobility and drive voltages, and inversely propor-
trolytic capacitors the electric charge double layer forms tional to the channel lengths including the parasitics coming
at every metal/semiconductor surface that is in contact from the electrode/insulator overlap. Here, on the one
with the electrolyte. Consequently, an electrolyte may of- hand, for the electrolyte-gated FETs, a speed limitation may
fer 3D gating ability, which can be utilized with nonuni- arise from the maximum allowable drive voltage that can be
form/porous semiconductor materials in order to obtain applied; on the other hand, huge capacitance of the electrolytic
extremely high and tunable charge densities and output insulators (which is otherwise beneficial to lower the operation
currents. The concept and essential difference with dielec- potential to only a few volts) would render equally large para-
tric gating have been schematically depicted in Figure 14. sitic capacitance values. In fact, this formidably large electro-
This phenomenon can be exploited with high surface area lytic capacitance remains as one of the primary challenge for
semiconductor channel FETs, either using traditional electrolyte-gated printed FETs.
(horizontal) or with vertical channel geometry.[508]
b. Although the switching speed in printed FETs is decided
d. The equivalent circuit of an electrolyte-gated FET is es-
by the channel lengths, which is associated with the lim-
sentially different from a typical oxide dielectric MOS-
ited resolution of the commercially available printing
FET. In the former case, two capacitors formed at the
techniques, for the electrolyte-gated FETs, the ionic mo-
respective electrodes are in series and separated by
bility of electrolytes has also to be considered, in order to
the electrolyte’s resistance. Therefore, in order to en-
determine the highest possible AC performance. Here,
sure that the gate voltage is actually applied across the
one needs to calculate the polarization time or AC po-
semiconductor–electrolyte interface (and not consumed
larizability of an electrolytic capacitor. There have been
largely at the gate–electrolyte interface) the actual capac-
various efforts to estimate effective capacitance with
itance and thereby the size of the gate electrode must
respect to operation frequency using impedance spec-
be significantly larger than the source–drain electrolyte
troscopy studies, where typically the resistance of the
overlay area.
electrolyte has been ignored[519,520]
1
Ceff = − (4)
Im (Z ) × ω
However, in reality, at high AC frequen-

cies, a large fraction of the applied potential
may actually drop within the electrolyte due
to finite electrolyte resistance that prevails
and consequently a model that includes the
electrolyte resistance of the electrolytic capac-
itor has later been proposed by Dasgupta
et al.[336]
Im (Z )
Ceff = − 2 (5)
ωZ
Here, Figure 15 shows a classic example

of a displaced gate MOS capacitor, where the
electric double layer capacitance (Cdl) is not
Figure 14. Dielectric versus electrolyte gating; schematic shows electrolyte can offer conformal
only a function of the applied gate potential,
interface with top gate geometry and can be especially suitable for inorganic semiconductors,
which typically show irregular or rough surface/interface morphology. Panels (a) and (b) can but a larger variation in capacitance values is
be pertinent to precursor-derived semiconductor film of any sort, whereas (c) and (d) can be also observed when the operation frequency
related to situation where transistor channel is made out of nanoparticle ensembles. is varied. Hence, it is quite important to
vinyl phosphonic acid and acrylic acid, P(VPA-AA), has been

chosen.[522–526] Besides individual transistors, simple circuit
elements have also been demonstrated.[525] However, a detailed
discussion on the device performances may be out of scope of
the present review as the chosen semiconductor materials have
always been organic. Nonetheless, it may be worthy to mention
the work of Laiho et al.,[526] where it has been demonstrated
that for this class of proton conductors, in combination with
the organic semiconductor channel, the operation mechanism
of the electrolyte-gated FETs may gradually change from com-
plete electrostatic coupling to pseudocapacitance or electro-
chemical surface reaction regime to complete bulk chemistry
dominated regime depending on the applied gate potential. In
fact, an identical observation has also been reported by Frisbie,
where again for organic semiconductors, the FET operation
mode has been reported to vary from electrostatic to electro-
chemical doping.[527]
Figure 15. Measured effective capacitance of In2O3 thin film versus In the group of Frisbie, the selected solid/gel electrolyte has
different applied gate potentials at varying frequencies (0.1−1000 Hz). been a mixture of a typical ionic liquid (e.g., 1-butyl-3-methyl-
Reproduced with permission.[185] Copyright 2013, American Chemical imidazolium hexafluorophosphate, BMIM-PF6) with a triblock
Society. copolymer (e.g., poly(styrene-block-ethylene oxide-block-
styrene), PS-PEO-PS) to form a so-called ion gel.[518] In this
use EDL capacitance and saturated drain currents measured case, once again, the early works have involved organic semi-
at identical frequencies while performing the mobility calcu- conductors only,[528,529] however, later there have been reports
lations; one must be careful that any underestimation in the involving inorganic semiconductors from the same group.
calculated Cdl would result in an equally overestimated field- PbSe nanocrystal-based, ion gel–gated, ambipolar FETs have
effect mobility value. In this regard, one of the easy and correct been demonstrated, however, with modest electron and hole
practice, which has actually been adopted by multiple work- mobility (0.4 and 0.02 cm2 V−1 s−1, respectively) values.[448]
groups, would be to estimate the Cdl directly from the displace- Later on, involving p-type organic P3HT and n-type inorganic
ment current (gate current, IG) measured at the FET device ZnO, hybrid complementary circuits have been prepared that
itself.[161,191] could demonstrate the following: (1)) complementary sub-2 V
Next, a common criticism against the electrolyte gating inverters with signal gain up to 18 and quasistatic power dis-
approach has always been the involvement of ionic mobility, sipation <10 nW; (2)) five-stage ring oscillators operating at
which results in a low switching speed for the electrolyte-gated 2 kHz at 2 V supply voltage; (4)) promising operational sta-
FETs. The reservation is partially true for printed FETs where bility with continuous dynamic switching of EGT inverters
the switching frequency is also limited by their micrometer- for 22 h.[457] Very recently, ion gel–gated In2O3 FETs have also
sized channel lengths that the present-day printing technology been reported where the obtained device mobility has been
can offer. It has been estimated by Dasgupta et al.[336] that about 3.4 cm2 V−1 s−1.[111] The same group have also reported
the switching frequency of an electrolyte-gated transistor can ion gel–gated ambipolar CNT channel FETs and ring oscilla-
be of the order of 10 MHz for an electrolyte with sufficiently tors with appreciably high oscillation frequency, the details
high conductivity and layer thickness of around 100 nm. of the device operation will be discussed in the following
In accordance with this assessment, a switching speed of section.[380,530]
100 kHz, for a gate–channel distance of 10 µm, has later been Eventually, ion gel as alternate gate insulator has become
demonstrated by Nasr et al.[521] Furthermore, Ha et al.[380] have increasingly popular among researchers working on solution-
achieved a switching frequency of an ion gel–gated ambipolar processed electronics; various examples of ion gels (involving
CNT-channel inverter to be in excess of 1 MHz. In this case, different ionic liquids and block copolymers) and semi-
the same group published two consecutive articles, where conductor combinations have been reported. For example,
an improvement in switching speed has been realized with 1-ethyl-3-methylimidazolium bis(trifluoro methylsulfonyl)
a decrease in channel lengths, leaving the other factors fairly imide, EMIMTFSI ionic liquid and poly(styrene-block-
unchanged. Hence, it can be inferred that albeit the electrolyte methyl methacrylate-block-styrene), PS-PMMA-PS have been
gating approach has strict switching speed limitations around chosen along with graphene as stretchable semiconductor by
the low MHz level, nevertheless, the electrolyte gating can be Lee et al.[506] Similarly, ion gel–gated FETs with CNT.[382] or ZnO
a relevant technology for printed transistors, where switching channel[504,505,531,532] have widely been reported.
speed of FETs are anyhow restricted by the limited miniaturiza- A composite solid polymer electrolyte that is composed
tion possibilities. of a synthetic polymer, a plasticizer, a solvent and a sup-
Many groups around the world have been active in using porting electrolyte has been used in the group of Das-
printed electrolyte-gated FETs involving various genres of gupta.[185,186,190,191,336,508] The electrolyte is liquid when prepared
solid/gel electrolytes. In the group of Berggren a proton con- and printed, but transforms to solid membrane upon evapora-
ducting polyelectrolyte, which is a random copolymer of tion of excess solvent. However, owing to considerable fraction
Figure 16. Temperature-dependent transistor characteristics of CSPE-gated printed In2O3 channel FETs: a) off-current; b) on/off ratio; c) threshold
voltage; d) subthreshold slope with theoretical minimum value at every temperature; e) field-effect mobility; and f) saturated drain currents. All panels
reproduced with permission.[509] Copyright 2016, American Chemical Society.
of trapped solvent inside the dried electrolyte demonstrates Na+, K+), in beta alumina–based electrolytes have been tested
a very high ionic conductivity around 10−2 S cm−1.[336,509] The and compared.[533] A comprehensive list of different solution-
chosen channel material has typically been transparent oxide processed/printable dielectrics that have been used by the
semiconductors. In this case, on the one hand, excellent elec- researchers worldwide are summarized in Table 5, with their
tronic transport of In2O3 has been exploited to obtain FETs capacitances and required operating voltages.[501–509]
with device mobility as high as 126 cm2 V−1 s−1, as reported
by Garlapati et al.,[185] on the other hand, the 3D gating ability
of the electrolyte as the gate insulator has been fully exploited 5. Beyond Single FETs
to build nanoparticle-based, complete room temperature pro-
cessed FETs[190,191] or even a vertical field-effect transistor In the previous sections, starting from various semiconductor
(vFET) where the porous oxide semiconductor channel has materials to gating strategies, the discussions have largely been
been sandwiched between two vertically stacked drive elec- focused on performance of the fabricated transistors, especially
trodes.[508] A large temperature window of the CSPE has also concerning their device mobility values, electrical stress sta-
recently been demonstrated (Figure 16).[509] bility, etc. However, although solution-processed/printed single
In contrast to the polymeric solid electrolytes that have FETs have performed reasonably well, often quite comparable
been discussed so far, ceramic solid electrolyte gated FETs to their PVD-grown TFT counterparts, it is nonetheless essen-
have been reported by the group of Katz.[348,507,533] In the first tial to probe their circuit characteristics, when multiple FETs are
report, combining sodium-doped beta alumina as the solid combined to perform a desired task. It is particularly important
electrolytic gate insulator and solution-processed poly(3,4-eth- because often a 100% yield of working FETs with low variability
ylenedioxythiophene) poly(styrenesulphonate) (PEDOT-PSS) is required in digital circuits, which can be nontrivial objective
and indium tin oxide as solution-processed drive and gate to achieve when fully printed. In this regard, there have been
electrodes, respectively, they have reported a field-effect many both isolated and also systematic developments, specifi-
mobility as high as 28 cm2 V−1 s−1 with ZTO as the semicon- cally within the last few years, where researchers have used
ductor material.[72] The operating voltages are found to be low various inorganic semiconductor materials and their combina-
(2–4 V), as can be expected for electrolyte gating. However, tions (hybrids) to fabricate basic logic units and circuits, such
in this case, the ceramic electrolytes cannot be processed at as NAND, NOR gates, ring oscillators, flip-flops, latches, etc.
room temperature, and in fact require process temperature The examples of more complex units, such as random-access
as high as 830 °C. When the process temperature is reduced memories, radio frequency identification tags and display
to 200 °C, the mobility value partially decreases (µFET = backplanes have also been reported. In this section, we sum-
10 cm2 V−1 s−1) due to lower quality of SBA. In a subsequent marize such developments starting with selective examples of
publication, the suitability of different alkali metal ions (Li+, all-printed diodes.
Table 5. Dielectric capacitance versus associated operation voltage and transistor mobility of solution-processed/printed high-k dielectrics.
Dielectric Semiconductor Substrate Processing route Maximum process Capacitance Operation Mobility Year published
temperature [°C] [µF cm−2] voltage [V] [cm2 V−1 s−1]
High-k oxide dielectrics
ZrO2/Al2O3 IZO Si wafer Spin coating 350 0.096 3 4.5 2017[480]
Polydimethylsiloxane– SWCNT Polydimethylsi- Drop casting 150 0.028 30 4 2016[501]
BaTiO3 nanoparticles loxane
(BaTiO3/PDMS)
ZrO2 ZnO Si wafer Spray pyrolysis 300 – 2 20 2016[487]
Spin coatinga)
Zr:AlOx a-IGZO Glass Spin coating 150 0.18 10 8.6 2015[485]
AlOx In2O3 Si wafer Spin coating 300 0.194 4 57 2015[259]
a-IZO 4 10
a-LaAlO3 a-IGZO Si wafer Sputtering 600 and rean- – 20–40 11 2015[486]
Spin coatinga) nealing of LaAlO3
in 5% H2/95% N2
at 300 °C
Al2O3 a-IGZO Si wafer Spin coating 350 0.046 2 84 2014[484]
AlOx In2O3 Si wafer Spin coating 300 0.167 1.5 22 2014[482]
a-IZO 4 12
a-HfLaOx ZnO Si wafer Spin coating 500 0.19 5 1.6 2014[493]
ZrOx In2O3 Si wafer Spin coating 300 0.426 1.5 24 2014[489]
Al2O3 Li:ZnO Si wafer Spin coating 350 0.143 10 47 2013[481]
In:ZnO 44
AlOx In2O3 Si wafer Spin coating 350 0.075 3 127 2013[181]
HfO2 ZnO Si wafer Spin coating 150 0.145 20 1.2 2013[492]
ZrO2 SnO2 ITO-coated glass Spin coating 400 – 1.5 100 2013[200]
ZrO2:B In2O3 Si wafer Spin coating 200 0.09 (annealed at 10 39 (on silicon 2013[488]
Polyimide 250 °C) substrate)
0.046 (annealed at 4 (on polyimide
200 °C) substrate)
YOx ZnO Si wafer Spin coating 400 0.07 6 455 2012[494]
ZTO 500 0.07 10
ZrO2 ZTO Glass Spin coating 300 0.24 2 4 2012[479]
Y2O3 ZnO ITO-coated glass Spray pyrolysis 400 0.13 4 34 2011[30]
Al2O3 40.05 7
ZrO2 CdS Glass Spin coating 300 – 5 48 2009[491]
HfO2 SrBi2Ta2O9 Si wafer Spin coating 750 – 10 2004[502]
Organic dielectrics
PMMA a-AIZO Glass Dip coating 500 – 5 27 2013[495]
PMMA a-LaZTO Glass Dip coating 500 – 30 3 2012[496]
PMMA ZnO ITO-coated PET Spin coating 120 0.008 20 7.5 2010[497]
High-k organic dielectric
Hf-SAND SWCNT Si wafer Spin coating 150 0.01 (parallel 0.75 21 2013[500]
plate) 137
0.17 (intrinsic)
P(VDF-TrFE) a-IZO ITO-coated glass Spin coating 400 – 30 3.3 2010[503]
AlOx-SAM ZnO Glass Spray pyrolysis 500 0.45–0.6 1.6 8.3 2009[499]
Si-SAND In2O3 Si wafer Spin coating 400 – 4 44 2008[180]
Ionic liquids/ion gels
Ion gel (EMI-TFSI+ In2O3 Si wafer Aerosol-jet 400 10 0.8 11 2017[111]
PS-PMMA-PS) printing
Table 5. Continued.
Dielectric Semiconductor Substrate Processing route Maximum process Capacitance Operation Mobility Year published
temperature [°C] [µF cm−2] voltage [V] [cm2 V−1 s−1]
DEME-TFSI ZnO Bulk ZnO Spin coating 80 10 2 100 2015[504]
Ion gel (1-ethyl-3- CNT Polydimethylsi- Solution cast 8.7 2 10 2014[382]
methylimidazolium in loxane on glass and
ethyl acetate) transferred onto
PDMS
Ion gel (EMI-TFSI+ ZnO Si wafer Aerosol-jet 300 10 1 2.4 2014[452]
Ion gel(EMI-TFSI+ SWCNT Si wafer Aerosol-jet 105 1 1.25 20 2013[380]
[EMIM]-[TFSI] ZnO nanorods Si wafer Spin coating 150 7 1 9 2013[505]
Ion gel (EMI-TFSI+ Graphene Rubber Aerosol-jet Low temperature 5.2 2 422 2011[506]
Ion gel (EMI-TFSI+ CNT Polyimide Aerosol-jet 105 10 1.8 20 2010[379]
Ion gel (EMI-TFSI+ PbSe NCs Si wafer Spin coating 10 2.5 0.4 2009[448]
PS-PMMA-PS)
Solid electrolytes (ceramic)
Potassium β-alumina a-ZTO ITO-coated glass Spin coating 500 – 2 16 2013[327]
Lithium β-alumina 19.6
Sodium β-alumina a-ZTO ITO-coated glass Dip coating 600 0.5–1.6 2 18 2011[507]
Sodium β-alumina a-ZTO ITO-coated glass Dip coating 600 2 2 28 2009[305]
Solid electrolytes (polymeric)
CSPE SnO2 Si wafer Inkjet printing 550 – 1 3 2017[508]
(PVA+PC+DMSO+LiClO4)
CSPE In2O3 ITO-coated glass Inkjet printing 400 (5–7) 0.9 90–120 2016[509]
(PVA+PC+DMSO+LiClO4)
CSPE In2O3 Si wafer Inkjet printing 400 4.63 2 8.3 2015[186]
(PVA+PC+DMSO+LiClO4) CuO 3.2 2 0.22
CSPE (PVA+ PC+ DMSO+ In2O3 ITO-coated glass Inkjet printing Room temperature 4.9 1 12.5 2015[191]
LiClO4)
CSPE (PVA+DI water + In2O3 ITO-coated glass Inkjet printing 400 4.33 1 126 2013[185]
KF)
CSPE (PVA + DI water + ITO NP’s ITO-coated glass Inkjet printing Room temperature – 1 5 2012[336]
KF)
CSPE (PVA+ DI water+ In2O3 NP’s Polyethylene naph- Inkjet printing Room temperature 3.2 1 0.8 2011[222]
KF) thalate (PEN)
a)The first method is for the semiconductor and the latter one is for processing the dielectric layer.
5.1. Diodes used silicon and have reported ultrahigh frequency (1.6 GHz)
metal–insulator–semiconductor (MIS) diodes (Schottky-type)
Diodes are used in rectifiers, voltage regulators, AC/DC con- using screen printing technique with (ball milled) Si micropar-
verters, etc., and are useful for many IoT applications.[534–536] ticles. These ultrahigh frequency diodes can be used to rectify
Many researchers around the world have prepared diodes radiofrequency signals. In fact, the authors have demonstrated
using different solution-based inorganic semiconductors; for the employment of printed diodes to fabricate fully printed
example, Park et al.[534] have reported ZnO nanoparticle–based logic circuits that consists of an antenna, a diode, and an elec-
Schottky diodes, which are used in a fully printed antenna for trochromic display. Although these sets of diodes have shown
wireless power transmission at 13.56 MHz. Because the cutoff high performance, the number of printing steps and the com-
frequency of diodes depends on the mobility of semiconduc- plexity involved in the whole fabrication procedure led the
tors, ultrahigh frequencies can be difficult to achieve using authors to look for an alternative and simpler method. As a
solution-processed oxides, especially with low mobility hole result, the same group,[536] subsequently came up with an
conductors. In order to resolve this issue, Sani et al.[535] have idea of self-supported composite structure using Si particles
and nanofibrillated cellulose. The prepared composite forms a thickness of indium oxide semiconductor layer) have been used
thin film, which can later be cut and laminated onto flexible as the load. Next, Marques et al.[544] have recently demonstrated
Al electrode structures. These Schottky diodes have also shown a three-stage ring oscillator using n-type In2O3 FETs and resistor
ultrahigh cutoff frequency of 1.8 GHz and a high rectifica- combination, and have successfully demonstrated oscillation
tion ratio of 4 × 103. Besides these significant developments, frequency of the order of 350 Hz at a very low supply voltages
solution-processed diodes based on chalcogenides.[537,538] for (2 V). On the other hand, Hong et al.[159] have used a printed
photodetectors and all-oxide diodes for solar cells[539] and photo resistor with optimum resistance values, which has resulted in
detector.[540] applications have also been reported by various higher signal gain (η = 8 at a VDD of 2 V), nonetheless, the static
research groups. power consumption is relatively high due to the constant load
(resistor). In contrast, using suitable p-type FETs have led to
better results; using n-type In2O3 and p-type CuO/Cu2O FETs;
5.2. CMOS Logics signal gains of 21 and 18 (at a VDD of 1.5 V) have been achieved
for the precursor-based (using p-type CuO) and the nanoparticle-
CMOS inverters are the commonly encountered building blocks based (using p-type Cu2O) CMOS inverters, respectively.[186,191]
of logic electronics and can be widely found in digital as well The low supply voltage in all these previous examples is due to
as analog circuits. In digital applications, these inverters (NOT the use of high-capacitance electrolytic gate insulators. On the
logic gate) generate a high output for a low input voltage and other hand, high frequency operation can be possible with high-
vice versa, which defines logic 1 and logic 0, respectively.[226] quality oxide dielectrics; it has been shown by Kim et al.[189] (for
Inverters may also be prepared using unipolar FETs (either partially solution-processed IGZO FETs, where ALD deposited
n- or p-type) or using a constant (load) resistor, however, the Al2O3 served as the gate insulator) that an oscillation frequency
complementary circuits that combine n- and p-type MOSFETs of 340 kHz and a stage delay of only 210 ns is possible for a
have critical advantage, such as low static power dissipation (as seven stage ring oscillator when high-quality oxide dielectrics
either of the MOSFET remains in off state), high signal gain, and top gate device geometry is chosen.
dVout/dVin (the figure of merit of an inverter, indicates how
sharply, in terms of input voltages, it can switch between the
logic states, thereby keeping the dynamic power low) and high 5.2.2. CNT Logics
noise immunity (it defines the degree of fluctuation in input
voltages which an inverter can tolerate and still maintain a par- CNTs can be ambipolar with comparable electron and hole
ticular logic state). Next, the combination of odd number of mobility; hence, analogous to silicon, they enjoy natural advan-
inverters, connected in series, and the final output connected to tage in CMOS logic fabrication. Pristine SWCNTs typically
the feedback loop is called a ring oscillator whose output oscil- show p-type semiconductor behavior in air due to absorbed
lates between two logic states (1 and 0 or true and false). When oxygen and moisture; however, it is easy to convert them
the supplied voltage is above the threshold voltage, the ring into n-type semiconductors using different methods, such
oscillator starts to oscillate spontaneously. The oscillation fre- as chemical doping,[383,545–547] oxide encapsulations,[548] etc.
quency is inversely proportional to the number of inverters and For example, Wang et al.[545] have used chemical doping with
directly proportional to supplied voltage. The oscillation period hydrazine molecules for the conversion and consequently pre-
depends on the delay at each inverter stages. pared different logic units. The CMOS inverters have shown a
Beside inverters, the other basic logic gates are AND (high gain of 5.4 at 1 V. The authors have also demonstrated NAND
output when both inputs are high) and OR (high output when and NOR logic gates, which operated fully at per with the
at least one input is high), whereas, NAND (negative AND) truth table. On the other hand, Nouchi et al.[546] have used
and NOR (negative OR) gates are called as universal gate, and PEI and tetracyanoquinodimethane (TCNQ) as dopants to
often demonstrated by the researchers as exemplary logic units control the polarity and have varied the amount of dopants
because these two, in different configurations, can provide all to tune the threshold voltages as well. In this way, they have
possible logic operations. CMOS NAND gate is a combination obtained threshold voltage matching in the high-performance
of two NMOS (connected in series) and two PMOS (connected CMOS inverters and observed a signal gain of 20 at 4 V. The
in parallel) transistors, whereas CMOS NOR gate requires the authors have also demonstrated NAND gates. Viologen mole
same number of FETs but configured in opposite fashion. cules as dopants have shown significantly high performances,
thus Lee et al.[383] have used chemical doping using viologen
(donates electrons) for the conversion. In this case, the sym-
5.2.1. Oxide CMOS Logics metric match of the threshold voltages has resulted in a signal
gain of 45 at 2 V. Although chemical doping has been found
Solution-processed/printed logics have been reported for all- to be useful to convert p-type CNTs into the n-type ones, how-
oxide MOSFETs. Most of the initial reports have used a combi- ever, the air-stability and life time of those n-type CNT FETs
nation of two n-type FETs, where one acts as the drive transistor can be a serious concern; in this regard, Zhang et al.[548] have
and the other as a load; however, the achieved performance has used high-k oxide encapsulation method. Here the high-k oxide
been low.[499,541,542] (HfO2), during high-temperature (250 °C) deposition, desorbed
In contrast, recently, Leppaeniemi et al.[543] have reported high oxygen from the CNTs and accumulated positive fixed charges
signal gain (up to 45 at a VDD of 20 V) for all NMOS inverters, in the oxide layer, which thereby converted the p-type CNTs into
where the depletion-type In2O3 FETs (prepared by controlling the n-type. The CMOS inverter prepared in this way have shown a
gain of 8.4 at a VDD of 5 V and a noise margin of 1.8 V and have as low as 50 µs. Based on the judicious estimations, further
been found to be air stable. On the other hand, Xu et al.[549,550] optimization of channel lengths of FETs and ionic conductivity
have used ambipolar FET instead of distinct p- and n-type and of ion-gels have been performed which enhanced the operating
achieved a signal gain of 33 at 1.25 V of VDD. However, because frequency of inverters to 1 MHz. In fact, the same group have
of the ambipolar nature of the FETs, the static power dissipa- later reported[380] one order of magnitude increase in oscillation
tion has been relatively high (1 µW). The five stage ring oscil- frequency up to 22 kHz and an order of magnitude smaller
lators, prepared with these ambipolar FETs, had an operating stage delay of 5 µs with a reduction in channel lengths, para-
frequency of 1.7 kHz with a stage delay of 58.8 µs. Notably, the sitic capacitances, and by controlling the ion-gel thickness to
authors have used ALD-grown HfOx as the gate dielectric and smaller values (Figure 17).
passivation layers. A year later, Kim et al.[470] have reported one of the best
Besides, high-k oxide dielectrics, easily printable organic die- ring oscillator (five stage) performance with a oscillation
lectrics, and solid/gel electrolytes have resulted in high perfor- frequency of 714 kHz (at VDD = 8 V) and a minimum stage
mance as well. Sun et al.[551] have reported all-carbon (PMMA delay of 140 ns, which, according to our knowledge, is the
as the dielectric and semiconducting and metallic CNTs as the best report so far in the case of solution-processed devices.
channel and electrodes, respectively) ICs. The 21-stage unipolar The reasons for such a high performance are many folds, i.e.,
ring oscillator fabricated using a p-type CNT FETs, both as the use of high-k oxide dielectric (ZrO2, solution processed),
pull-up as pull-down transistor, have shown an operation fre- minimal overlap (1 µm) between the gate and source–drain
quency of 3 kHz at a VDD of −5 V with a stage delay of 7.9 ms. contacts to reduce parasitic capacitance, short channel
In contrast, Ha et al.[379] have used ion gel–gated CNTs for length (4 µm) for high cutoff frequency of FETs and also
logics. The authors have demonstrated a five-stage ring oscil- substantially matching of performance of both n- (a-ZTO)
lator with an operation frequency of >2 kHz and stage delays and p-type (CNTs) FETs.
Figure 17. a) Characteristics of seven-stage ring oscillators operating with supply voltages of 5 V (left panel) and 15 V (right panel), and demonstrating
oscillation frequencies of 45 and 341 kHz, respectively. Reproduced with permission.[189] Copyright 2012, Nature Publishing Group; b) circuit diagram
of printed five-stage CNT ring oscillators employing high-capacitance ion-gel gate dielectrics; c) the output signal of the CNT ring oscillator with a
frequency of 22 kHz and stage delays of 4.5 µs; d) frequency and stage delay of the ring oscillator with respect to supply voltage VDD. b–d) Reproduced
with permission.[380] Copyright 2013, American Chemical Society; e) circuit diagram of a five-stage ring oscillator with ZTO- and CNT-based NMOS
and PMOS TFTs; f) the output signal of the ring oscillator with oscillation frequency of 714 kHz at VDD = 8 V. e,f) Reproduced with permission.[470]
Copyright 2014, American Chemical Society.
5.2.3. Other Materials (Graphene, Silicon, and Chalcogenides) two NOT gates on a plastic substrate (PEN); its output state
changes as per input only when the clock signal is in the
Other inorganic materials such as graphene, silicon, and chal- rising-edge state, thus confirming the logic function. Further-
cogenides have also been used for logics. Li et al.[552] have made more, they have also demonstrated reset–set flip-flops.
an attempt using single layer graphene for CMOS logics. The A static random-access memory (SRAM) cell that can
top gate geometry and naturally oxidized Al2O3 as the dielec- store data when externally powered has been demonstrated
tric layer have resulted in a gain of 6 at VDD of 2 V; however, by Geier et al.[557] using CNT-based FETs. The functions of a
as graphene is a semimetal without a bandgap, the FETs have RAM include read, write, and hold capabilities. The authors have
shown poor off state, resulting in a high static power consump- used two cross coupled CMOS inverters and two individual
tion. Using microstructured Si and SAND gate dielectric Kim p-type FETs that are connected to bit lines and word lines.
et al.[553] have demonstrated unipolar NMOS inverter with a gain The fabricated SRAM have demonstrated the basic capabili-
of 4.8 at a VDD of 2 V. Interestingly, high-performance solution- ties at a supply voltage of 1.75 V with low power consumption
processed all-chalcogenide nanoparticle CMOS logics have also (maximum of 10 nW). The devices have been shown to be
been demonstrated by Yun et al.;[554,555] CMOS inverters based stable over 12 000 measurement cycles.
on p-type HgTe and n-type HgSe nanoparticles on plastic sub- An all-printed 1 bit RF tag, comprised of a printed antenna, a
strates (polyethersulfone (PES) have resulted in a signal gain of rectifier (capable of providing at least 10 V dc from a 13.56 MHz
80 at a VDD of 5 V. Subsequently, the three-stage ring oscillator RFID reader) and a ring oscillator, all placed on a plastic foil
has been demonstrated with operation frequency of 12 kHz. has been demonstrated by Jung et al.[560] They have used dif-
ferent printing techniques, such as roll-to-roll gravure, inkjet,
and pad printing to fabricate the components, for example,
5.2.4. Flip Flops, SRAMs, RFIDs, OLED Display Backplanes, etc the antenna, using silver inks, the rectifier, based on ZnO
Schottky diodes, and ring oscillators, using a combination of
Sun et al.[556] have reported unipolar CNT logics that are slightly SWCNT FETs and printed resistor loads. The printed antenna
doped with F4TCNQ to adjust the threshold voltages. The could generate 102.8 Hz clock signal when brought close to
21-stage ring oscillator operated at a frequency of 2 kHz at a the 13.56 MHz operated RFID reader. The authors have also
VDD of −4 V and a stage of delay of 12 µs. The authors have estimated the cost of this 1-bit RFID tag as 0.03 dollar/unit. On
also demonstrated first CNT-based sequential logic master-slave the other hand, fully solution-processed FETs (SWCNT based)
delay flip-flop, which shows a memory function. The master- have also been used to drive OLEDs.[381,561] and also have served
slave delay flip-flop has been prepared with eight NAND and as display backplanes (Figure 18).[558,559]
Figure 18. a) Optical microscope image of the single pixel circuit with two TFTs, one capacitor, and ITO electrode for OLED integration; b) AMOLED
display characteristics: photographs showing illumination under different VDATA. a,b) Reproduced with permission.[558] Copyright 2011, American
Chemical Society; c) Circuit schematic of flexible visible light imager; d) optical photograph of a fully fabricated imager (18 × 18 pixels); e) corresponding
2D intensity profile. c–e) Reproduced with permission.[559] Copyright 2013, American Chemical Society.
6. Challenges and Opportunities are expensive, and more importantly their toxicity aspect may
pose a restriction against their widespread use in consumer
A large variety of solution-processed/printed inorganic semi- electronics. In this regard, the incipient 2D semiconductors
conductors ranging from crystalline to amorphous oxides, have sufficiently high mobility, ambipolar carrier transport, and
chalcogenides, silicon (mostly dry transfer printed), CNTs, excellent mechanical performance at the same time.[410] There-
and newly emerging 2D semiconductors have been discussed fore, they can be ideally suitable for printed, flexible, and con-
in this review. It is to be noted that the processing and perfor- formal electronics. However, so far the development in printed
mance related challenges of this variety of materials are not 2D electronics is in its infancy.[418]
identical; however, printed electronics, which may encompass Consequently, within the short to medium future, oxide
a larger array of possible applications in not so distant future, semiconductors, especially the amorphous ones, may actu-
requiring completely different performance levels and material/ ally have the highest possibility to reach some sort of applica-
processing constraints, may actually host all of these materials tion domain. Then again, the other resilient challenge, which
for one application area or the other. Both crystalline and amor- remains as a general problem for printed electronics, irrespec-
phous oxide semiconductors have already been commercially tive of the chosen semiconductor material, is the limited min-
used at a large scale, when they are not solution processed. iaturization that is possible with fully printed devices. In this
Therefore, given the fact that they are environmentally stable, case, once again various alternative solutions of the problem
the necessary task for the printed FETs and circuits would be to have been sought after, starting from self-aligned printing[62,63]
attain certain level of electrical reliability in their functioning. to vertical device geometry,[508] etc. (Figure 19). However, given
The limitations in this case may be the requirement to anneal the fact that the speed of the FETs is actually inversely propor-
them at higher temperatures (although certain alternatives have tional to the square of printing resolution, a significant devel-
been considered, for example, approaches such as combustion opment in any large-scale additive manufacturing technique,
synthesis,[188] sol–gel on chip,[275] chemical curing,[191] etc.) and which can lead to sub-micrometer resolution regularly and
the absence of a matching p-type variant with somewhat iden- reproducibly, would be a big step forward for the whole printed
tical carrier mobility. On the other hand, CNTs enjoy ambipolar electronics community. Fortunately, there are several alterna-
behavior and the best performing solution-processed or printed tive printing approaches that have been coming up in the last
circuits (for example, ring oscillators,[379,551] SRAM,[557] and flip decade can take the printing resolution to the sub-micrometer
flops[556]) to date are either partially or fully CNT based. How- regime. Electrohydrodynamic jet printing is certainly a high-
ever, on the one hand, the sorted semiconducting nanotubes resolution printing process, although it suffers from limited
Figure 19. vFET geometry, morphology, and performance: a) the final vFET geometry after printing the CSPE gate dielectric; b) the 3D porous mor-
phology of the semiconductor channel, as obtained from the surface rendering of the reconstructed STEM tomography; c) the effect of influence of
morphology on transfer characteristics. All panels reproduced with permission.[508] Copyright 2016, Wiley.
throughput possibilities. The newly developed reverse offset still pertaining major limitations, such as high process tem-
printing, on the other hand, not only offers low micrometer peratures and limited mechanical stress tolerance, have to be
to sub-micrometer scale resolution but can also provide suffi- sorted out. On the other hand, CNT network transistors and
ciently high printing speed and volume.[80,101,114] logics can be ultraflexible and can demonstrate substantially
It may be possible to draw a general conclusion at this stage superior device performance and logic operation pushing to
that the solution-processed/printed FETs that use various inor- the 1 MHz level, which may be sufficient for medium resolu-
ganic semiconductors can offer excellent device performance, tion display backplanes. However, as has been pointed out, we
at the individual transistor level, often equally good compared would still require methods to separate semiconducting CNTs
to their ultrahigh vacuum grown counterparts. However, essen- more efficiently at a lower cost and one may also consider
tially more studies are required to prove the robustness of the using CNT composites, which may dramatically reduce the tox-
technology, their temperature, environmental stability, electrical icity threat of the 1D whiskers. At the end, the authors believe
(bias stress) stability, and operation lifetime. On the other hand, that an organized and systematic study is essential at present,
unfortunately there has traditionally been less attention from even with existing materials and inks, in order to demonstrate
the design engineers toward these emerging (beyond silicon) steady and mature circuit performance in ambient conditions
technologies, resulting in abysmally small efforts toward circuit and for a reasonable lifetime, which would certainly earn the
design and simulation. Some of these material technologies necessary confidence for this new technology from everybody
(for example, amorphous oxides) may be matured enough to in the value chain.
be investigated at a larger scale; however, there is again notable
scarcity of any small- or medium-sized printing-based found-
ries, which would be absolutely essential at the present date in Acknowledgements
order to take the technology to the next level.
The authors (R.K., H.H., S.D.) appreciate the financial support of
the Helmholtz Association under the Virtual Helmholtz Institute
VI-530. In addition, we would like to thank the following scientists for
7. Conclusions their contributions in the field and fruitful discussions: J. Aghassi of
Hochschule Offenburg; G. C. Marques, T. T. Baby, and F. von Seggern of
In this review, various solution-processing and printing tech- Karlsruhe Institute of Technology; and B. Nasr of University of Melbourne.
niques have been discussed, and a wide range of semicon-
ductor materials that can be solution processed have been
covered along with comparative highlights of their device per-
Conflict of Interest
formance. Successful logics and ICs have been presented with
performance analysis. What has not been addressed to a great The authors declare no conflict of interest.
extent, at least not for every semiconductor material discussed,
is the printable ink formulation; however, it is no doubt one of
the most important prerequisites to fabricate high-performance Keywords
FETs. In fact, alongside the development of high-performance
field-effect transistors, gating mechanisms, inorganic semiconductors,
materials (semiconductors and dielectrics), the need for high-
logic electronics, printed electronics
quality ink formulation and their high-resolution dispension
(using various printing techniques) is of utmost importance; Received: December 29, 2017
for example, easy printability without large fraction of addi- Revised: March 20, 2018
tives, nanoparticulate inks without stabilizers (or with decom- Published online: June 27, 2018
posable polymers), and precursor inks that can be cured at
very low temperatures, all these can have great technological
importance. Next are the dispensing processes, i.e., different
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Advanced Materials - 2018 - Garlapati - Printed Electronics Based on Inorganic Semiconductors From Processes and Materials

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Printed Electronics www.advmat.de

Printed Electronics Based on Inorganic Semiconductors:

proposed and investigated, where one

Although the first ever experimental demonstration of

other emerging 2D semiconductors, solution-processed qτ m qλm

Low (<0.01 m2 s−1); medium (0.01–1 m2 s−1); high (>1 m2 s−1).

ZnO-FETs with ZrO2 gate dielectric; b) output characteristics of the same

very appealing concepts of all-printed FETs made of compatible

Silicon, an indirect bandgap semiconductor, has naturally been

However, in reality, at high AC frequen-

Here, Figure 15 shows a classic example

vinyl phosphonic acid and acrylic acid, P(VPA-AA), has been

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