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MV1449
PRELIMINARY INFORMATION
DS3164 2.2

MV1449
PCM HDB3 ENCODER/DECODER
The MV1449, along with other devices in the GPS 2Mbit PCM signalling series comprise a group of circuits which will perform the common channel signalling and error detection functions for a 2.048Mbit PCM transmission link operating in accordance with the appropriate CCITT Recommendations. The MV1449 is also capable of operation at the next CCITT hierarchical bit rate of 8.448Mbit. The MV1449 circuit is fabricated in CMOS and operates from a single +5V supply with all inputs and outputs being TTL compatible. The MV1449 is an encoder/decoder for the HDB3 pseudoternary transmission code, described in Annex A of CCITT Recommendation G.703. The device encodes and decodes simultaneously and asynchronously. Error monitoring functions are provided to detect violations of the HDB3 coding, all ones detection and loss of input (all zeros detection). In addition a loop back function is provided for terminal testing.

D CLK-EC LIA Q CLK-DC RESET AIS AIS GND

1 2 3 4 5 6 7 8

16 15 14 MV 13 1449 12 11 10 9

VDD TXD2 TXD1 RXD2 LTE RXD1 CDR DV

FEATURES
s Single +5V supply. s All Inputs and Outputs TTL compatible. s HDB3 Encoding and Decoding to CCITT Recommendation G.703. s Simultaneous Encoding and Decoding. s Clock Recovery Signal allows Clock Regeneration from Incoming HDB3 Data. s Loop Back Control. s HDB3 Error Monitor. s Alarm Indication Signal Monitor. s Loss of Input Alarm. s Low Power Operation. s 2.048MHz or 8.448MHz Operation.

DG16, DP16

D CLK-EC LIA Q CLK-DC RESET AIS AIS GND

1 2 3 4

16 15 14

VDD TXD2 TXD1 RXD2 LTE RXD1 CDR DV

MV 13 1449 5 12 6 7 8 11 10 9

MP16/L
Fig. 1 Pin connections - top view

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL RATINGS
Supply Voltage Input Voltage Output Voltage -0.5V to +7V -0.5V to VDD +0.5V -0.5V to VDD +0.5V

ORDERING INFORMATION
MV1449/IG/DGAS MV1449/IG/DPAS MV1449/IG/MPES

MV1449
RXD2 RXD1

TXD1

TXD2

RESET AIS

AIS

CLK-EC

HDB3 Encoder

HDB3 Decoder, Error and AIS Circuits

Q DV LIA

VDD GND

LTE

CDR

CLK-DC

Fig. 2 Block diagram

FUNCTIONAL DESCRIPTION
High Density Bipolar 3 (HDB3) is a ternary transmission code in which the number of consecutive zeros which may occur is restricted to three, to ensure adequate clock recovery at the receiver. In any sequence of four consecutive binary zeros, the last zero is substituted by a mark of the same polarity of the previous mark, thus breaking the Alternate Mark Inversion (AMI) code. This mark is termed a violation. In addition, the first zero may also be substituted by a mark if the last mark and last violation are of the same polarity. This mark does not violate the AMI code and ensures that successive violations alternate in polarity and as such introduce no DC component to the HDB3 signal. The MV1449 consists of two main blocks, the HDB3 Encoder and the HDB3 Decoder, with the Block Diagram being shown in Fig. 2. The function of each block is now described separately. HDB3 Encoder The HDB3 Encoder is responsible for converting the incoming NRZ data into HDB3 Encoded pseudo-ternary form for transmission over a 2.048Mbit/8.448Mbit PCM link. This conversion is carried out in accordance with the HDB3 coding laws specified in CCITT Recommendation G.703, Annex A. The data to be encoded is input on the D input pin and the encoding process is synchronised to the 2.048MHz/8.448MHz clock signal being input on the CLK-EC pin. The HDB3 Encoder has two outputs, TXD1 and TXD2, which represent the HDB3 encoded PCM data stream in pseudo-ternary form. If a mark or violation is to be transmitted the output pulses high after the rising edge of clock, with the length of the pulse set by the clock high pulse width. The timing diagram of the HDB3 Encoder is shown in Fig. 3.

HDB3 Decoder The HDB3 Decoder circuit is responsible for converting the 2.048Mbit/8.448Mbit HDB3 encoded pseudo-ternary PCM data stream on its inputs, RXD1 and RXD2, into NRZ binary form to be output on the Q output pin. This conversion is carried out in accordance with the HDB3 coding laws specified in CCITT Recommendation G.703, Annex A. The HDB3 Decoder synchronously decodes the data on its RXD input pins into NRZ form under control of the 2.048MHz/8.448MHz clock being input on its CLK-DC pin. There is a 5 clock period delay between the HDB3 data being clocked in from the RXD inputs and the NRZ data appearing on the Q output. The Decoder clock must be externally regenerated from the incoming HDB3 data stream and in order to aid this clock recovery a logical OR function of the inverted HDB3 inputs is output on the CDR pin. In addition to the basic HDB3 decoding the circuit also provides three alarm outputs. The first of these alarms is DV (Double Violation) and a logic high on this output denotes that two successive violations have been received with the same polarity, thus violating the HDB3 decoding laws. The second alarm, LIA (Loss of Input Alarm), is used to denote that 11 consecutive zeros have been received on the RXD inputs. The third alarm output is AIS (Alarm Indication Signal). This output will go high if less than 3 decoded zeros have been detected in the preceding RESET AIS=1 period (i.e. between RESET AIS=0 pulses) and as such this alarm can be used to detect the CCITT Alarm Indication Signal. All the alarm circuitry as well as the decoding process is synchronised to the clock signal being input on the CLK-DC pin. The clock signal may be asynchronous with the CLK-EC signal. The timing diagrams of the HDB3 Decoder circuit are shown in Fig. 4. In addition to the normal mode of operation, a loop test mode is available for terminal testing. This mode is selected by taking the LTE (Loop Test Enable) input high. In this mode, the HDB3 encoded pseudo-ternary data outputs of the encoder block are inverted and fed back as the inputs to the decoder block, which in turn decodes this data and outputs it in NRZ form.

MV1449
CLK-EC D TXD1
4.5 Clock Periods

B B
Notes:-

B B V

TXD2

1) The Encoded HDB3 outputs, TXD1/2 are delayed by 4.5 clock periods with respect to NRZ DATA IN. 2) B is a HDB3 mark, V is a HDB3 violation. 3) The diagram assumes the last mark occured on TXD2, the last violation on TXD1.

Fig. 3 HDB3 Encoder waveforms

RXD1 RXD2 CDR CLK-DC Q

B B

V B

B B

B B

5 Clock Periods

Notes:-

1) The Decoded NRZ output is delayed by 5 clock periods with respect to the HDB3 inputs. 2) The diagram assumes the last violation occured on RXD2. 3) B is HDB3 mark, V is a HDB3 violation. Decoder waveforms

RXD1 RXD2 CLK-DC DV

B B

V B

V B

1 Clock Period

Notes:-

1)There is a single period delay between detection of an error and the rising edge of DOUBLE VIOLATION 2) The diagram assumes the last violation occured on RXD2. 3) B is HDB3 mark, V is a HDB3 violation.

HDB3 Double violation waveforms

RXD1 RXD2 CLK-DC LIA

1 Clock Period

Note:-

1)The 'LOSS OF INPUT' is delayed by a single clock period with respect to the incoming HDB3 waveforms.

Loss of input violations

CLK-DC Q RESET AIS AIS

AIS and RESET AIS waveforms

Fig. 4 HDB3 Decoder waveforms

MV1449
PIN DESCRIPTIONS
Pin Name D Pin no. 1 Pin description NRZ Data Input pin to HDB3 Encoder. The NRZ binary data on this pin is input to the HDB3 Encoder for conversion to HDB3 pseudo-ternary form under control of the CLK-EC signal. The D input is latched into the Encoder block by the falling edge of CLK-EC. 2.048MHz/8.448MHz Clock Input to HDB3 Encoder. The clock signal on this input pin is used for the encoding of data on pin 1. Loss of Input Alarm Output from HDB3 Decoder. This output goes high one period after the detection of 11 consecutive zeroes on the RXD inputs. Any HDB3 mark on the inputs (RXD1 or RXD2=0) resets this output low after a single clock period delay. NRZ Data Output from HDB3 Decoder. This output represents the HDB3 input data decoded back into NRZ binary form, with a 5 clock period delay from the HDB3 inputs to the NRZ output. This decoding process is carried out under control of the CLK-DC signal. 2.048MHz/8.448MHz clock Input to HDB3 Decoder. The clock signal on this pin is used for the decoding of data on the RXD input pins, or the TXD pins in Loop Test Mode. This pin is used to input the externally regenerated clock signal recovered from the incoming HDB3 waveforms back to the Decoder block. Reset AIS Input to HDB3 Decoder. A logic 0 on this input resets a decoded zeros counter in the HDB3 Decoder. It will also reset the AIS output to 0 provided 3 or more zeros have been decoded in the preceding RESET AIS=1 period, or set AIS to 1 if less than 3 zeros have been decoded in the preceding RESET AIS=1 period. This may be used to detect the CCITT Alarm Indication Signal. A logic '1' on this pin enables the decoded zeros counter. Alarm Indication Signal Output from HDB3 Decoder. See description for RESET AIS pin. Digital Ground. 0V Double Violation Alarm Output from HDB3 Decoder. This output goes high for one period of CLK-DC, one period after the detection of a HDB3 violation of the same polarity as the previous HDB3 violation. Clock Recovery Output from HDB3 Decoder. This pin is used to output the logical OR function of the inverted HDB3 inputs for the use of the external clock recovery circuit.

CLK-EC

LIA

CLK-DC

RESET AIS

AIS

GND DV

8 9

CDR

10

MV1449
PIN DESCRIPTIONS (continued)
Pin Name RXD1 Pin no. 11 Pin description HDB3 Encoded Input 1 to HDB3 Decoder. This is one of the pair of 2.048Mbit pseudo-ternary HDB3 encoded PCM data stream inputs to the HDB3 Decoder. This input asynchronously latches the incoming HDB3 data and is falling edge sensitive. Since the input is asynchronously latched it is not necessary for the RXD pulse to straddle a rising clock edge. Loop Test Enable Control Input. A logic low on this pin selects normal operation, with encoding and decoding being independent and asynchronous. A logic high on this pin internally connects TXD1 to RXD1 and TXD2 to RXD2. Note that in loop back mode, a decoder clock must be supplied (or regenerated from CDR) along with the encoder clock. HDB3 Encoded Input 2 to HDB3 Decoder. See description for pin RXD1. HDB3 Encoded Pseudo-Ternary Output 1 from HDB3 Encoder. The NRZ PCM data stream being input on the D pin is HDB3 encoded and output on this pin and pin TXD2. This output is always low during the low half cycle of clock and is only high during the high half cycle of clock if a mark is to be output. There is a 4.5 clock period delay from the falling edge of CLK-EC to TXD1. HDB3 Encoded Pseudo-Ternary Output 2 from HDB3 Encoder. See Pin TXD1 description. Digital Supply Voltage. 5V

LTE

12

RXD2 TXD1

13 14

TXD2

15

VDD NOTES

16

1. All inputs have 100K on-chip pull down resistors.

MV1449
ELECTRICAL CHARACTERISTICS
Test Conditions: Supply Voltage VDD = 5V 0.5V Ambient Temperature Tamb = -40C to +85C

STATIC CHARACTERISTICS
Characteristic Symbol Min Low Level Input Voltage High Level Input Voltage Low Level Output Voltage High Level Output Voltage VIL VIH VOL VOHT VOHC Input Leakage Current Supply Current IIL IS 2.4 VDD1.0 -10 200 5 0.0 2.0 Value Typ Max 0.8 VDD 0.4 V V V V V Isink=2mA Isource=2mA Isource=lmA Units Conditions

uA mA

VIN=VDD or VSS 2.048MHz Operation, Note 1. 8.448MHz Operation, Note 1. All Inputs All Outputs

15

mA

Input Capacitance Output Capacitance NOTES

CIN COUT

5 5

pF pF

1. All supply currents measured with outputs unloaded.

MV1449
DYNAMIC CHARACTERISTICS
Note: Two sets of dynamic characterisitics are supplied, for use over the Commercial and Industrial Temperature ranges. The parameter set for the Commercial temperature range is aimed at customers wishing to switch from either the MJ1440 or MV1448 devices to the MV1449 since both the older devices were specified over the Commercial temperature range. Test Conditions: Supply Voltage VDD = 5V 0.5V Ambient Temperature Tamb = 0C to +70C Characteristic Symbol Min Value Typ Max Units Conditions

CLOCK
Clock Period Clock Rise/Fall Time Clock High/Low Time tCP tCR/tCF tCH/tCL 30 100 20 ns ns ns See Fig. 5 See Fig. 5 See Fig. 5

ENCODER
Encoder Data Setup Time Encoder Data Hold Time TXD1/TXD2 Output Propagation Delay tEDS tEDH tEPDR/ tEPDF 15 15 45 ns ns ns See Fig. 6 See Fig. 6 See Fig. 6, Note 1.

DECODER
RXD1/2 Data Setup Time RXD1/2 Pulse Width CDR Propagation Delay tRS tRW tCPDR/ tCPDF tOPD tRAHO tRAW tRAS tAPD 15 15 10 45 15 20 40 ns ns ns See Fig. 7 See Fig. 7 See Fig. 7, Note 1.

Decoder Output Propagation Delay. RESET AIS Hold-Off Time RESET AIS Pulse Width Reset AIS Setup Time AIS Propagation Delay

45

ns

See Fig. 7, Notes 1 and 2. See Fig. 7 See Fig. 7 See Fig. 7 See Fig. 7, Note 1.

ns ns ns ns

MV1449
Test Conditions: Supply Voltage VDD = 5V 0.5V Ambient Temperature Tamb = -40C to +85C Characteristic Symbol Min Value Typ Max Units Conditions

CLOCK
Clock Period Clock Rise/Fall Time Clock High/Low Time tCP tCR/tCF tCH/tCL 35 100 20 ns ns ns See Fig. 5 See Fig. 5 See Fig. 5

ENCODER
Encoder Data Setup Time Encoder Data Hold Time TXDl/TXD2 Output Propagation Delay tEDS tEDH tEPDR/ tEPDF 20 20 50 ns ns ns See Fig. 6 See Fig. 6 See Fig. 6, Note 1.

DECODER
RXD1/2 Data Setup Time RXD1/2 Pulse Width CDR Propagation Delay tRS tRW tCPDR/ tCPDF tOPD tRAHO tRAW tRAS tAPD 15 20 15 55 20 25 45 ns ns ns See Fig. 7 See Fig. 7 See Fig. 7, Note 1.

Decoder Output Propagation Delay. RESET AIS Hold-Off Time RESET AIS Pulse Width Reset AIS Setup Time AIS Propagation Delay

50

ns

See Fig. 7, Notes 1 and 2. See Fig. 7 See Fig. 7 See Fig. 7 See Fig. 7, Note 1.

ns ns ns ns

NOTES 1. All output propagation delays are measured with a 50pF load. 2. The tOPD parameter applies to outputs Q, LIA and DV, but does not apply to AIS.

MV1449

tCH tCR tCF

tCL

CLK-EC/ CLK-DC
tCP

VIH VIL

Fig. 5 Clock timing parameters

CLK-EC
tEDS tEDH

VIH VIL

D
tEPDR tEPDF

VIH VIL

TXD1/TXD2

VOHT VOL

Fig. 6 Encoder timing parameters

tRW VIH VIL tCPDR tCPDF VOHT VOL tRS

RXD1/RXD2

CDR

CLK-DC
tOPD

VIH VIL

D/LIA/DV
tRAHO tRAW tRAS

VOHT VOL

RESET AIS
tAPD

VIH VIL

AIS

VOHT VOL

Fig. 7 Decoder timing parameters

MV1449

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