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The document provides an overview of Verilog, covering various topics such as data types, port connections, abstraction levels, hierarchical modeling, and system tasks and functions. It includes examples of code snippets demonstrating the use of different data types like integer, reg, and real, as well as the syntax for assigning values to variables. Additionally, it discusses the functionality of system tasks like $display and $monitor, along with the concept of clock generation and procedural blocks.

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numamahesh12345
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Download as TXT, PDF, TXT or read online on Scribd
4 views

Notes

The document provides an overview of Verilog, covering various topics such as data types, port connections, abstraction levels, hierarchical modeling, and system tasks and functions. It includes examples of code snippets demonstrating the use of different data types like integer, reg, and real, as well as the syntax for assigning values to variables. Additionally, it discusses the functionality of system tasks like $display and $monitor, along with the concept of clock generation and procedural blocks.

Uploaded by

numamahesh12345
Copyright
© © All Rights Reserved
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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o verilog

datatypes
literls
port connection
abstraction levels
heirachical modeling
system task and function
compile directives
task and function
clock generation
fork join
looping constructs
scalars and vectors
arrays
prodecdural blocks
delays constructs
primitives
operators
events

o datatypes
integer, reg , wire ,real, time ,realtime,tri wand wor

o reg [7:0]a;
integer b;

intital begin
a=-12 ;
b=-12 ;
$display(" a=%0d b=%0d ",a,b);
end

o real
DEAFULT SIZE - 64

ex:
module top;
real a;
real b ;
real c;

initial begin
a=10;
b= 3.0 ;
c=a/b; //
$display(" reuslt c=%0f ",c);//3.00
end
endmodule
time and realtime datatypes
which can able to store the current time in the varaibles

regarding thes we have system functions , $time and $realtime

o tri a ;

module top;
tri a;
reg b ;
assign a=b?1'b1: 1'bz ;
endmodule

o real a;
a='d10;//2 ,10

o decalre a variable which stores the N no of alphabets in it ?

reg [N*8-1:1] a;
a = NAME;
a ="NAME";

in genral what syntax for the asssiging value to variable

variable = <SIZE>'<RADIX><VALUE>;

ex:
reg [3:0]a;
//asssign value in octal
a=4'o1010;
//asssign value in hexa
a=4'ba;/wrong
a=4'ha;
a= 'ha;
a= 'h1;

o port connection

three types of ports connection


- input - ouput - inout

the ports indicatws the direction of the signal

o what is the default data type of input port ?


- wire

o what is the default data type of ouput port ?


- wire

o abstraction levels

o bheviuoral level - algorithm (truth tables) / circuit daigram


o data flow - boolean expression
o structal level - logical gates
o switch level - transsiter level (cmos/pmos /nmos)

o heirarical modeling
implemeting bigger modules usin g smaller module

Q. 7x1 mux using 2x1 is possible?


-YES
o how many 2x1 mux required ?

ex:
module tri(
input en;
input data_i;
inout data_o;
);
assign data_o=en? data_i:1'bz;
endmodule

o system task and system function

system task
o $display,$monitor,$write,$strobe,$value$plusargs,$finish,$stop

o $display,$monitor,$write,$strobe
- all are used to print hte display statements

$display - executes only once and prints the statements


for every next print ,give new display in
next line

$monitor - executes when ever the variables changes the values


comapored to precvious prints .then only prints the statements
for every next print ,give new display in next
line

$write - executes only once and prints the statements


for every next print, happnes in same line
$display= $write + \n

$strobe - executes only once in simulation


statemenst prints at end of the
time step

ex:
initial begin
a=100;
$strobe(" a=%0d ",a);//100
#1;
$strobe(" a=%0d ",a);//200
a=200;
#2;
$display(" a=%0d ",a);//200
end

o system function
- $time ,$realtime,$random,$urandom ,$urandom_range

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