UNIT-IV Digital Electronisc
UNIT-IV Digital Electronisc
UNIT-IV Digital Electronisc
Difference between analogue and
Digital signals
Analog signal more prone to noise
Analog signal has complete information
Digital signal can produce approximate information.
Processing tool for digital signal are available.
Mathematical operations become simple
Number Systems and Binary
Arithmetic
Most number systems are order dependent
Decimal
123410 = (1 103) + (2 102) + (3 101) + (4 100)
Binary
11012 = (1 23) + (1 22) + (0 21) + (1 20)
Octal
1238 = (1 82) + (2 81) + (3 80)
Hexadecimal
12316 = (1 162) + (2 161) + (3 160)
here we need 16 characters – 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
Number conversion
S L
OPEN OFF
CLOSED ON
S L
0 0
1 1
A simple binary arrangement
A truth table
A binary arrangement with two switches in series
L = S1 AND S2
A binary arrangement with two switches in parallel
L = S1 OR S2
Three switches in series
L = S1 AND S2 AND S3
Three switches in parallel
L = S1 OR S2 OR S3
A series/parallel arrangement
00=0 0+0=0 0 1
01=0 0+1=1 1 0
10=0 1+0=1 A A
11=1 1+1=1
A0=0 A+0=A
0A=0 0+A=A
A1=A A+1=1
1A=A 1+A=1
AA=A A+A=A
A A 0 A A 1
Boolean Algebra
1. x+0=x 2. x1=x
3. x+1=1 4. x0=0
5. x+x=x 6. xx=x
7. x + x’ = 1 8. x x’ = 0
9. (x’)’ = x
10. x+y=y+x 11. xy = yx Commutative
12. x + (y + z) = (x + y) + z 13. x(yz) = (xy)z Associative
14. x(y + z) = xy + xz 15. x + yz = (x + y)(x + z) Distributive
16. (x + y)’ = x’y’ 17. (xy)’ = x’ + y’ DeMorgan’s
We can now start doing some simplifications
1. x + xy = x 4. x(x + y) = x
2. xy + xy’ = x 5. (x + y)(x + y’) = x
3. x + x’y = x + y 6. x(x’ + y) = xy
xy + x’z + yz = xy + x’z (x + y)(x’ + z)(y + z) = (x + y)(x’ + z)
1.xy + x’z + yz = xy + x’z
2.(x+y)•(x’+z)•(y+z) = (x+y)•(x’+z) -- (dual)
Proof:
xy + x’z + yz = xy + x’z + (x+x’)yz
= xy + x’z + xyz + x’yz
= (xy + xyz) + (x’z + x’zy)
= xy + x’z
1. Prove that : xy + x’z + yz = xy + x’z
Proof:
xy + x’z + yz = xy + x’z + (x+x’)yz
= xy + x’z + xyz + x’yz
= (xy + xyz) + (x’z + x’zy)
= xy + x’z
Prove that: (x+y)•(x’+z)•(y+z) = (x+y)•(x’+z)
1. Prove that AB+A’C = (A+C) (A’+B)
2. AB’C + A’C +B + BD’ + ABD’ = B + C
Boolean laws
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Examples of K-Maps:
Examples:
Cell numbers are written in the cells.
2-variable K-map
B
A 0 1
0 0 1
1 2 3
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3-Variable K-Map:
3-variable K-map
BC
A 00 01 11 10
0 0 1 3 2
1 4 5 7 6
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4-variable K-map
4-variable K-map
CD
AB 00 01 11 10
00 0 1 3 2
01 4 5 7 6
11 12 13 15 14
10 8 9 11 10
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STORAGE ELEMENTS:
Maintain a binary state indefinitely as long as power is
delivered to the circuit
Latches: Binary state changes with signal levels: Level
Triggered
Flip-flops: Binary state changes with signal transitions:
Edge Triggered
S-R Latch
•The latch
-holds (stores) when S = R = 0
-is set (to 1) by bringing S = 1 with R = 0
-is reset (to 0) or cleared by bringing R = 1 with S = 0
•The condition S = R = 1 must be avoided because it leads to an
indeterminate condition, where the output can not be predicted
at any one point in time. This can cause a race condition to
occur when the inputs change to S = R = 0.
Latches: SR Latch with NOR gates
NOR Latch: Active High Inputs NAND Latch: Active Low Inputs
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SR Latch with Control (Enable) Input
The operation of the basic SR latch can be modified by
providing an additional control input that determines when
the state of the latch can be changed. It consists of the basic
SR latch and two additional NAND gates.
Symbol:
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D-Latch and Symbol:
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Flip-Flops
The state of a latch or flip-flop is switched by a change in
the control input. This momentary change is called a trigger
and the transition it cause is said to trigger the flip-flop. The
D latch with pulses in its control input is essentially a flip-flop
that is triggered every time the pulse goes to the logic 1
level. As long as the pulse input remains in the level, any
changes in the data input will change the output and the
state of the latch.
Clock Response in Latch
CLK 1 0 1 0 1 0
D 110011…
Y 110011…
Q ? 1 1 0 0 1 ….
Graphic Symbol for Edge-Triggered D Flip-Flop
JK Flip-Flop
There are four operations that can be performed with a flip-flop: set it to 1, reset it
to 0, no change, complement its output. The JK flip-flop performs all four
operations. The circuit diagram of a JK flip-flop constructed with a D flip-flop and
gates.
Q=J.Q’+K’.Q
Operation...
Q=J.Q’+K’.Q
JK Flip-Flop
The J input sets the flip-flop to 1, the K input resets it to 0, and when both inputs are
enabled, the output is complemented. This can be verified by investigating the
circuit applied to the D input:
D = J Q` + K` Q
T (Toggle) Flip-Flop
The T flip-flop is a complementing flip-flop and can be obtained from a JK flip-
flop when inputs J and K are tied together.
T Flip-Flop
The T flip-flop can be constructed with a D flip-flop and an exclusive-OR gates
as shown in Fig. (b). The expression for the D input is
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