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UNIT-IV Digital Electronisc

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Digital Electronics

 Number systems (Decimal, Binary)


 Boolean algebraic theorems
 Logic gates
 Implementation of Boolean expressions using logic gates
 Basics of Flip-flops and its applications.
Introduction
 4 types of signals
 1—continuous time-continuous amplitude
signal

 2 -- continuous time-discrete amplitude


signal(digital signal—binary signals)

 3--- Discrete time-continuous amplitude signal

 4--- Discrete time-Discrete amplitude signal


Difference between analogue and
Digital signals
 Analog signal more prone to noise
 Analog signal has complete information
 Digital signal can produce approximate information.
 Processing tool for digital signal are available.
 Mathematical operations become simple
Number Systems and Binary
Arithmetic
 Most number systems are order dependent
 Decimal
123410 = (1  103) + (2  102) + (3  101) + (4  100)
 Binary
11012 = (1  23) + (1  22) + (0  21) + (1  20)
 Octal
1238 = (1  82) + (2  81) + (3  80)
 Hexadecimal
12316 = (1  162) + (2  161) + (3  160)
here we need 16 characters – 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
Number conversion

 conversion Binary to decimal


 add up decimal equivalent of individual digits
Example –
Convert 110102 to decimal
110102 = (1  24) + (1  23) + (0  22) + (1  21) + (0  20)
= 16 + 8 + 0 + 2 + 0
= 2610
Decimal to Binary
 repeatedly divide by the base and remember the remainder
Example –
Convert 2610 to binary
Number Remainder
Starting point 26
2 13 0
2 6 1
2 3 0
2 1 1
2 0 1
read number from this end
=11010
Binary Quantities and Variables
 A binary quantity is one that can take only 2 states

S L
OPEN OFF

CLOSED ON

S L
0 0
1 1
A simple binary arrangement
A truth table
 A binary arrangement with two switches in series

L = S1 AND S2
 A binary arrangement with two switches in parallel

L = S1 OR S2
 Three switches in series

L = S1 AND S2 AND S3
 Three switches in parallel

L = S1 OR S2 OR S3
 A series/parallel arrangement

L = S1 AND (S2 OR S3)


 Representing an unknown network
Logic Gates
 The building blocks used to create digital circuits are
logic gates
 There are three elementary logic gates and a range of
other simple gates
 Each gate has its own logic symbol which allows
complex functions to be represented by a logic diagram
 The function of each gate can be represented by a
truth table or using Boolean notation
 The AND gate
 The OR gate
 The NOT gate (or inverter)
 A logic buffer gate
 The NAND gate
 The NOR gate
 The Exclusive OR gate
 The Exclusive NOR gate
Boolean Algebra
 Boolean Constants
 these are ‘0’ (false) and ‘1’ (true)
 Boolean Variables
 variables that can only take the vales ‘0’ or ‘1’
 Boolean Functions
 each of the logic functions (such as AND, OR and NOT)
are represented by symbols as described above
 Boolean Theorems
 a set of identities and laws.
 Boolean identities

AND Function OR Function NOT function

00=0 0+0=0 0 1
01=0 0+1=1 1 0
10=0 1+0=1 A A
11=1 1+1=1
A0=0 A+0=A
0A=0 0+A=A
A1=A A+1=1
1A=A 1+A=1
AA=A A+A=A
A A  0 A  A 1
Boolean Algebra
1. x+0=x 2. x1=x
3. x+1=1 4. x0=0
5. x+x=x 6. xx=x
7. x + x’ = 1 8. x  x’ = 0
9. (x’)’ = x
10. x+y=y+x 11. xy = yx Commutative
12. x + (y + z) = (x + y) + z 13. x(yz) = (xy)z Associative
14. x(y + z) = xy + xz 15. x + yz = (x + y)(x + z) Distributive
16. (x + y)’ = x’y’ 17. (xy)’ = x’ + y’ DeMorgan’s
 We can now start doing some simplifications

 x’y’ + xyz + x’y


 = x’(y’ + y) + xyz [ Distributive; x’y’ + x’y = x’(y’ + y) ]
 = x’1 + xyz [ Axiom 7; y’ + y = 1 ]
 = x’ + xyz [ Axiom 2; x’1 = x’ ]
 = (x’ + x)(x’ + yz) [ Distributive ]
 = 1  (x’ + yz) [ Axiom 7; x’ + x = 1 ]
 = x’ + yz [ Axiom 2 ]
Here are some more useful laws.

1. x + xy = x 4. x(x + y) = x
2. xy + xy’ = x 5. (x + y)(x + y’) = x
3. x + x’y = x + y 6. x(x’ + y) = xy
xy + x’z + yz = xy + x’z (x + y)(x’ + z)(y + z) = (x + y)(x’ + z)
1.xy + x’z + yz = xy + x’z
2.(x+y)•(x’+z)•(y+z) = (x+y)•(x’+z) -- (dual)
Proof:
xy + x’z + yz = xy + x’z + (x+x’)yz
= xy + x’z + xyz + x’yz
= (xy + xyz) + (x’z + x’zy)
= xy + x’z
1. Prove that : xy + x’z + yz = xy + x’z
 Proof:
xy + x’z + yz = xy + x’z + (x+x’)yz
= xy + x’z + xyz + x’yz
= (xy + xyz) + (x’z + x’zy)
= xy + x’z
Prove that: (x+y)•(x’+z)•(y+z) = (x+y)•(x’+z)
1. Prove that AB+A’C = (A+C) (A’+B)
2. AB’C + A’C +B + BD’ + ABD’ = B + C
 Boolean laws

Commutative law Absorption law


AB  BA A  AB  A
AB  B  A A(A  B)  A

Distributive law De Morgan’s law


A(B  C)  AB AC A  B  AB
A BC  ( A B)(A C) AB  A  B

Associative law Note also


A(BC)  (AB)C A  AB  A  B
A  (B  C)  (A  B)  C A(A  B)  AB
DeMorgan’s Theorem
( A  B )  A.B
A.B  A  B
Combinational Logic
 Digital systems may be divided into two broad
categories:
 combinational logic
 where the outputs are determined solely by the current states
of the inputs
 sequential logic
 where the outputs are determined not only by the current
inputs but also by the sequence of inputs that led to the
current state
 Implementing a function from a Boolean expression
Example – X  A  BC
Implement the function
 Implementing a function from a Boolean expression
Example – Y  AB  C D
Implement the function
 Generating a Boolean expression from a logic
diagram
Example (continued)
– work progressively from the inputs to the output adding
logic expressions to the output of each gate turn
 Implementing a logic function from a description
Example –
The operation of the Exclusive OR gate can be stated as:
“The output should be true if either of its inputs are true,
but not if both inputs are true.”
This can be rephrased as:
“The output is true if A OR B is true,
AND if A AND B is NOT true.”
We can write this in Boolean notation as
X  (A  B)  (AB)
Example (continued)
The logic function
X  (A  B)  (AB)
can then be implemented as before
 Implementing a logic function from a truth table
Example –
Implement the function of the following truth table
A B C X – first write down a Boolean
0 0 0 0 expression for the output
0 0 1 1
0 1 0 0
– then implement as before
0 1 1 0 – in this case
1 0 0 0
X  A BC  ABC  ABC
1 0 1 1
– By looking at when X=1
1 1 0 1
1 1 1 0
Example (continued)
The logic function X  A BC  A BC  ABC
can then be implemented as before
 In some cases it is possible to simplify logic
expressions using the rules of Boolean algebra
Example – X  ABC ABC  AC  AC
can be simplified to X  BC A
hence the following circuits are equivalent
Boolean expression simplefication
 Prove that x+yz=(x+y)(x+z)
 RHS=(x+y)(x+z)
 =x.x+x.z+y.x+y.z; using distributive property
 =x+x.z+x+y.x+y.z; x+x=x
 =x(1+z)+x(1+y)+y.z; taking common
 =x+x+y.z; as 1+x=x
 =x+y.z
 proved
Contd...
 Prove that x(x’+y)=xy
 LHS=x(x’+y)
 =x.x’+x.y
 =x.y; as x.x’=0.
 proved
Contd...
 Simplify f(x,y,z)=x’y’z+ x’yz+ xy’
 x’y’z+ x’yz+ xy’
 =x’z(y’+y)+xy’
 =x’z+xy’; As y+y’=1
 Answer
Contd...
 Simplify f(x,y,z)=xy+x’z+yz
 xy+x’z+yz
 = xy+x’z+yz(x+x’)
 = xy+x’z+yzx+yzx’
 =xy(1+z)+x’z(1+y)
 =xy+x’z; as 1+z=1
 Answer
Contd...
 Prove that (x+y)(x’+z)(y+z)=(x+y)(x’+z)
 LHS=(x+y)(x’+z)(y+z)=(xx’+xz+yx’+yz)(y+z)
 =xyz+yx’+yz+xz+x’yz+yz; as xx’=0, xx=x
 =xyz+yz+xyz+xz+yx’+x’yz+yz; adding xyz
 =yz(1+x)+xz(1+y)+yx’+yz(1+x’)
 =yz+xz+yx’+yz;
 =xx’+yz+xz+yx’; adding xx’=0 & removing extra yz
 =(x+y)(x’+z)
Exercise...
 Simplify...
 1. x’y’+xy+x’y
 2. (x+y)(x+y’)
 3. x’y+xy’+xy+x’y’
 4. x’+xy+xz’+xy’z’
 5. xy’+y’z’+x’z’
 6. x’yz+xz
 7. (x+y)’(x’+y’)
Key Points
 It is common to represent the two states of a binary variable
by ‘0’ and ‘1’
 Logic circuits are usually implemented using logic gates
 Circuits in which the output is determined solely by the
current inputs are termed combinational logic circuits
 Logic functions can be described by truth tables or using
Boolean algebraic notation
 Binary digits may be combined to form digital words
 Digital words can be processed using binary arithmetic
 Several codes can be used to represent different forms of
information
Simplification of Boolean Functions:
Two Methods
 The algebraic method by
using Identities
 The graphical method by
using Karnaugh Map method
 The K-map method is easy and straightforward.
 A K-map for a function of n variables
 consists of 2n cells, and,
 in every row and column, two adjacent cells should differ
in the value of only one of the logic variables.

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Examples of K-Maps:
 Examples:
Cell numbers are written in the cells.
 2-variable K-map

B
A 0 1
0 0 1
1 2 3

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3-Variable K-Map:
 3-variable K-map

BC
A 00 01 11 10
0 0 1 3 2
1 4 5 7 6

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4-variable K-map
 4-variable K-map
CD
AB 00 01 11 10

00 0 1 3 2
01 4 5 7 6
11 12 13 15 14
10 8 9 11 10

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STORAGE ELEMENTS:
 Maintain a binary state indefinitely as long as power is
delivered to the circuit
 Latches: Binary state changes with signal levels: Level
Triggered
 Flip-flops: Binary state changes with signal transitions:
Edge Triggered
S-R Latch
•The latch
-holds (stores) when S = R = 0
-is set (to 1) by bringing S = 1 with R = 0
-is reset (to 0) or cleared by bringing R = 1 with S = 0
•The condition S = R = 1 must be avoided because it leads to an
indeterminate condition, where the output can not be predicted
at any one point in time. This can cause a race condition to
occur when the inputs change to S = R = 0.
Latches: SR Latch with NOR gates

The SR latch is a circuit with two cross-coupled NOR gates or


two cross-coupled NAND gates. It has two inputs labeled S
for set and R for reset.
SR Latch with NAND Gates
Graphic Symbols for Latches
A latch is designated by a rectangular block with inputs on
the left and outputs on the right. One output designates the
normal output, and the other designates the complement
output.

NOR Latch: Active High Inputs NAND Latch: Active Low Inputs

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SR Latch with Control (Enable) Input
The operation of the basic SR latch can be modified by
providing an additional control input that determines when
the state of the latch can be changed. It consists of the basic
SR latch and two additional NAND gates.
Symbol:

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D-Latch and Symbol:

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Flip-Flops
The state of a latch or flip-flop is switched by a change in
the control input. This momentary change is called a trigger
and the transition it cause is said to trigger the flip-flop. The
D latch with pulses in its control input is essentially a flip-flop
that is triggered every time the pulse goes to the logic 1
level. As long as the pulse input remains in the level, any
changes in the data input will change the output and the
state of the latch.
Clock Response in Latch

In Fig (a) a positive level response in the control input


allows changes, in the output when the D input changes
while the clock pulse stays at logic 1.
Clock Response in Flip-Flop
Latches and Flip Flops
Edge-Triggered D Flip-Flop
The first latch is called the master and the second the
slave. The circuit samples the D input and changes its output
Q only at the negative-edge of the controlling clock.

CLK 1 0 1 0 1 0
D 110011…
Y 110011…
Q ? 1 1 0 0 1 ….
Graphic Symbol for Edge-Triggered D Flip-Flop
JK Flip-Flop
There are four operations that can be performed with a flip-flop: set it to 1, reset it
to 0, no change, complement its output. The JK flip-flop performs all four
operations. The circuit diagram of a JK flip-flop constructed with a D flip-flop and
gates.

Q=J.Q’+K’.Q
Operation...
Q=J.Q’+K’.Q
JK Flip-Flop
The J input sets the flip-flop to 1, the K input resets it to 0, and when both inputs are
enabled, the output is complemented. This can be verified by investigating the
circuit applied to the D input:
D = J Q` + K` Q
T (Toggle) Flip-Flop
The T flip-flop is a complementing flip-flop and can be obtained from a JK flip-
flop when inputs J and K are tied together.
T Flip-Flop
The T flip-flop can be constructed with a D flip-flop and an exclusive-OR gates
as shown in Fig. (b). The expression for the D input is

D=T Q = TQ` + T`Q

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