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Electronics Lab Week 07

The document outlines an experimental verification for sequential circuits, focusing on the design of a 4-bit R/2R ladder D/A converter and a 4-bit asynchronous counter. It details the apparatus required, circuit diagrams, procedures for setup, and observation tables for data collection. The experiment aims to compare calculated and observed outputs to validate the designs.

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Aditya
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2 views

Electronics Lab Week 07

The document outlines an experimental verification for sequential circuits, focusing on the design of a 4-bit R/2R ladder D/A converter and a 4-bit asynchronous counter. It details the apparatus required, circuit diagrams, procedures for setup, and observation tables for data collection. The experiment aims to compare calculated and observed outputs to validate the designs.

Uploaded by

Aditya
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Experiment No.

07
Objective: Design an experimental verification of sequential circuits.

Apparatus Required:
Sl No. Name Range / Value Quantity
1 Regulated Power Supply 0-25 V 1
2 Multimeter 0-25 V 1
3 Bread Board - 1
4 Resistor - As Required
5 Connecting Wires - As Required
6 OPAMP IC-741 - 1
7 IC-74390 - 1
8 IC-7447 - 1
9 CRO 20MHz 1
10 Seven Segment Display - 1

1 Design of R/2R ladder 4-bit D/A Converter using IC 741:


Real world signals are analogue. Digital systems that interface with the real world do so using
analogue-to-digital converters (ADC). Conversion back to analogue is accomplished using digital-to-
analogue converters (DAC). The R-2R ladder network is commonly used for Digital to Analogue
conversions. In basic N bit R-2R resistor ladder network the digital inputs or bits range from the most
significant bit (MSB) to the least significant bit (LSB). The bits are switched between either 0V or VR
and depending on the state and location of the bits Vo will vary between 0V and VR. The MSB causes
the greatest change in output voltage and the LSB causes the smallest. The R-2R ladder is inexpensive
and relatively easy to manufacture since only two resistor values are required. It is fast and has fixed
output impedance R. In R-2R ladder type D to A converter, only two values of resistor is used (i.e. R
and 2R). Hence it is suitable for integrated circuit fabrication.
1.1 Circuit Diagram:

1.2 Procedure:
1. Wire the R/2R ladder 4-bit DAC circuit on the bread board.
2. Select the approximate value of R and 2R.
3. Reference voltage VR is set as 5V.
4. Find the output voltage Vo for different combinations of digital binary inputs from 0000 to 1111.
5. Compare the calculated values with observed values and plot DAC characteristics.
1.3 Calculation:
Analog output voltage is given by

Where, n is Number of bits,


V0, V1, V2, ……... Vn-1 are Digital input voltage levels corresponding to logic 1 and logic 0.

1.4 Observation Table:


Obs. Digital Input Equivalent Analog Output Volts Error
No. Decimal |X-Y|
A B C D Number Calculated (X) Observed (Y)
(23) (22) (21) (20)

1. 0 0 0 0 0

2. 0 0 0 1 1

3. 0 0 1 0 2

4. 0 0 1 1 3

5. 0 1 0 0 4

6. 0 1 0 1 5

7. 0 1 1 0 6

8. 0 1 1 1 7

9. 1 0 0 0 8

10. 1 0 0 1 9

11. 1 0 1 0 10

12. 1 0 1 1 11

1.5 Summary:
Analog output voltage matches with calculated voltage or not. (Yes/No)
2 Design of 4-bit asynchronous counter:
A binary ripple counter can be constructed by use of clocked J K flip- flops. The system clock, a
square wave, drives flip flop A. The output of A drives B, and the output of B drives flip –flop C
and so on. All the J and K input are tied to +Vcc. This means that each flip flop will change state
with a negative transition at its clock input. Let’s assume that the flip - flops are initially reset to
produce “0” outputs. If we consider A to be least -significant bit (LSB) and C the most significant
bit (MSB), we can say the contents of the counter is DCBA =0000. Since A acts as the clock for B,
each time the waveform at A goes low, flip flop B will toggle. Thus at point b on the time line, B
goes high ;it then goes low at the point d and toggles back high again at point f. Notice that the wave
from at the output of flip flops one –half the frequency of A and one –fourth the clock frequency .
Since B acts as the clock for C, Each time the waveform at B goes low, flip flop C will toggle. Thus
C goes high at point d on the time line and goes back low again at point h. The frequency of the wave
form at C is one half that at B, But it is only one either the clock frequency.
2.1 Circuit Diagram:

Fig 2: 4-bit Asynchronous up counter


2.2 Timing Diagram
2.3 Dual Decade Counter Chip:
The SN54/74LS390 contain a pair of high-speed 4-stage ripple counters. Each half of the LS390 is
partitioned into a divide-by-two section and a divide-by five section, with a separate clock input for each
section. The two sections can be connected to count in the 8.4.2.1 BCD code or they can count in a binary
sequence to provide a square wave (50% duty cycle) at the final output.

2.4 Seven Segment Driver IC:


The SN74LS47 is a 7-segment Driver IC. It is used to drive a 7-segment display without the need
of a microcontroller. It accepts decimal values (Binary coded) as inputs and provides a pattern on
output pins that can display from 0 to 9 on a 7-segment display. The 74LS47 accepts four lines of BCD
input data, generates their complements internally, and decodes the data with seven AND/OR gates
having open-collector outputs to drive indicator segments directly.
2.5 Seven Segment Display
The 7-segment display, also written as “seven segment display”, consists of seven LEDs (hence its
name) arranged in a rectangular fashion as shown. Each of the seven LEDs is called a segment because
when illuminated the segment forms part of a numerical digit (both Decimal and Hex) to be displayed.
An additional 8th LED is sometimes used within the same package thus allowing the indication of a
decimal point, (DP) when two or more 7-segment displays are connected together to display numbers
greater than ten.

The Common Cathode (CC) – In the common cathode display, all the cathode connections of the
LED segments are joined together to logic “0” or ground. The individual segments are illuminated by
application of a “HIGH”, or logic “1” signal via a current limiting resistor to forward bias the
individual Anode terminals (a-g).

The Common Anode (CA) – In the common anode display, all the anode connections of the LED
segments are joined together to logic “1”. The individual segments are illuminated by applying a
ground, logic “0” or “LOW” signal via a suitable current limiting resistor to the Cathode of the
particular segment (a-g).

2.6 Procedure:
1. Make the connections as shown in the figure below.
2. Apply clock pulse from function generator of 1 Hz.
3. Note down the binary count and count on seven segment display and observation table.
4. Verify truth table.

2.7 Observation Table:


Obs. Present State Calculated Next State Observed Next State
No.
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0

1. 0 0 0 0

2. 0 0 0 1

3. 0 0 1 0

4. 0 0 1 1

5. 0 1 0 0

6. 0 1 0 1

7. 0 1 1 0
8. 0 1 1 1

9. 1 0 0 0

10. 1 0 0 1

11. 1 0 1 0

12. 1 0 1 1

2.8 Summary:
Counter output voltage matches with calculated output or not. (Yes/No)

3 Conclusion:

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