Assignment given by

Unmanned Dynamics India Private Limited

Embedded Systems Internship

Assignment solved by
Prabhat Pandey
+91 7470526702
prabhatpandeypps@gmail.com
Question 1

How many pins are there in the chosen IC?

Answer 1

STM32F405xx and STM32F407xx family offers devices in various packages ranging from 64 pins to 176 pins.
(DataSheet Page No. 14)

• LQFP64 package: 64 pins. (DataSheet Page 1)

• LQFP100 package: 100 pins. (DataSheet Page 1)

• LQFP144 package: 144 pins. (DataSheet Page 1)

The STM32F405RET6 follows STMicroelectronics' standard naming conventions. The "RE" suffix denotes a 64-pin
LQFP package. (taken some reference from STMicroelectronics' site)

Question 2

What is the maximum number of pins that can be configured as GPIOs?

Answer 2

The GPIO count is dependent on the package type. Out of 64 total pins, some are reserved for power, ground, and
other dedicated functions.

The maximum number of GPIOs available in this variant is 51. (DataSheet Page No. 16, Table 2)

Question 3

What is the maximum number of pins that can be configured as ADC inputs?

Answer 3

Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16 external channels. (DataSheet
Page No. 40)

Question 4

What is the maximum CPU frequency?

Answer 4

The STM32F405 series features the ARM Cortex-M4 core, which operates at a maximum clock frequency of 168
MHz. (DataSheet Page No. 1)

Question 5

What is the flash memory size?

Answer 5

The "RET6" variant of the STM32F405 family is defined to have 512 KB of flash memory. (DataSheet Page No. 1)

Question 6
Suggest an alternate part number in the same series with a higher flash memory size.

Answer 6

The STM32F405 family includes variants with higher flash memory, such as STM32F405VG, which has 1 MB Flash
while maintaining similar features. (DataSheet Page No. 15, Table 2)

Question 7

Is the chosen part number suitable for the operation at 100 degrees Celsius? If not, suggest an alternate part number
in the same series.

Answer 7

The STM32F405RET6 is a commercial-grade microcontroller, meaning it typically supports an operating temperature

range of -40°C to +85°C. However, STMicroelectronics provides industrial-grade variants such as STM32F405VE,
which supports up to 105°C. (DataSheet Page No. 16, Table 2)

Question 8

What is the start address of flash memory?

Answer 8

This is a standard address for STM32F4 series microcontrollers, where Flash memory always starts at 0x08000000.
(DataSheet Page No. 72 Figure 18)

Question 9

What is the end address of the flash memory for the chosen part number?

Answer 9 Page No. -

Since the STM32F405RET6 has 512 KB of Flash memory, we need to calculate the end address based on the Flash
memory range. (Page No. 72 Figure 18)

End Address = Start Address + Flash Size − 1

= 0x08000000 + 0x00080000 − 1

= 0x0807FFFF

Question 10

What is the start address of RAM memory?

Answer 10

In STM32 microcontrollers, RAM always starts at 0x20000000. (DataSheet Page No. 72 Figure 18)

Question 11

What is the end address of the RAM memory for the chosen part number?

Answer 11
The STM32F405RET6 has 128 KB of main SRAM and 64 KB of Core Coupled Memory (CCM) SRAM, total of 192 KB.
(Page No. 72 Figure 18)

End Address = Start Address + Flash Size − 1

= 0x20000000 + 0x00020000 − 1

= 0x2001FFFF

Question 12

The hardware designer decided to connect pin 60 of the chosen IC to 0 V. What can be the reason?

Answer 12

The STM32F405RET6 is a 64-pin LQFP package where pin 60 is a BOOT0 pin. (DataSheet Page No. 42, Figure 12 -
LQFP64 pinout)

The BOOT0 pin is often pulled low (0V) to ensure the microcontroller boots from Flash memory instead of System
Memory (bootloader mode).

Pin 60 is likely a VSS (ground) pin. VSS must be connected to 0V (GND) to ensure proper circuit operation and
prevent floating voltage.

Question 13

What is the expected value of the variable 'data' before the execution of the infinite loop if the following program is
executed in the chosen part number?

void main(void){

uint32_t * address;

uint32_t data;

address = (uint32_t *)0x4002040C;

data = *address;

while(1);

Answer 13

The program reads a value from the memory location 0x4002040C. This address belongs to the STM32F4 memory-
mapped peripheral region. (DataSheet Page No. 76, Table 10)

The address 0x4002040C corresponds to the GPIOB_ODR register, which holds the current output data of GPIO port
B.

GPIOB was not configured or modified before execution. Therefore, Expected value of data = 0x00000000

Question 14

Which bit should be modified in RCC_PLLCFGR register to select external crystal as the clock source for PLL?

Answer 14
The RCC_PLLCFGR (Reset and Clock Control - PLL Configuration Register) contains a bit called PLLSRC (Bit 22), which
selects the clock source for the PLL (Phase-Locked Loop).

• HSE (High-Speed External): An external crystal oscillator (e.g., 8 MHz).

• HSI (High-Speed Internal): The internal RC oscillator (16 MHz).

Setting PLLSRC = 1 selects HSE as the PLL input clock.

Setting PLLSRC = 0 selects HSI as the PLL input clock.

(I found this information in the RCC (Reset and Clock Control) chapter of the STM32F4 Reference Manual (RM0090))

Question 15

What should be the minimum value of PLLM bits in RCC_PLLCFGR register if the external crystal frequency is 8 MHz?

Answer 15

PLLM – PLL Main Divider

PLLN – PLL Multiplication Factor

PLLP – PLL Main Output Divider

The STM32F4 series uses a Phase-Locked Loop (PLL) to generate higher frequencies from an external crystal (HSE).

The PLLM value divides the external crystal frequency (HSE) before feeding it to the PLL Voltage-Controlled Oscillator
(VCO).

To ensure proper PLL operation, the input to the VCO (after division by PLLM) must be between 1 MHz and 2 MHz.

Given an 8 MHz external crystal (HSE), the minimum value of PLLM should be 8 to bring the VCO input frequency
within this range:
𝑓𝐻𝑆𝐸 8𝑀𝐻𝑧
𝑓𝑣𝑐𝑜_𝑖𝑛𝑝𝑢𝑡 = = = 1𝑀𝐻𝑧
𝑃𝐿𝐿𝑀 8
Since 1 MHz is within the valid range (1-2 MHz), PLLM = 8 is the correct minimum value.

(I found this information in the RCC (Reset and Clock Control) chapter of the STM32F4 Reference Manual
(RM0090))

Question 16

What should be the values of PLLN and PLLP bits in RCC_PLLCFGR register if maximum allowed PLL output clock
frequency is selected?

Answer 16 Page No. –

• The STM32F405RET6 has a maximum system clock frequency of 168 MHz.

• The PLL (Phase-Locked Loop) output frequency is calculated using the formula:
𝑃𝐿𝐿𝑁
𝑓(𝑉𝐶𝑂_𝑐𝑙𝑜𝑐𝑘) = 𝑓𝑃𝐿𝐿_𝑐𝑙𝑜𝑐𝑘_𝑖𝑛𝑝𝑢𝑡 ×
𝑃𝐿𝐿𝑀
Where:

• 𝑓𝑃𝐿𝐿_𝑐𝑙𝑜𝑐𝑘_𝑖𝑛𝑝𝑢𝑡 (for HSE) = 8 MHz (external crystal)

• PLLM = 8 (minimum valid divider)

• PLLN (multiplier)
 • PLLP (divider for system clock)
𝑃𝐿𝐿𝑁
𝑓(𝑉𝐶𝑂_𝑐𝑙𝑜𝑐𝑘) = 𝑓𝑃𝐿𝐿_𝑐𝑙𝑜𝑐𝑘_𝑖𝑛𝑝𝑢𝑡 ×
𝑃𝐿𝐿𝑀
𝑃𝐿𝐿𝑁
2 × 168 𝑀𝐻𝑧 = 8 ×
8
𝑃𝐿𝐿𝑁 = 336
(DataSheet Page No. 165 RCC PLL configuration register)

Question 17

What is the maximum allowed frequency of AHB buses?

Answer 17 Page No. –

The maximum frequency of the three AHB (Advanced High-performance Bus) buses is 168 MHz. (DataSheet Page No.
25 Clocks and startup)

Question 18

What is the maximum allowed frequency of APB2 peripheral clock?

Answer 18 Page No. –

the maximum frequency of the high-speed APB2 domains is 84 MHz. (DataSheet Page No. 25 Clocks and startup)

Question 19

What is the maximum allowed frequency of APB1 peripheral clock?

Answer 19 Page No. –

The maximum allowed frequency of the low-speed APB1 domain is 42 MHz. (DataSheet Page No. 25 Clocks and
startup)

Question 20

What is the maximum allowed frequency of APB2 timer clock?

Answer 20 Page No. –

The APB2 domain has a maximum frequency of 84 MHz. However, when the APB2 prescaler is greater than 1, the
timer clock frequency is automatically set to twice the APB2 clock frequency, resulting in a maximum timer clock
frequency of 168 MHz.

(I found this information in DataSheet Page No. 25 Clocks and startup and STM32F4 Reference Manual (RM0090))

Question 21

What is the maximum allowed frequency of APB1 timer clock?

Answer 21
The APB1 domain has a maximum frequency of 42 MHz. However, when the APB1 prescaler is greater than 1, the
timer clock frequency is automatically set to twice the APB1 clock frequency, resulting in a maximum timer clock
frequency of 84 MHz.

(I found this information in DataSheet Page No. 25 Clocks and startup and STM32F4 Reference Manual (RM0090))

Statement

The frequencies of AHB clock, APB1 peripheral clock, APB2 peripheral clock, APB1 timer clock and APB2 timer clock
are configured to their respective maximum allowed values.

Question 22

Timer 2 is configured in edge-aligned and upcounter mode. What should be Timer 2 auto-reload register (ARR) value
to achieve a frequency of 150 kHz (TIM2_PSC is not modified)?

Answer 22

Given that TIM2 is on APB1, its timer clock runs at 84 MHz (twice the APB1 clock).
𝑓𝑡𝑖𝑚𝑒𝑟_𝑐𝑙𝑜𝑐𝑘
𝐴𝑅𝑅 = −1
𝑑𝑒𝑠𝑖𝑟𝑒𝑑 𝑓𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦
84000000
𝐴𝑅𝑅 = −1
150000
𝐴𝑅𝑅 = 559
𝐴𝑅𝑅 = 0𝑥022𝐹 (𝐼𝑛 𝐻𝑒𝑥𝑎𝑑𝑒𝑐𝑖𝑚𝑎𝑙)
Thus, the ARR value should be 0x022F.

Question 23

Timer 1 is configured in edge-aligned and upcounter mode. What should be Timer 1 auto-reload register (ARR) value
to achieve a frequency of 150 kHz (TIM1_PSC is not modified)?

Answer 23

Given that TIM1 is on APB2, and its timer clock runs at 168 MHz (twice the APB2 clock)
𝑓𝑡𝑖𝑚𝑒𝑟_𝑐𝑙𝑜𝑐𝑘
𝐴𝑅𝑅 = −1
𝑑𝑒𝑠𝑖𝑟𝑒𝑑 𝑓𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦
168000000
𝐴𝑅𝑅 = −1
150000
𝐴𝑅𝑅 = 1119
𝐴𝑅𝑅 = 0𝑥045𝐹 (𝐼𝑛 𝐻𝑒𝑥𝑎𝑑𝑒𝑐𝑖𝑚𝑎𝑙)
Thus, the ARR value should be 0x045F.

Question 24

Timer 8 is configured in edge-aligned and upcounter mode. What should be Timer 8 auto-reload register (ARR) value
to achieve a frequency of 150 kHz (TIM8_PSC is not modified)?

Answer 24
TIM8 is also an APB2 timer, meaning its clock is 168 MHz.
𝑓𝑡𝑖𝑚𝑒𝑟_𝑐𝑙𝑜𝑐𝑘
𝐴𝑅𝑅 = −1
𝑑𝑒𝑠𝑖𝑟𝑒𝑑 𝑓𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦
168000000
𝐴𝑅𝑅 = −1
150000
𝐴𝑅𝑅 = 1119
𝐴𝑅𝑅 = 0𝑥045𝐹 (𝐼𝑛 𝐻𝑒𝑥𝑎𝑑𝑒𝑐𝑖𝑚𝑎𝑙)
Thus, the ARR value should be 0x045F.

Question 25

Name the register, the bits of the corresponding register and the values to be written in those bits such that channel
1 and channel 2 of Timer 2 are configured in PWM mode 1 and PWM mode 2, respectively.

Answer 25

PWM stands for Pulse Width Modulation.

TIM2_CCMR1 (Capture/Compare Mode Register 1) is used.

Enable preload for proper operation.

Bits to Modify:

Bit Name Description Value

OC1M (Bits 6:4) Output Compare Mode for Channel 1 0110 (PWM Mode 1) {in binary}

OC2M (Bits 14:12) Output Compare Mode for Channel 2 0111 (PWM Mode 2) {in binary}

OC1PE (Bit 3) Output Compare Preload Enable for Channel 1 1 {in binary}

OC2PE (Bit 11) Output Compare Preload Enable for Channel 2 1 {in binary}

(I found this information in Section 17.3.10 PWM mode section Page No. 544 of STM32F4 Reference Manual
(RM0090))

Statement

Timer 2 and Timer 1 are to be synchronized such that Timer 1 counter (TIM1_CNT) starts from 0, i.e., TIM1_CNT
resets, when the Timer 2 counter (TIM2_CNT) has reached to one-third of its ARR value (TIM2_ARR). Timer 2 channel
3 is used to generate trigger output and Timer 1 is to be configured to receive the trigger from Timer 2.

Question 26

What should be the value of TS bits of TIM1_SMCR register?

Answer 26 Page No. –

TS stands for Trigger Selection.

TIM1 must be synchronized with TIM2, meaning TIM1 should reset when TIM2 counter (TIM2_CNT) reaches one-
third of TIM2_ARR.
TIM2 Channel 3 (TIM2_CH3) is used as the trigger output.

We need to select TIM2_CH3 as the trigger source for TIM1.

TIM2_CH3 is set as the master trigger output, so TIM1 must use TS = 011 (ITR3) {in binary} to receive this trigger.

(I found this information in Section 18.3.15 Timer synchronization section of STM32F4 Reference Manual
(RM0090))

Question 27

What should be the value of SMS bits of TIM1_SMCR register?

Answer 27

SMS (Slave Mode Selection) = 100 (Reset Mode) {in binary}

(I found this information in Section 18.3.15 Timer synchronization section of STM32F4 Reference Manual
(RM0090))

Question 28

What should be the value of MMS bits of TIM2_CR2 register?

Answer 28

MMS (Master Mode Selection) = 011 (OC3REF signal is used as TRGO) {in binary}

(I found this information in Section 18.3.15 Timer synchronization section of STM32F4 Reference Manual
(RM0090))

Question 29

What should be the value of OC3M bits of TIM2_CCMR2 register?

Answer 29

OC3M (Output Compare Mode) = 0110 (PWM Mode 1)

(I found this information in Section 18.4.7 Output compare mode section of STM32F4 Reference Manual
(RM0090))

Question 30

What should be the value of TIM2_CCR3 register if the value of TIM2_ARR is the same as the one previously
calculated?

Answer 30

𝐴𝑅𝑅 = 559 (𝑓𝑟𝑜𝑚𝑒 𝑞𝑢𝑒𝑠𝑡𝑖𝑜𝑛 22)

𝐴𝑅𝑅 559
𝐶𝐶𝑅3 = = ≈ 186
3 3
(I found this information in Section 18.4.7 Output compare mode section of STM32F4 Reference Manual
(RM0090))
Statement

2 analog signals are connected to pins PA1 and PA6. These analog signals are to be converted to digital data using
ADC1 peripheral. Scan mode is enabled by setting SCAN bit in ADC1_CR1 register.

Each of the two signals needs to be sampled at a frequency same as the that of Timer 2. The signals need to be
sampled at the start of the Timer 2 counter. Channel 4 of Timer 2 is used to generate trigger for the ADC. TIM2_CCR4
is set to 1. Channel 4 is configured in PWM mode 2 by assigning 0b111 to OC4M bits of TIM2_CCMR2 register.

Question 31

What should be the value of EXTSEL bits of ADC1_CR2 register?

Answer 31

𝐸𝑋𝑇𝑆𝐸𝐿 = 0101 (0𝑥𝐷)

(I found this information in Section 13.6 Table 69 of STM32F4 Reference Manual (RM0090))

Question 32

What should be the value of ADC1_SQR3 register?

Answer 32

Since ADC1_SQR3 holds the first six conversion channels, we need to configure it as:

• First conversion: Channel 1 (PA1)

• Second conversion: Channel 6 (PA6)

Thus, the SQR3 register is configured as:

• LSB (SQ1) = 00001 (Channel 1)

• Next 5 bits (SQ2) = 00110 (Channel 6)

ADC1_SQR3 = (6 << 5) | (1 << 0)

= 0x0011

(I found this information in Section 13.13.11 ADC regular sequence register 3 (ADC_SQR3) of STM32F4 Reference
Manual (RM0090))

Question 33

What should be the value of ADC1_SQR1 register?

Answer 33

Since we are converting two channels (PA1 -> Channel 1 and PA6 -> Channel 6), we must set the L[3:0] (bits 20:23)
field to indicate that two conversions will occur.

Since we have two ADC conversions, we set L[3:0] = 0b0001 (1 in decimal, since it represents "total conversions - 1").

ADC1_SQR1 = (1 << 20)

= 0x00000000
(I found this information in Section 13.13.9 ADC regular sequence register 1 (ADC_SQR1) of STM32F4 Reference
Manual (RM0090))

Statement

The ADC results have to be transferred to an array of 16-bit unsigned integers of size 2 using DMA.

Question 34

Which DMA (DMA1 or DMA2) should be used?

Answer 34

The STM32F405RET6 microcontroller has two DMA controllers: DMA1 and DMA2. ADC1 is connected only to DMA2,
which means DMA1 cannot be used for ADC1 data transfers.

(I found this information in Section 10.3.3 Table 43 and 44 of STM32F4 Reference Manual (RM0090))

Question 35

What are the stream numbers that can be used?

Answer 35

ADC1 is mapped to Stream 0 and Stream 4 in DMA2.

(I found this information in Section 10.3.3 Table 43 and 44 of STM32F4 Reference Manual (RM0090))

Question 36

Which channel of the DMA stream can be used?

Answer 36

Each DMA stream can support multiple channels, and for ADC1, DMA2 streams 0 and 4 must use Channel 0.

(I found this information in Section 10.3.3 Table 44 of STM32F4 Reference Manual (RM0090))

Question 37

Should MINC bit of DMA stream configuration register be set or clear?

Answer 37

The ADC results need to be stored in an array of 16-bit unsigned integers.

When MINC is set (1), the memory address automatically increments after each data transfer, allowing the ADC
results to be stored sequentially in the array.

If MINC is cleared (0), all data would be written to the same memory location, which is incorrect.

Thus, The MINC (Memory Increment) bit should be SET (1).

(I found this information in Section 10.3.17 of STM32F4 Reference Manual (RM0090))

Question 38

Should PINC bit of DMA stream configuration register be set or clear?

Answer 38

The ADC result is stored in a fixed peripheral register.

PINC = 1 would increment the peripheral register address, which is incorrect for ADC1.

PINC = 0 ensures that all data transfers come from the same ADC data register.

Thus, The PINC (Peripheral Increment) bit should be CLEARED (0).

(I found this information in Section 10.5.5 of STM32F4 Reference Manual (RM0090))

Thanks for your consideration