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Orhan Gazi

A Tutorial
Introduction
to VHDL
Programming
A Tutorial Introduction to VHDL Programming
Orhan Gazi

A Tutorial Introduction
to VHDL Programming

123
Orhan Gazi
Department of Electronics and
Communication Engineering
Çankaya University
Ankara, Turkey

ISBN 978-981-13-2308-9 ISBN 978-981-13-2309-6 (eBook)

https://doi.org/10.1007/978-981-13-2309-6
Library of Congress Control Number: 2018952599

© Springer Nature Singapore Pte Ltd. 2019

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Contents

1 Entity, Architecture and VHDL Operators . . . . . . . . . . . . . . . . . . . . 1

1.1 Entity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 The Data Types Used in Input/Output Ports . . . . . . . . . . . . . . . . . 6
1.3 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.4 Data Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.4.1 Constant Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.4.2 Signal Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.4.3 Variable Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.5 VHDL Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.5.1 Assignment Operators . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.5.2 Logical Operators and Shift Operators . . . . . . . . . . . . . . . 26
1.5.3 Relational Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.5.4 Arithmetic Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.5.5 Concatenation Operator “&” . . . . . . . . . . . . . . . . . . . . . . 32
1.5.6 Generic Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2 Combinational Logic Circuit Design and Concurrent
Coding in VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.1 “When” and “Select” Statements . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.2 Generate Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.3 Examples for Combinational Circuits Implemented in VHDL . . . . 45
3 Simulation of VHDL Programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.1 Test-Bench Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4 User Defined Data Types, Arrays and Attributes . . . . . . . . . . . . . . . 99
4.1 User Defined Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.1.1 Enumerated Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.2 User Defined Array Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.2.1 Constrained Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.2.2 Unconstrained Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.2.3 Defining PORT Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . 105

v
vi Contents

4.3 Defining 2D Arrays or Matrices . . . . . . . . . . . . . . . . . . . . . . . . . 107

4.3.1 Matrix as Column Wise Concatenated Row Vectors . . . . . 107
4.3.2 Matrix as Table of Numbers . . . . . . . . . . . . . . . . . . . . . . 110
4.3.3 3D Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
4.4 Subtypes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
4.4.1 Type Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
4.5 Attributes of Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
4.5.1 Attributes for Scalar Data Types . . . . . . . . . . . . . . . . . . . 115
4.5.2 Attributes for Array Data Types . . . . . . . . . . . . . . . . . . . 117
4.5.3 Attributes for Signal Objects . . . . . . . . . . . . . . . . . . . . . . 119
5 Sequential Circuit Implementation in VHDL . . . . . . . . . . . . . . . . . . 123
5.1 Sequential Circuits in VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.1.1 Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.1.2 IF Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.2 Example Implementations for Sequential Logic Units . . . . . . . . . . 125
5.2.1 D-Type Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.2.2 Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.2.3 JK and T Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.2.4 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.2.5 Clock Divider (Frequency Divider) . . . . . . . . . . . . . . . . . 135
5.2.6 BCD to SS Converter with 1 s BCD Counter . . . . . . . . . 143
5.3 The Wait Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.3.1 Wait Until . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.3.2 Wait on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
5.4 Case Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
5.5 Loop Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
5.5.1 Next and Exit Statements . . . . . . . . . . . . . . . . . . . . . . . . 149
5.6 Example Sequential Logic Circuit Implementation in VHDL . . . . . 150
6 VHDL Implementation of Logic Circuits Involving
Registers and Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
6.1 Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
6.1.1 Shift Register with Parallel Load . . . . . . . . . . . . . . . . . . . 168
6.1.2 Logic Circuits Involving Shift Registers and Counter . . . . 170
6.1.3 Serial Transfer Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
6.1.4 Serial Adder Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
7 Packages, Components, Functions and Procedures . . . . . . . . . . . . . . 189
7.1 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
7.2 Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
7.3 Functions and Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
7.3.1 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
7.3.2 Operator Overloading . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Contents vii

7.4 Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

7.4.1 Differences Between a Function and a Procedure . . . . . . . 214
8 Fixed and Floating Point Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . 217
8.1 Fixed Point Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
8.1.1 Type Conversion Functions . . . . . . . . . . . . . . . . . . . . . . 221
8.1.2 Operators for Fixed Point Numbers . . . . . . . . . . . . . . . . . 222
8.1.3 Arithmetic Operations with Fixed Point Numbers
and Sizing Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
8.1.4 Automatic Resizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
8.1.5 Resize Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
8.1.6 Add Cary Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
8.1.7 Divide Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
8.1.8 Reciprocal Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
8.1.9 Remainder Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
8.1.10 Scalb Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
8.1.11 Maximum and Minimum Function . . . . . . . . . . . . . . . . . 233
8.1.12 ‘Find Left Most’ and ‘Find Right Most’ Functions . . . . . . 234
8.1.13 ABS Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
8.2 Floating Point Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
8.2.1 Floating Point Type Conversion Functions . . . . . . . . . . . 238
8.2.2 Operators for Floating Point Numbers . . . . . . . . . . . . . . . 243
8.2.3 Copysign Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
8.2.4 Scalb Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
8.2.5 Logb Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Chapter 1
Entity, Architecture and VHDL
Operators

VHDL stands for “very high speed integrated circuits hardware description lan-
guage”, and first developed by the US department of defense in 1980s. It is used to
describe the behavior of an electronic circuit. VHDL programs consist of program
modules. A module is nothing but a program segment written for some specific
purposes. For instance, we have package modules, test modules, and main VHDL
modules, i.e., main programs.
In this chapter, entity and architecture parts of a VHDL program will be
explained in details. Entity part is used to describe the input and output ports of an
electronic circuit, i.e., used to describe I/O ports. On the other hand, architecture
part of a VHDL module is used to describe the operation of the electronic circuit.
During the circuit operation, the circuit process its input data obtained from input
ports, and produces its output data to be sent to the output ports. We will also
discuss the data types used for the ports available in entity part. In addition, VHDL
operators will be explained shortly.

1.1 Entity

As we mentioned in the previous paragraph, entity part of the VHDL program

describes the I/O ports of an electronic circuit. A port can be an input port, or an
output port, or both input and output port at the same time, or can be a buffer port.
In Fig. 1.1, the graphical illustration of the port types is given.

© Springer Nature Singapore Pte Ltd. 2019 1

O. Gazi, A Tutorial Introduction to VHDL Programming,
https://doi.org/10.1007/978-981-13-2309-6_1
2 1 Entity, Architecture and VHDL Operators

Fig. 1.1 Black box

representation of an electronic Output
circuit

Input/Output
Input Electronic
Circuit
Buffer

Internal
Circuit

The general structure of the entity part is shown in PR 1.1

PR 1.1 General structure of

entity unit entity entity_name is
port( port_ID1: I/O option signal_type;
port_ID2: I/O option signal_type;
);
end [entity] [entity_name];

where ‘[entity] [entity_name]’ means that you can omit or keep words inside
braces. Let’s illustrate the use of entity by an example.
Example 1.1 The black box representation of an electronic circuit is shown in
Fig. 1.2. Describe the electronic circuit ports by a VHDL program, i.e., by PR.

Fig. 1.2 Black box

representation of an electronic Electronic
circuit for Example 1.1 Circuit

Solution 1.1 We can write the entity part for the black box shown in Fig. 1.2 with
the following steps.
(S1) First, write the reserved word entity as in PR 1.2.

PR 1.2 Program 1.2

entity

(S2) In step 2, we give a name to entity as in PR 1.3.

PR 1.3 Program 1.3

entity my_circuit_name
1.1 Entity 3

(S3) In step 3, write the reserved word is to the end of the line of PR 1.3 as in PR 1.4.

PR 1.4 Program 1.4

entity my_circuit_name is

(S4) In step 4, write the closing tag of entity part as in PR 1.5.

PR 1.5 Program 1.6

entity my_circuit_name is

end my_circuit_name

(S5) In step 5, put a semicolon to the end of the closing tag as in PR 1.6.

PR 1.6 Program 1.6

entity my_circuit_name is

end my_circuit_name;

(S6) In step 6, write the reserved word port as in PR 1.7.

PR 1.7 Program 1.7

entity my_circuit_name is
port
end my_circuit_name;

(S7) In step 7, add parentheses to the port as in PR 1.8.

PR 1.8 Program 1.8

entity my_circuit_name is
port()
end my_circuit_name;

(S8) In step 8, put a semicolon to the end of port() as in PR 1.9.

PR 1.9 Program 1.9
entity my_circuit_name is
port();
end my_circuit_name;

(S9) If we look at the black box in Fig. 1.2, we see that we have two input ports and
three output ports. Let’s give names to these ports as in PR 1.10.

PR 1.10 Program 1.10

entity my_circuit_name is
port( inp1
inp2
outp1
outp2
outp3 );
end my circuit name;
4 1 Entity, Architecture and VHDL Operators

(S10) In step 10, we indicate the type of the ports using the reserved words in and
out as in PR 1.11.
PR 1.11 Program 1.11
entity my_circuit_name is
port( inp1: in
inp2: in
outp1: out
outp2: out
outp3: out );
end my_circuit_name;

(S11) In Step 11, we indicate the data type available at the input and output ports an
in PR 1.12 where we used std_logic for all port data types.

PR 1.12 Program 1.12

entity my_circuit_name is
port( inp1: in std_logic
inp2: in std_logic
outp1: out std_logic
outp2: out std_logic
outp3: out std_logic );
end my circuit name;

(S12) In step 12, we put semicolon to the end of every std_logic except for the last
one as in PR 1.13.

PR 1.13 Program 1.13

entity my_circuit_name is
port( inp1: in std_logic;
inp2: in std_logic;
outp1: out std_logic;
outp2: out std_logic;
outp3: out std_logic );
end my_circuit_name;

The enclosing tag or enclosing line of the program segment in PR 1.13 can also
be written as in PR 1.14. We can also write the enclosing line as “end entity
my_circuit_name”.

entity my_circuit_name is entity my_circuit_name is

port( inp1: in std_logic; port( inp1: in std_logic;
inp2: in std_logic; inp2: in std_logic;
outp1: out std_logic; outp1: out std_logic;
outp2: out std_logic; outp2: out std_logic;
outp3: out std_logic ); outp3: out std_logic );
end entity; end;

PR 1.14 Program 1.14

1.1 Entity 5

It is up to the programmer to select the enclosing line of the entity part.

(S12) In Step 12, add the header lines which are necessary for the data type
std_logic to be meaningful in our VHDL program as in PR 1.15.

PR 1.15 Program 1.15

library IEEE;
use IEEE.std_logic_1164.all;

entity my_circuit_name is
port( inp1: in std_logic;
inp2: in std_logic;
outp1: out std_logic;
outp2: out std_logic;
outp3: out std_logic );
end my circuit name;

(S12) Finally, we can add some comments to our VHDL code. For this purpose,
we can use


Your comment here

format in our program. Then, our entity part becomes as in PR 1.16.

library IEEE; -- IEEE library

use IEEE.std_logic_1164.all; -- Necessary to use the std_logic

entity my_circuit_name is
port( inp1: in std_logic; --Input port
inp2: in std_logic; --Input port
outp1: out std_logic; --Output port
outp2: out std_logic; --Output port
outp3: out std_logic ); --Output port
end my_circuit_name; -- End of entity

PR 1.16 Program 1.16

The VHDL program in PR 1.16 completely describes the input/output ports of

the electronic circuit whose black box representation is given in Fig. 1.2.
The VHDL program in PR 1.16 can also be written as in PR 1.17 where the port
types are written in the same line.

library IEEE; -- IEEE library

use IEEE.std_logic_1164.all; -- Necessary to use the std_logic

entity my_circuit_name is
port( inp1, inp2: in std_logic; --Input ports
outp1, outp2, outp3: out std_logic ); --Output ports
end my_circuit_name; -- End of entity

PR 1.17 Program 1.17

6 1 Entity, Architecture and VHDL Operators

1.2 The Data Types Used in Input/Output Ports

In this section, we will give information about the data types used in VHDL
programming.
std_logic
In PR 1.17 the data type used for the ports is std_logic defined in the package IEEE.
std_logic_1164.all. For std_logic data type, there are 8 possible values available,
and these values are tabulated in Table 1.1.

Table 1.1 std_logic values ‘X’ Unknown

‘0’ Logic 0
‘1’ Logic 1
‘Z’ High Impedance
‘W’ Weak Unknown
‘L’ Weak Low
‘H’ Weak High
‘-’ Don’t Care

std_logic_vector
The std_logic_vector data type is defined in the library IEEE.std_logic_1164.all. If
an I/O port has data type of std_logic_vector, it means that the I/O port has a
number of std_logic values.
std_ulogic
The data type std_ulogic is defined in the package IEEE.std_logic_1164.all. For
std_ulogic data type, there are 9 possible values available, and these values are
tabulated in Table 1.2.

Table 1.2 std_ulogic values ‘U’ Uninitialized

‘X’ Unknown
‘0’ Logic 0
‘1’ Logic 1
‘Z’ High Impedance
‘W’ Weak Unknown
‘L’ Weak Low
‘H’ Weak High
‘-’ Don’t Care

std_ulogic_vector
The std_ulogic_vector data type is defined in the library IEEE.std_logic_1164.all.
If an I/O port has data type of std_ulogic_vector, it means that the I/O port has a
number of std_ulogic values.
1.2 The Data Types Used in Input/Output Ports 7

bit
The bit data type is defined in standard package, i.e., we don’t need to include an
extra package at the header of the VHDL program. For instance, if we use data type
bit for port I/Os, we can write PR 1.17 as in PR 1.18 where it is seen that no header
file is needed.

PR 1.18 Program 1.18

entity my_circuit_name is
port( inp1: in bit;
inp2: in bit;
outp1: out bit;
outp2: out bit;
outp3: out bit);
end my_circuit_name;

bit_vector
The bit_vector data type is defined in standard package, i.e., we don’t need to
include an extra package at the header of the VHDL program. If an I/O port has data
type of bit_vector, it means that the I/O port has a number of bit values.
integer, natural, positive
The data types integer, natural, positive are defined in standard package, i.e., we
don’t need to include an extra package at the header of the VHDL program. The
data type integer is used to represent integer numbers in the range
231 to 231
1.
The data type natural is used to represent the integers in the range 0 to 231
1. On
the other hand, the data type positive is used to represent the integers in the range 1
to 231
1.
unsigned, signed
The data types unsigned and signed are defined in the packages numeric_std and
std_logic_arith. One of these packages should be included in the header of the
VHDL program to be able to use these data types in entity declarations. The data
type unsigned is used to represent unsigned numbers, i.e., nonnegative integers,
and the data type signed is used to represent the signed numbers, i.e., integers.
An electronic circuit with a number of ports which consists of a number of bits
can be expressed with a number of equivalent ways. Let’s illustrate this concept
with an example.
Example 1.2 The black box representation of an electronic circuit is shown in
Fig. 1.3. Describe the electronic circuit ports by a VHDL program.
8 1 Entity, Architecture and VHDL Operators

Fig. 1.3 The black box 4-bit 5-bit

representation of an electronic
circuit for Example 1.2 Electronic
Circuit
4-bit 5-bit

(a) Use the data type std_logic_vector to describe the ports in entity part.
(b) Use the data type bit_vector to describe the ports in entity part.
(c) Use the data type integer to describe the ports in entity part.
(d) Use the data type natural to describe the ports in entity part.
(e) Use the data type positive to describe the ports in entity part.
(f) Use the data type unsigned to describe the ports in entity part.
(g) Use the data type signed to describe the ports in entity part.

Solution 1.2 Let’s solve the part-a in details, and follow the same approach for the
other parts in short.
In Fig. 1.3, the number of bits available at the ports is indicated, however, the
type of the data available at the ports is not clarified. For this reason, we can employ
all the data types mentioned in the question to represent the bits. Otherwise, con-
sidering the type of the data available at the ports, we would select the suitable
VHDL data type representation in our VHDL program. Now let’s proceed with the
solution of part-a.
(a) We can write the entity part for the black box as shown in Fig. 1.3 with the
following steps.
(S1) First, write the reserved word entity as in PR 1.19.

PR 1.19 Program 1.19

entity

(S2) In step 2, we give a name to entity as in PR 1.20.

PR 1.20 Program 1.20
entity FourBit_Circuit

(S3) In step 3, write the reserved word is to the end of the line of PR 1.20 as in PR
1.21.

PR 1.21 Program 1.21

entity FourBit_Circuit is

(S4) In step 4, write the closing tag of entity part as in PR 1.22.

PR 1.22 Program 1.22

entity FourBit_Circuit is

end FourBit_Circuit
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