Digital Logic Design

Chapter No 7

Memory and Programmable Logic

Instructor: Adnan Zafar
Lecturer (EE)
adnan.zafar@ist.edu.pk Department of Electrical Engineering Institute of Space Technology

Topics
Random Access Memory (RAM) Memory Decoding Read-Only Memory (ROM) Programmable Logic Array (PLA) Programmable Array Logic (PAL) Sequential Programmable Devices

MEMORY UNIT
A memory unit is a device to which binary information is transferred for storage and from which information is retrieved when needed for processing. A memory unit is a collection of cells capable of storing a large quantity of binary information.
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Types of memories
There are two types of memories that are used in digital systems
Random Access Memory Read Only Memory

The process of storing new information into memory is referred to as a memory write information and the process of transferring the stored information out of memory is referred to as memory read operation. RAM can perform both write and read operation while ROM allows only read operation.
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ROM
ROM is a Programmable Logic Device (PLD) As the ROM can only perform read operation, it means a suitable binary information is already stored (In a process called programming the device) inside the memory, which can be retrieved or read at any time. However, the existing information cannot be altered by writing because the ROM can only read; it cannot write. Programming means that the hardware procedure which specifies the bits that are inserted into the hardware configuration of the device.
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Programming Logic Device

A PLD is an integrated circuit with internal logic gates connected through electronic paths that behaves similarly to fuses. In start, all fuses are intact. Programming means that blowing those fuses along the paths that must be removed in order to obtain the particular configuration of the desired logic function.
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Memory
RAM
Write and Read from the system

ROM
Read from the system Written during configuration

Programmable Logic Device

ROM PLA FPGA

Symbol used in Array Logic diagrams

Random Access Memory

Block diagram of a Memory unit

It is customary to refer to the number of words (or bytes) in a memory with one of the letters K(kilo) = 210, M(mega) = 220, or G(giga) = 230 8 For Example: 4K = 212, 16M = 224, 8G = 233

Random Access Memory

Content of a 1024 16 Memory
The memory unit with a capacity of 1K words of 16 bits each As 1K = 1024 = 210 and 16bits constitutes of 2 bytes so the memory can accommodate 2048 = 2K bytes Each binary address consists of 10 bits The memory is named as 1K(210) x 16 memory, with 10 bits binary address
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Memory Control

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Write operation (Cycle Time)

The steps that must be taken for the purpose of transferring a new word to be stored into memory are as follows
Apply the binary address of the desired word on the address lines Apply the data bits that must be stored in memory to the data input lines Activate the write input
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Write operation (Cycle Time)

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READ OPERATION (Access time)

The steps that must be taken for the purpose of transferring a stored word out of memory are as follows
Apply the binary address of the desired word on the address lines Activate the read input

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READ OPERATION (Access time)

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Type of Memories
There are two type of memories
Random Access Memory Sequential Access Memory

RAMs (Volatile Memory)

SRAM (Static RAM)
Latches are used to store binary information

DRAM (Dynamic RAM)

Store binary information in the form of electrical charges on capacitors

ROMs
Non Volatile Memory
CD (PROM) RW/CD (EPROM) Memory Sticks (EEPROM)
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RAM TYPES - I
Following are different type of RAMs DRAM (Dynamic RAM)
Must be constantly refreshed by CPU or it will lose its information

SDRAM (Synchronous Dynamic RAM)

Used in most PCs today Synchronized by system clock Faster than DRAM

SRAM (Static RAM)

Faster than DRAM Retains contents without being refreshed
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RAM TYPES - II
RDRAM (Rambus Dynamic RAM)
Faster and more expensive than RDRAM Used in P-IV PCs

DDR-SDRAM (Double Data Rate Synchronous Dynamic RAM)

Just Like SDRAM But higher speed

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Quiz
18/1/12

It is required to generate six repeated timing signals T0 through T5. Design a circuit using Flip Flops Only A Counter and a Decoder Max Time: 10 mins
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Memory Decoding
In addition to the storage components in a memory unit, there is a need for decoding circuits to select the memory word specified by the input address Block diagram of a memory cell
Binary Cell Enables the cell for Reading and Writing

1 bit storing device

1 for Read and 0 for Write

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Memory Cell
Logic diagram of 1 Bit storage Cell
0 1

X 0 X 0 0 X X 1 0 0 1 10

X 1

1 X 0

Read = 1 Write = 0
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Memory Decoding (4x4 RAM)

2 bit address 4 bits at each address

4 4 (22 X 4) RAM

A memory with 2k words of n bits per word would require k address lines that goes into a k X 2k decoder

0 0

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Coincident Decoding
A decoder with k inputs and 2k outputs requires 2k AND gates with k inputs per gate, the number of inputs and number of gates can be reduced by employing two decoders in a 2D selection scheme Two k/2 input decoders are used instead of k input decoder One performs row selection while other perform column selection
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Coincident Decoding
Two dimensional decoding structure for a 1K (210) word memory
Two 5x32 decoders instead of one 10x1024 decoder 5 MSBs of memory address goes into X
1 0 1 0 0

5 LSBs of the memory address goes into Y

Each word within the memory array is selected by the coincidence of one X line and one Y line

0 1 1 0 0

Example = Consider a word whose address is 404 = 01100 10100

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Address Multiplexing for a 64K DRAM

64K = 216, so we use two 8 x 256 decoders for 2D decoding i.e. 28 x 28 = 216 Column Address Strobe

Row Address Strobe

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Read Only Memory

Permanent Storage Allows for configuration of devices to be stored on device without requiring load

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Read Only Memory

32 8 ROM
5 Address Lines (either open or close e.g. fuse) 8 bits at each Memory Address
2k x n ROM will have k x 2k decoder and n OR gates, each OR gate will have 2k inputs

Each connection is programmable

32 x 8 = 256 connections

Each OR gate has 32 inputs

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Read Only Memory

ROM Truth Table
The programmable connections are made according to the contents of each memory location

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Read Only Memory

Programming the ROM
00000 10110110 00001 00011101 00010 11000101

11110 01001010 11111 00110011

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Read Only Memory

Combinational circuit implementation using ROM Input a 3-bit number & Output should be square of the number
8 x 4 ROM would be required B1 = 0 B0 = A0

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Read Only Memory

Block diagram & truth table

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Types of ROM
Mask Programming
Done during the fab process

Programmable ROM (PROM)

All fuses are intact (set to 1) and are Blown

Erasable PROM (EPROM)

Ultraviolet light used to reprogram

Electronically Erasable PROM (EEPROM)

Programmed connections can be erased via electrical signals
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Programmable Logic Devices

Combinational PLDs
Implement function as sum of minterms

Provides product terms of the function

Sum provided by the OR gates

Provide sum of product implementation

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Programmable Logic Array

F1 = AB+AC+ABC F2 = (AC+BC) A B C C
XOR are used to either have the same output or the compliment output e.g. XOR(X,1) = X XOR (X,0) = X

PLA with 3-inputs 4-terms 2-outputs

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Programmable Logic Array

PLA Programming table:
F1 = AB+AC+ABC One input of XOR F2 = (AC+BC) connected to 0
One input of XOR connected to 1

If a variable in the product term appear in its true form, the input variable is 1 If a variable in the product term appear in its compliment form, the input variable is 0 34 If the variable is not there in the product term, the input variable is -

Programmable Array Logic

Typical PAL PAL with 4-inputs / outputs / sections 3 wide AND- OR array per section Commercial PAL Eight inputs / outputs / sections with eight wide AND-OR array Example w(A,B,C,D) = (2,12,13) x(A,B,C,D) = (7,8,9,10,11,12,13,14,15) y(A,B,C,D) = (0,2,3,4,5,6,7,8,10,11,15) z(A,B,C,D) = (1,2,8,12,13) Simplified Boolean Functions w = ABC +ABCD x = A+BCD y = AB+CD+BD z = ABC+ABCD+ACD+ABCD = w+ACD+ABCD 35

Programmable Array Logic

PAL Programming table:
Simplified Boolean Functions w = ABC +ABCD x = A+BCD y = AB+CD+BD z = ABC+ABCD+ACD+ABCD = w+ACD+ABCD

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Programmable Array Logic

w Simplified Boolean Functions w = ABC +ABCD x = A+BCD y = AB+CD+BD z = ABC+ABCD+ACD+ABCD = w+ACD+ABCD

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Sequential Programmable Devices

Sequential Programmable Logic Device (SPLD)
Some times referred as simple PLD to differentiate it from complex PLD

Complex Programmable Logic Device (CPLD) Field Programmable Gate Array (FPGA)

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Sequential (Simple) PLDs

The configuration mostly used for SPLD is the combinational PAL together with D flip flops Each section of the SPLD is called a Macrocell
A macrocell is a circuit that contains a SOP combinational logic function and an optional flip flop 39

SPLD Macrocell

A typical SPLD has from 8 to 10 macrocells within one IC package

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Complex PLDs
The design of a digital system using PLD often requires the connection of several devices to produce the complete specifications. 8-16 macrocells It is more economical to use a CPLD

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Field Programmable Gate Array (FPGA)

A typical FPGA consists of an array of hundreds or thousands of logic blocks The logic blocks are surrounded by programmable input and output blocks All the blocks are connected together via programmable interconnections A typical FPGA logic block consist of look up tables, multiplexers, gates and flip flops
The look up table is a truth table stored in a SRAM and provides the combinational circuit functions for the logic 42 block

Field Programmable Gate Array (FPGA)

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