Document

AREA IN AN INNOVATIVE MANNER
SENDING SMS THROUGH BLOCK SPOT
CHAPTER1 Sending SMS through black spot area in an innovative manner

1.1.Aim :
main aim of this project is to develop an embedded system to send a message from block spot area using GSM and ZIGBEE.
1.2.Description :
Block spot is nothing but an area where we could not find any signal. Even in cities also sometimes we may not have signals inside the room. Through such area sending or calling is tedious. Here our project is useful to create a signal and sending SMS In this work mainly we will use two different frequencies like GSM(1800MHz) and ZIGBEE(2.4GHz). by using these 2 wireless communications first we will create a signal in between zigbee and message will be sent through GSM.
1.3.Operation :
In this project we are having 2 embedded developed boards, one contains ZIGBEE and keypad and the other contains ZIGBEE and GSM. The first board we will place at black spot area and the second board we will place in the signal area. Whenever we will type a message and press an enter button in the first board it will sends the information to the other zigbee board where a GSM is also arranged and the GSM will sends the message for the destination mobile The system uses a compact circuitry built around flash version of at89s52 microcontroller with a non-volatile memory capable of retaining the password data for over ten years. The user can modify the password. Programs are developed in embedded c. Isp is used to dump the code into the microcontroller.
1.4.SOFTWARE: EMBEDDED C RIDE TO WRITE CODE ISP TO BURN THE CHIP
1.5.HARDWARE: AT89S52 BASED OUR OWN DEVELOPED BOARD POWER SUPPLY ZIGBEE MODULES GSM MODEM. MAX232
1.6.BLOCK DIAGRAM OF TRANSMITER
MICROCONTROLLER 2
AT89S52
LCD
KEYPAD TO TYPE THE MESSAGE
Crystal
zigbee
RPS 1.6.block diagram
1.7.RECEIVER :
zigbee
MICROCONTROLLER
Crystal
AT89S52
MAX232
GSM
RPS
1.7.reseiver
CHAPTER 2 EMBEDDED MICROCONTROLLER AND HARDWARE

2.1.INTRODUCTION:
Micro-controller unit is constructed with ATMEL 89C52 Micro-controller chip. The ATMEL AT89C52 is a low power, higher performance CMOS 8-bit microcomputer with 4K bytes of flash programmable and erasable read only memory (PEROM). Its highdensity non-volatile memory compatible with standard MCS-51 instruction set makes it a powerful controller that provides highly flexible and cost effective solution to control applications. Micro-controller works according to the program written in it. The program is written in such a way, so that the output from the ADC will be converted into its equivalent voltage and based on the magnitude of the voltage, it calculates the parameter value. Now this magnitude is again digitalized and fed to LCD display unit through the latch. Micro-controllers are "embedded" inside some other device so that they can control the features or actions of the product. Another name for a micro-controller, therefore, is "embedded controller". Micro-controllers are dedicated to one task and run one specific program. The program is stored in ROM (read-only memory) and generally does not change. Micro-controllers are often low-power devices. A battery-operated Microcontroller might consume 50 milli watts. A micro-controller has a dedicated input device and often (but not always) has a small LED or LCD display for output. A microcontroller also takes input from the device it is controlling and controls the device by sending signals to different components in the device
2.2.MICROCONTROLLER (89C52): 2.2.1.Microprocessor has following instructions to perform:

1.Reading instructions or data from program memory ROM.
2.Intrepreting the instruction and executing it. 3.Microprocessor Program is a collection of instructions stored in nonvolatile memory. 4.Read Data from I/O device 5.Process the input read, as per the instructions read in program memory. 6.Read or write data to Data memory. 7.Write data to I/O device and output the result of processing to O/P device. 2.2.2.NECESSITY OF MICROCONTROLLERS: Microprocessors brought the concept of programmable devices and made many applications of intelligent equipment. Most applications, which do not need large amount of data and program memory, tended to be: Costly: The microprocessor system had to satisfy the data and program
requirements so, sufficient RAM and ROM are used to satisfy most applications .The peripheral control equipment also had to be satisfied. Therefore, almost all-peripheral chips were used in the design. Because of these additional peripherals cost will be comparatively high. An example: 8085 chip needs: An Address latch for separating address from multiplex address and
data.32-KB RAM and 32-KB ROM to be able to satisfy most applications. As also
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Timer / Counter, Parallel programmable port, Serial port, Interrupt controller are needed for its efficient applications. In comparison a typical Micro controller 8051 chip has all that the 8051 board has except a reduced memory as follows. 4K bytes of ROM as compared to 32-KB, 128 Bytes of RAM as compared to 32-KB.
Bulky:
On comparing a board full of chips (Microprocessors) with one chip with all
components in it (Micro controller). Debugging: Lots of Microprocessor circuitry and program to debug. In Micro controller
there is no Microprocessor circuitry to debug. Slower Development time: As we have observed Microprocessors need a lot of debugging at board level and at program level, where as, Micro controller do not have the excessive circuitry and the built-in peripheral chips are easier to program for operation. So peripheral devices like Timer/Counter, Parallel programmable port, Serial Communication Port, Interrupt controller and so on, which were most often used were integrated with the Microprocessor to present the Micro controller .RAM and ROM also were integrated in the same chip. The ROM size was anything from 256 bytes to 32Kb or more. RAM was optimized to minimum of 64 bytes to 256 bytes or more.
Typical Micro controller have all the following features: ->8/16/32 CPU operations. ->One or more I/O ports. -> One or more PWM output ports. ->One or more timer/counters. ->One or more serial communication ->Instruction set rich in I/O & bit
Analog to Digital /Digital to Analog converter interface One or more interrupt inputs and an interrupt controller 2.2.3.Why AT 89C51? :
->Network
controlled
The system requirements and control specifications clearly rule out the use of 16, 32 or 64 bit micro controllers or microprocessors. Systems using these may be earlier to implement due to large number of internal features. They are also faster and more reliable but, the above application is satisfactorily served by 8-bit micro controller. Using an inexpensive 8-bit Microcontroller will doom the 32-bit product failure in any competitive market place. Coming to the question of why to use AT89C52 of all the 8-bit Microcontroller available in the market the main answer would be because it has 4 Kb on chip flash memory which is just sufficient for our application. The on-chip Flash ROM allows the program memory to be reprogrammed in system or by conventional non-volatile memory Programmer. Moreover ATMEL is the leader in flash technology in todays market place and hence using AT 89C52 is the optimal solution.
2.2.4.8052 micro controller architecture:

The 8051 architecture consists of these specific features: Eight bit CPU with registers A (the accumulator) and B Sixteen-bit program counter (PC) and data pointer (DPTR) Eight- bit stack pointer (PSW) Eight-bit stack pointer (Sp) Internal ROM or EPROM (8751) of 0(8031) to 4K (8051) Internal RAM of 128 bytes: 1. Four register banks, each containing eight registers 2. Sixteen bytes, which maybe addressed at the bit level
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3. Eighty bytes of general- purpose data memory Thirty two input/output pins arranged as four 8-bit ports:p0-p3 Two 16-bit timer/counters: T0 and T1 Full duplex serial data receiver/transmitter: SBUF Control registers: TCON, TMOD, SCON, PCON, IP, and IE Two external and three internal interrupts sources. Oscillator and clock circuits.
2.2.4.Functional block diagram of micro controller
2.2.5.The 8052 oscillator and clock: The heart of the 8052 circuitry that generates the clock pulses by which all the internal all internal operations are synchronized. Pins XTAL1 And XTAL2 is provided for connecting a resonant network to form an oscillator. Typically a quartz crystal and capacitors are employed. The crystal frequency is the basic internal clock frequency of the microcontroller. The manufacturers make 8051 designs that run at specific minimum and maximum frequencies typically 1 to 16 MHz.
2.3.Types of memory:
The 8052 have three general types of memory. They are on-chip memory, external Code memory and external Ram. On-Chip memory refers to physically existing memory on the micro controller itself. External code memory is the code memory that resides off chip. This is often in the form of an external EPROM. External RAM is the Ram that resides off chip. This often is in the form of standard static RAM or flash RAM. a) Code memory Code memory is the memory that holds the actual 8052 programs that is to be run. This memory is limited to 64K. Code memory may be found on-chip or off-chip. It is possible to have 4K of code memory on-chip and 60K off chip memory simultaneously. If
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only off-chip memory is available then there can be 64K of off chip ROM. This is controlled by pin provided as EA b) Internal RAM The 8051 have a bank of 128 of internal RAM. The internal RAM is found on-chip. So it is the fastest Ram available. And also it is most flexible in terms of reading and writing. Internal Ram is volatile, so when 8052 is reset, this memory is cleared. 128 bytes of internal memory are subdivided. The first 32 bytes are divided into 4 register banks. Each bank contains 8 registers. Internal RAM also contains 128 bits, which are addressed from 20h to 2Fh. These bits are bit addressed i.e. each individual bit of a byte can be addressed by the user. They are numbered 00h to 7Fh. The user may make use of these variables with commands such as SETB and CLR.
2.3.PIN diagram
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2.4.Special Function registered memory: Special function registers are the areas
of memory that control specific functionality of the 8052 micro controller. a) Accumulator (0E0h): As its name suggests, it is used to accumulate the results of large no of instructions. It can hold 8 bit values. b) B register (0F0h):The B register is very similar to accumulator. It may hold 8-bit value. The b register is only used by MUL AB and DIV AB instructions. In MUL AB the higher byte of the product gets stored in B register. In div AB the quotient gets stored in B with the remainder in A. c)Stack pointer (81h): The stack pointer holds 8-bit value. This is used to indicate where the next value to be removed from the stack should be taken from. When a value is to be pushed onto the stack, the 8051 first store the value of SP and then store the value at the resulting memory location. When a value is to be popped from the stack, the 8052 returns the value from the memory location indicated by SP and then decrements the value of SP. d) Data pointer: The SFRs DPL and DPH work together work together to represent a 16bit value called the data pointer. The data pointer is used in operations regarding external RAM and some instructions code memory. It is a 16-bit SFR and also an addressable SFR. e) Program counter: The program counter is a 16 bit register, which contains the 2 byte address, which tells the 8052 where the next instruction to execute to be found in memory. When the 8051 is initialized PC starts at 0000h. And is incremented each time an instruction is executes. It is not addressable SFR. f) PCON (power control, 87h): The power control SFR is used to control the 8051s
power control modes. Certain operation modes of the 8052 allow the 8052 to go into a type of sleep mode which consume much lee power.
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g) TCON (timer control, 88h) The timer control SFR is used to configure and modify the way in which the 8052s two timers operate. This SFR controls whether each of the two timers is running or stopped and contains a flag to indicate that each timer has overflowed. Additionally, some non-timer related bits are located in TCON SFR. These bits are used to configure the way in
which the external interrupt flags are activated, which are set when an external interrupt occurs.
h) TMOD (Timer Mode, 89h) The timer mode SFR is used to configure the mode of operation of each of the two timers. Using this SFR your program may configure each timer to be a 16-bit timer, or 13 bit timer, 8-bit auto reload timer, or two separate timers. Additionally you may configure the timers to only count when an external pin is activated or to count events that are indicated on an external pin.
i) TO (Timer 0 low/high, address 8A/8C h):
These two SFRs taken together
represent timer 0. Their exact behavior depends on how the timer is configured in the TMOD SFR; however, these timers always count up. What is configurable is how and when they increment in value. j) T1 (Timer 1 Low/High, address 8B/ 8D h): These two SFRs, taken together, represent timer 1. Their exact behavior depends on how the timer is configured in the TMOD SFR; however, these timers always count up. What is Configurable is how and when they increment in value.
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k) P0 (Port 0, address 90h, bit addressable): This is port 0 latch. Each bit of this SFR corresponds to one of the pins on a micro controller. Any data to be outputted to port 0 is first written on P0 register. e.g., bit 0 of port 0 is pin P0.0, bit 7 is pin p0.7. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas a value of 0 will bring it to low level.
l) P1 (port 1, address 90h, bit addressable):This is port latch1. Each bit of this SFR corresponds to one of the pins on a micro controller. Any data to be outputted to port 0 is first written on P0 register. e.g., bit 0 of port 0 is pin P1.0, bit 7 is pin P1.7. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas a value of 0 will bring it to low level
m) P2 (port 2, address 0A0h, bit addressable): This is a port latch2. Each bit of this SFR corresponds to one of the pins on a micro controller. Any data to be outputted to port 0 is first written on P0 register. For e.g., bit 0 of port 0 is pin P2.0, bit 7 is pin P2.7. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas a value of 0 will bring it to low level.
n) P3(port 3,address B0h, bit addressable): This is a port latch3. Each bit of this SFR corresponds to one of the pins on a micro controller. Any data to be outputted to port 0 is first written on P0 register. e.g., bit 0 of port 0 is pin P3.0, bit 7 is pin P3.7. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas a value of 0 will bring it to low level
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o) IE (interrupt enable, 0A8h): The Interrupt Enable SFR is used to enable and disable specific interrupts. The low 7 bits of the SFR are used to enable/disable the specific interrupts, where the MSB bit is used to enable or disable all the interrupts. Thus, if the high bit of IE is 0 all interrupts are disabled regardless of whether an individual interrupt is enabled by setting a lower bit.
p) IP (Interrupt Priority, 0B8h): The interrupt priority SFR is used to specify the relative priority of each interrupt. On 8051, an interrupt maybe either low or high priority. An interrupt may interrupt interrupts. For e.g., if we configure all interrupts as low priority other than serial interrupt. The serial interrupt always interrupts the system, even if another interrupt is currently executing. However, if a serial interrupt is executing no other interrupt will be able to interrupt the serial interrupt routine since the serial interrupt routine has the highest priority.
q) PSW (Program Status Word, 0D0h): The program Status Word is used to store a number of important bits that are set and cleared by 8051 instructions. The PSW SFR contains the carry flag, the auxiliary carry flag, the parity flag and the overflow flag. Additionally, it also contains the register bank select flags, which are used to select, which of the R register banks currently in use.
r) SBUF (Serial Buffer, 99h): SBUF is used to hold data in serial communication. It is physically two registers. One is writing only and is used to hold data to be transmitted out of 8051 via TXD. The other is read only and holds received data from external sources via RXD. Both mutually exclusive registers use address 99h.
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2 .5.I/O ports: One major feature of a microcontroller is the versatility built into the input/output (I/O) circuits that connect the 8051 to the outside world. The main constraint that limits numerous functions is the number of pins available in the 8051 circuit. The DIP had 40 pins and the success of the design depends on the flexibility incorporated into use of these pins. For this reason, 24 of the pins may each used for one of the two entirely different functions which depend, first, on what is physically connected to it and, then, on what software programs are used to program the pins. PORT 0: Port 0 pins may serve as inputs, outputs, or, when used together, as a bi directional low-order address and data bus for external memory. To configure a pin as input, 1 must be written into the corresponding port 0 latch by the program. When used for interfacing with the external memory, the lower byte of address is first sent via PORT0, latched using Address latch enable (ALE) pulse and then the bus is turned around to become the data bus for external memory. PORT 1: Port 1 is exclusively used for input/output operations. PORT 1 pins have no dual function. When a pin is to be configured as input, 1 is to be written into the corresponding Port 1 latch. PORT 2: Port 2 may be used as an input/output port. It may also be used to supply a high order address byte in conjunction with Port 0 low-order byte to address external memory. Port 2 pins are momentarily changed by the address control signals when supplying the high byte a 16-bit address. Port 2 latches remain stable when external memory is addressed, as they do not have to be turned around (set to 1) for data input as in the case for Port 0. PORT 3: Port 3 may be used to input /output port. The input and output functions can be programmed under the control of the P3 latches or under the control of various special function registers. Unlike Port 0 and Port 2, this can have external addressing functions and
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change all eight-port bits when in alternate use, each pin of port 3 maybe individually programmed to be used as I/O or as one of the alternate functions. The Port 3 alternate uses are: Pin P3.0 - RXD P3.1 - TXD P3.2 - INTO 0 P3.3 - INTO 1 P3.4 - T0 P3.5 T1 P3.6 - WR P3.7 - RD Alternate Use Serial data input Serial data output External interrupt 0 External interrupt 1 External Timer 0 input External timer 1 input External memory write pulse External memory read pulse SFR SBUF SBUF TCON.1 TCON.3 TMOD TMOD -
2.6.INTERRUPTS:
Interrupts are hardware signals that are used to determine conditions that exist in external and internal circuits. Any interrupt can cause the 8052 to perform a hardware call to an interrupt handling subroutine that is located at a predetermined absolute address in the program memory. Five interrupts are provided in the 8052. Three of these are generated automatically by the internal operations: Timer flag 0, Timer Flag 1, and the serial port interrupt (RI or TI) Two interrupts are triggered by external signals provided by the circuitry that is connected to the pins INTO 0 and INTO1. The interrupts maybe enable or disabled, given priority or otherwise controlled by altering the bits in the Interrupt Enabled (IE) register, Interrupt Priority (IP) register, and the Timer Control (TCON) register. . These interrupts are mask able i.e. they can be disabled. Reset is a non maskable interrupt which has the highest priority. It is generated when a high is applied to the reset pin. Upon reset, the registers are loaded with the default values. Each interrupt source causes the program to do store the address in PC onto the stack and causes a hardware call to one of the dedicated addresses in the program memory. The appropriate memory locations for each for each interrupt are as follows: Interrupt RESET IE0 (External interrupt 0)
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Address 0000 0003
TF0 (Timer 0 interrupt) IE1 (External interrupt 1) TF1 (Timer 1 interrupt) SERIAL
000B 0013 001B 0023
2.7.CRYSTAL OSCILLATOR:
DESCRIPTION:
If a piezoelectric crystal, usually quartz has electrodes plated on opposite faces and if a potential is applied between these electrodes, forces will be exerted on the bound charges within the crystal. If this device is properly mounted deformations takes place within the crystal, and electromechanical system is formed which will vibrate when properly excited. The resonant frequency and the Q depend upon the crystal dimensions, how the surfaces are oriented with respect to its axes and how the device is mounted. Frequency ranging from few kilohertz to a few megahertz, and Qs in the range from several thousand to several hundred thousand, are commercially available. These extraordinarily high values of Q and the fact that the characteristics of quartz are extremely stable with respect to time and temperature account for the exceptional frequency stability of oscillators incorporating crystals.
Figure1: SYMBOL
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CHARACTERS TICS 2.7.characteristics
It covers every significant performance characteristics of crystals such as resonance frequency, resonance mode, load capacitance, series resistance, holder capacitance, motional inductance and capacitance, and drive level. Quartz crystals are available in a myriad of shapes and sizes, and can range widely in performance specifications. These specifications include resonance frequency, resonance mode, load capacitance, series resistance, holder capacitance, motional inductance and capacitance, and drive level. Understanding these parameters and how they relate to the crystal's performance will allow you to successfully specify crystals for your circuit application. A quartz crystal can be modeled as a series LRC circuit in parallel with a shunt capacitor. Crystals below 30MHz are often specified at the fundamental frequency, but above 30MHz they are typically specified as 3rd, 5th, or even 7th overtone (overtones occur only at odd multiples). It's important to know whether the oscillator is operating in fundamental or overtone mode. An overtone is similar in concept to a harmonic, with the exception that crystal oscillation overtones are not exact integer multiples of the fundamental. Selection of overtone is based upon using the lowest possible overtone that will result in a crystal fundamental frequency below 30MHz. The vendor calibrates a 3rd overtone crystal at the 3rd overtone, not the fundamental. For example, most crystal vendors will automatically give you a 3rd overtone 50MHz crystal if you don't specify
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fundamental mode or an overtone mode. If you plug a 50MHz 3rd overtone crystal into an oscillator that expects a fundamental-mode crystal, you are likely to have an oscillator running at 50/3 or 16.666MHz! If you don't know the frequency mode of your crystal, contact the designer or the manufacturer of the oscillator circuit. The majority of clock sources for microcontrollers can be grouped into two types: those based on mechanical resonant devices, such as crystals and ceramic resonators, and those based on electrical phase-shift circuits such as RC (resistor, capacitor) oscillators. Silicon oscillators are typically a fully integrated version of the RC oscillator with the added benefits of current sources, matched resistors and capacitors, and temperaturecompensation circuits for increased stability. Two examples of clock sources are illustrated in Figure 1. Figure 1a shows a Pierce oscillator configuration suitable for use with mechanical resonant devices like crystals and ceramic resonators, while Figure 1b shows a simple RC feedback oscillator.
2.8. Basic Components of Embedded System

Embedded Hardware, Embedded Software/Firmware, RTOS or Real Time Kernel
2.9. MEMORY
MODELS
2.9.1. MEMORY ORGANIZATION
All 80C52 devices have separate address spaces for program and data memory, as shown in Figures 1 and 2. The logical separation of program and data memory allows the data memory to be accessed by 8-bit addresses, which can be quickly stored and manipulated by
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an 8-bit CPU. Nevertheless, 16-bit data memory addresses can also be generated through the DPTR register. Program memory (ROM, EPROM) can only be read, not written. There can be up to 64k bytes of program memory. In the 80C51, the lowest 4k bytes of program are on-chip. In the ROM less versions, all program memory is external. The read strobe for external program memory is the PSEN (program store enable). Data Memory (RAM) occupies a separate address space from Program Memory. In the 80C52, the lowest 128 bytes of data memory are on-chip. Up to 64k bytes of external RAM can be addressed in the external Data Memory space. In the ROM less version, the lowest 128 bytes are on-chip. The CPU generates read and write signals, RD and WR, as needed during external Data Memory accesses. External Program Memory and external Data Memory may be combined if desired by applying the RD and PSEN signals to the inputs of an AND gate and using the output of the gate as the read strobe to the external Program/Data memory. A.Program Memory After reset, the CPU begins execution from location 0000H. Each interrupt is assigned a fixed location in Program Memory. The interrupt causes the CPU to jump to that location, where it commences execution of the service routine.External Interrupt 0, for example, is assigned to location 0003H. If External Interrupt 0 is going to be used, its service routine must begin at location 0003H. If the interrupt is not going to be used, its service location is available as general purpose Program Memory. The interrupt service locations are spaced at 8-byte intervals: 0003Hfor External Interrupt 0, 000BH for Timer 0, 0013H for External Interrupt 1, 001BH for Timer 1, etc. If an interrupt service routine is short enough (as is often the case in control applications), it can reside entirely within that 8-byte interval. Longer service routines can use a jump instruction to skip over subsequent interrupt locations, if other interrupts are in use.The lowest 4k bytes of Program Memory can either be in the on-chip ROM or in an external ROM. This selection is made by strapping the EA (External Access) pin to either VCC, or
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VSS. In the 80C52, if the EA pin is strapped to VCC, then the program fetches to addresses 0000H through 0FFFH are directed to the internal ROM. Program fetches to addresses 1000H through FFFFH are directed to external ROM. If the EA pin is strapped to VSS, then all program fetches are directed to external ROM. The ROMless parts (8031, 80C31, etc.) must have this pin externally strapped to VSS to enable them to execute from external Program Memory. The read strobe to external ROM, PSEN, is used for all external program fetches. PSEN is not activated for internal program fetches. The hardware configuration for external program execution is shown in Figure 4. Note that 16 I/O lines (Ports 0 and 2) are dedicated to bus functions during external Program Memory fetches. Port 0 (P0 in Figure 4) serves as a multiplexed address/data bus. It emits the low byte of the Program Counter (PCL) as an address, and then goes into a float state awaiting the arrival of the code byte from the Program Memory. During the time that the low byte of the Program Counter is valid on Port 0, the signal ALE (Address Latch Enable) clocks this byte into an address latch. Meanwhile, Port 2 (P2 in Figure 4) emits the high byte of the Program Counter (PCH). Then PSEN strobes the EPROM and the code byte is read into the microcontroller. Program Memory addresses are always 16 bits wide, even though the actual amount of Program Memory used may be less than 64k bytes. External program execution sacrifices two of the 8-bit ports, P0 and P2, to the function of addressing the Program Memory.
B.Data Memory
The CPU in this case is executing from internal ROM. Port 0 serves as a multiplexed address/data bus to the RAM, and 3 lines of Port 2 are being used to page the RAM. The CPU generates RD and WR signals as needed during external RAM accesses. There can be up to 64k bytes of external Data Memory. External Data Memory addresses can be either 1 or 2 bytes wide. One-byte addresses are often used in conjunction with one or more other I/O lines to page the RAM, as shown in Figure 5. Two-byte addresses can also be used, in which case the high address byte is emitted at Port 2. Internal Data Memory is mapped in Figure 6. The memory space is shown divided into three blocks,
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which are generally referred to as the Lower 128, the Upper 128, and SFR space. Internal Data Memory addresses are always one byte wide, which implies an address space of only 256 bytes. However, the addressing modes for internal RAM can in fact accommodate 384 bytes, using a simple trick. Direct addresses higher than 7FH access one memory space, and indirect addresses higher than 7FH access a different memory space. Thus Figure 6 shows the Upper 128 and SFR space occupying the same block of addresses, 80H through FFH, although they are physically separate entities. The Lower 128 bytes of RAM are present in all 80C52 devices as mapped in Figure 7. The lowest 32 bytes are grouped into 4 banks of 8 registers. Program instructions call out these registers as R0 through R7. Two bits in the Program Status Word (PSW) select which register bank is in use. This allows more efficient use of code space, since register instructions are shorter than instructions that use direct addressing. The next 16 bytes above the register banks form a block of bitaddressable memory space. The 80C52 instruction set includes a wide selection of singlebit instructions, and the 128 bits in this area can be directly addressed by these instructions. The bit addresses in this area are 00H through 7FH. All of the bytes in the Lower 128 can be accessed by either direct or indirect addressing. The Upper 128 (Figure 8) can only be accessed by indirect addressing. Figure 9 gives a brief look at the Special Function Register (SFR) space. SFRs include the Port latches, timers, peripheral controls, etc. These registers can only be accessed by direct addressing. Sixteen addresses in SFR space are both byte- and bit-addressable. The bitaddressable SFRs are those whose address ends in 0H or 8H.
2.9.2.Types of memory:
The 89C52 have three general types of memory. They are on-chip memory, external Code memory and external Ram. On-Chip memory refers to physically existing memory on the micro controller itself. External code memory is the code memory that
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resides off chip. This is often in the form of an external EPROM. External RAM is the Ram that resides off chip. This often is in the form of standard static RAM or flash RAM.
a.Code memory
Code memory is the memory that holds the actual 89C52 programs that is to be run. This memory is limited to 64K. Code memory may be found on-chip or off-chip. It is possible to have 4K of code memory on-chip and 60K off chip memory simultaneously. If only off-chip memory is available then there can be 64K of off chip ROM. This is controlled by pin provided as EA
b.Internal
RAM
The 89C52 have a bank of 256 of internal RAM. The internal RAM is found onchip. So it is the fastest Ram available. And also it is most flexible in terms of reading and writing. Internal Ram is volatile, so when 89C52 is reset, this memory is cleared. 256 bytes of internal memory are subdivided. The first 32 bytes are divided into 4 register banks. Each bank contains 8 registers. Internal RAM also contains 256 bits, which are addressed from 20h to 2Fh. These bits are bit addressed i.e. each individual bit of a byte can be addressed by the user. They are numbered 00h to 7Fh. The user may make use of these variables with commands such as SETB and CLR.
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CHAPTER 3 ZigBee
3.1.INTRODUCTION
ZigBee module. The 1 coin, shown for size reference, is about 23 mm (0.9 inch) in diameter.
3.1.zigbee
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ZigBee is a specification for a suite of high level communication protocols using small, low-power digital radios based on an IEEE 802 standard for personal area networks. Applications include wireless light switches, electrical meters with in-home-displays, and other consumer and industrial equipment that requires short-range wireless transfer of data at relatively low rates. The technology defined by the ZigBee specification is intended to be simpler and less expensive than other WPANs, such as Bluetooth. ZigBee is targeted at radio-frequency (RF) applications that require a low data rate, long battery life, and secure networking. ZigBee has a defined rate of 250 kbps best suited for periodic or intermittent data or a single signal transmission from a sensor or input device.[1] ZigBee based traffic management system have also been implemented. The name refers to the waggle dance of honey bees after their return to the beehive.[2]
3.2.Technical overview
ZigBee is a low-cost, low-power, wireless mesh network standard. The low cost allows the technology to be widely deployed in wireless control and monitoring applications. Low power-usage allows longer life with smaller batteries. Mesh networking provides high reliability and more extensive range. ZigBee chip vendors typically sell integrated radios and microcontrollers with between 60 KB and 256 KB flash memory. ZigBee operates in the industrial, scientific and medical (ISM) radio bands; 868 MHz in Europe, 915 MHz in the USA and Australia, and 2.4 GHz in most jurisdictions worldwide. Data transmission rates vary from 20 to 900 kilobits/second. The ZigBee network layer natively supports both star and tree typical networks, and generic mesh networks. Every network must have one coordinator device, tasked with its creation, the control of its parameters and basic maintenance. Within star networks, the coordinator must be the central node. Both trees and meshes allows the use of ZigBee routers to extend communication at the network level.
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3.2.ZigBee protocol stack
ZigBee builds upon the physical layer and medium access control defined in IEEE standard 802.15.4 (2003 version) for low-rate WPANs. The specification goes on to complete the standard by adding four main components: network layer, application layer, ZigBee device objects (ZDOs) and manufacturer-defined application objects which allow for customization and favor total integration. Besides adding two high-level network layers to the underlying structure, the most significant improvement is the introduction of ZDOs. These are responsible for a number of tasks, which include keeping of device roles, management of requests to join a network, device discovery and security. ZigBee is not intended to support powerline networking but to interface with it at least for smart metering and smart appliance purposes. Because ZigBee nodes can go from sleep to active mode in 30 ms or less, the latency can be low and devices can be responsive, particularly compared to Bluetooth wake-up delays, which are typically around three seconds. [3] Because ZigBee nodes can sleep most of the time, average power consumption can be low, resulting in long battery life.
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3.3.Application profiles
The current list of application profiles either published, or in the works are:
Released specifications
o o o o o
ZigBee Home Automation ZigBee Smart Energy 1.0 ZigBee Telecommunication Services ZigBee Health Care ZigBee RF4CE - Remote Control
Specifications under development

o o o o
ZigBee Smart Energy 2.0 ZigBee Building Automation ZigBee Retail Services ZigBee Light Link
The ZigBee Smart Energy V2.0 specifications define an IP-based protocol to monitor, control, inform and automate the delivery and use of energy and water. It is an enhancement of the ZigBee Smart Energy version 1 specifications,[9] adding services for plug-in electric vehicle (PEV) charging, installation, configuration and firmware download, prepay services, user information and messaging, load control, demand response and common information and application profile interfaces for wired and wireless networks. It is being developed by partners including:
HomeGrid Forum responsible for marketing and certifying ITU-T G.hn technology and products HomePlug Powerline Alliance International Society of Automative Engineers SAE International IPSO Alliance SunSpec Alliance
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Wi-Fi Alliance.
In 2009 the RF4CE (Radio Frequency for Consumer Electronics) Consortium and ZigBee Alliance agreed to jointly deliver a standard for radio frequency remote controls. ZigBee RF4CE is designed for a wide range of consumer electronics products, such as TVs and set-top boxes. It promises many advantages over existing remote control solutions, including richer communication and increased reliability, enhanced features and flexibility, interoperability, and no line-of-sight barrier
3.4.Uses
ZigBee protocols are intended for embedded applications requiring low data rates and low power consumption. The resulting network will use very small amounts of power individual devices must have a battery life of at least two years to pass ZigBee certification.
[11]
Typical application areas include:[12]
Home Entertainment and Control Home automation, smart lighting, advanced temperature control, safety and security, movies and music Wireless Sensor Networks' Starting with individual sensors like Telosb/Tmote and Iris from Memsic. Industrial control, Embedded sensing, Medical data collection, Smoke and intruder warning, Building automation.
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3.5.Device types
There are three different types of ZigBee devices:
ZigBee coordinator (ZC): The most capable device, the coordinator forms the root of the network tree and might bridge to other networks. There is exactly one ZigBee coordinator in each network since it is the device that started the network originally. It is able to store information about the network, including acting as the Trust Center & repository for security keys.[13][14]
ZigBee Router (ZR): As well as running an application function, a router can act as an intermediate router, passing on data from other devices. ZigBee End Device (ZED): Contains just enough functionality to talk to the parent node (either the coordinator or a router); it cannot relay data from other devices. This relationship allows the node to be asleep a significant amount of the time thereby giving long battery life. A ZED requires the least amount of memory, and therefore can be less expensive to manufacture than a ZR or ZC.
3.6.Protocols
The protocols build on recent algorithmic research (Ad-hoc On-demand Distance Vector, neuRFon) to automatically construct a low-speed ad-hoc network of nodes. In most large network instances, the network will be a cluster of clusters. It can also form a mesh or a single cluster. The current ZigBee protocols support beacon and non-beacon enabled networks. In non-beacon-enabled networks, an unslotted CSMA/CA channel access mechanism is used. In this type of network, ZigBee Routers typically have their receivers continuously active, requiring a more robust power supply. However, this allows for heterogeneous networks in which some devices receive continuously, while others only transmit when an
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external stimulus is detected. The typical example of a heterogeneous network is a wireless light switch: The ZigBee node at the lamp may receive constantly, since it is connected to the mains supply, while a battery-powered light switch would remain asleep until the switch is thrown. The switch then wakes up, sends a command to the lamp, receives an acknowledgment, and returns to sleep. In such a network the lamp node will be at least a ZigBee Router, if not the ZigBee Coordinator; the switch node is typically a ZigBee End Device. In beacon-enabled networks, the special network nodes called ZigBee Routers transmit periodic beacons to confirm their presence to other network nodes. Nodes may sleep between beacons, thus lowering their duty cycle and extending their battery life. Beacon intervals depend on data rate; they may range from 15.36 milliseconds to 251.65824 seconds at 250 kbit/s, from 24 milliseconds to 393.216 seconds at 40 kbit/s and from 48 milliseconds to 786.432 seconds at 20 kbit/s. However, low duty cycle operation with long beacon intervals requires precise timing, which can conflict with the need for low product cost. In general, the ZigBee protocols minimize the time the radio is on, so as to reduce power use. In beaconing networks, nodes only need to be active while a beacon is being transmitted. In non-beacon-enabled networks, power consumption is decidedly asymmetrical: some devices are always active, while others spend most of their time sleeping. Except for the Smart Energy Profile 2.0, ZigBee devices are required to conform to the IEEE 802.15.4-2003 Low-Rate Wireless Personal Area Network (LR-WPAN) standard. The standard specifies the lower protocol layersthe (physical layer) (PHY), and the (media access control) portion of the (data link layer (DLL)). The basic channel access mode is "carrier sense, multiple access/collision avoidance" (CSMA/CA). That is, the nodes talk in the same way that people converse; they briefly check to see that no one is talking before they start. There are three notable exceptions to the use of CSMA. Beacons
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are sent on a fixed timing schedule, and do not use CSMA. Message acknowledgments also do not use CSMA. Finally, devices in Beacon Oriented networks that have low latency real-time requirements may also use Guaranteed Time Slots (GTS), which by definition do not use CSMA.
3.7.Security services
As one of its defining features, ZigBee provides facilities for carrying out secure communications, protecting establishment and transport of cryptographic keys, cyphering frames and controlling devices. It builds on the basic security framework defined in IEEE 802.15.4. This part of the architecture relies on the correct management of symmetric keys and the correct implementation of methods and security policies.
CHAPTER4 GSM GLOBAL SYSTEM FOR MOBILE COMMUNICATIONS
4.1.INTRODUCTION
The Global System for Mobile Communications, GSM is the most popular standard for mobile phones in the world. The ubiquity of the GSM standard makes international roaming very common between mobile phone operators, enabling subscribers to use their phones in many parts of the world. GSM differs significantly from its predecessors in that both signaling and speech channels are Digital call quality, which means that it is considered a second generation (2G) mobile phone system. This fact has also meant that data communication was built into the system from the 3rd Generation Partnership Project (3GPP).
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From the point of view of the consumers, the key advantage of GSM systems has been higher digital voice quality and low cost alternatives to making calls such as text messaging. The advantage for network operators has been the ability to deploy equipment from different vendors because the open standard allows easy inter-operability. Like other cellular standards GSM allows network operators to offer roaming services which mean subscribers can use their phones all over the world.This GSM modem is a highly flexible plug and play GSM 900 / GSM 1800 / GSM 1900 modem for direct and easy integration RS232, voltage range for the power supply and audio interface make this device perfect solution for system integrators and single user. Voice, Data/Fax, SMS, DTMF, GPRS, integrated TCP/P stack and other features like the GSM / GPRS modules on this homepage.
Definitions The words, Mobile Station (MS) or Mobile Equipment (ME) are used for mobile terminals supporting GSM services.A call from a GSM mobile station to the PSTN is called a mobile originated call (MOC) or outgoing call, and a call from a fixed network to a GSM mobile station is called a mobile terminated call (MTC) or incoming call.In this document, the word product refers to any Multi-Tech product supporting the AT commands interface. 4.2.GSM modem characteristics: Dual Band or Triband GSM GPRS modem (EGSM 900/1800MHz) / (EGSM
900/1800 / 1900 MHz) Designed for GPRS, data, fax, SMS and voice applications Fully compliant with ETSI GSM Phase 2+ specifications (Normal MS) General characteristics:
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Input voltage: 8V-40V Input current: 8mA in idle mode, 150mA in communication GSM 900 @ 12V Input current: 8mA in idle mode, 110mA in communication GSM 1800 @ 12V Temperature range: Operating -20 to +55 degree Celsius; Storage -25 to +70 degree Celsius Overall dimensions: 80mm x 62mm x 31mm / Weight: 200g RS-232 through D-TYPE 9 pin connector RJ11 voice connector 4.3.Interfaces:
Power supply through Molex 4 pin connector SMA antenna connector Toggle spring SIM holder Red LED Power on Green LED status of GSM / GPRS module Basic GSM network (1) Driving idea in GSM: to define several open interfaces. Operator may obtain different network components form different suppliers. Strictly defined interface determines how the functions are proceeding in the network
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and which functions are implemented internally by the network element. GSM provides a means to distribute intelligence in the network. Network divided into four subsystems: Network Subsystem (NSS): call control. Base station Subsystem (BSS): radio path control. Network Management Subsystem (NMS): operation and maintenance. Mobile Station (MS). Difference between 1G and 2G: Symmetric data transfer possibility. Service palette adopted from Narrowband ISDN.
4.3.GSM Network
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4.4.GSM Network elements
35
36
4.5.3G
Technical requirements:
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4.6.Cellular generations
4.6.cellulor generations
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4.7.AT COMMANDS FEATURES

Multi-Tech line settings A serial link handler is set with the following default values (factory settings): auto baud, 8 bits data, 1 stop bit, no parity, RTS/CTS flow control. Please use the +IPR, +IFC and +ICF commands to change these settings. Command line Commands always start with AT (which means ATtention) and finish with a <CR> character. Information responses and result codes Responses start and end with <CR><LF>, except for the ATV0 DCE response format) and the ATQ1 (result code suppression) commands. _ if command syntax is incorrect, an ERROR string is returned. _ If command syntax is correct but with some incorrect parameters, the +CME ERROR: <Err> or +CMS ERROR: <SmsErr> strings are returned with different error codes. _ If the command line has been performed successfully, an OK string is returned. In some cases, such as AT+CPIN? or (unsolicited) incoming events, the product does not return the OK string as a response.
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4.8. GENERAL BEHAVIORS:

SIM Insertion, SIM Removal: From the SIM card Insertion and Removal procedures are supported. There are software functions relying on positive reading of the hardware SIM detect pin. This pin state (open/closed) is permanently monitored. When the SIM detect pin indicates that a card is present in the SIM connector, the product tries to set up a logical SIM session. The logical SIM session will be set up or not depending on whether the detected card is a SIM Card or not. The AT+CPIN? Command delivers the following responses: _ If the SIM detect pin indicates absent, the response to AT+CPIN? is +CME ERROR 10 (SIM not inserted). _ If the SIM detect pin indicates present, and the inserted Card is a SIM Card, the response to AT+CPIN? is +CPIN: xxx depending on SIM PIN state. _ If the SIM detect pin indicates present, and the inserted Card is not a SIM Card, the response to AT+CPIN? Is CME ERROR 10. _ These last two states are not given immediately due to background initialization. Between the hardware SIM detect pin indicating present and the previous results the AT+CPIN? Sends +CME ERROR: 515 (Please When the SIM detect pin indicates card absence, and if a SIM Card was previously inserted, an IMSI detach procedure is performed, all user data is removed product (Phonebooks, SMS etc.). The product then switches to emergency mode.
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4.9.Background initialization After entering the PIN (Personal Identification Number), some SIM user data files are loaded into the product (Phonebooks, SMS status, etc.). Please be aware that it might take some time to read a large phonebook. The AT+CPIN? Command response comes just after the PIN is checked. After this response user data is loaded (in background). This means that some data may not be available just after PIN entry is confirmed by OK. The reading of phonebooks will then be refused by +CME ERROR: 515 or +CMS ERROR: 515 meaning, Please wait, service is not available, init in progress. This type of answer may be sent by the product at several points: _ When trying to execute another AT command before the previous one is completed (before response), _ When switching from ADN to FDN (or FDN to ADN) and trying to read the relevant phonebook immediately, _ When asking for +CPIN? Status immediately after SIM insertion and before the product has determined if the inserted card is a valid SIM Card.
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CHAPTER 5 MAX 232

5.1.INTRODUCTION
_ Meets or Exceeds TIA/EIA-232-F and ITU Recommendation V.28 _ Operates From a Single 5-V Power Supply With 1.0-_F Charge-Pump Capacitors _ Operates Up To 120 kbit/s _ Two Drivers and Two Receivers _ 30-V Input Levels _ Low Supply Current . . . 8 mA Typical _ ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) _ Upgrade With Improved ESD (15-kV HBM) and 0.1-_F Charge-Pump Capacitors is Available With the MAX202 _ Applications TIA/EIA-232-F, Battery-Powered Systems, Terminals, Modems, and Computers
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5.2.Description/ordering information The MAX232 is a dual driver/receiver that includes a capacitive voltage generator to supply TIA/EIA-232-F voltage levels from a single 5-V supply. Each receiver converts TIA/EIA-232-F inputs to 5-V TTL/CMOS levels. These receivers have a typical threshold of 1.3 V, a typical hysteresis of 0.5 V, and can accept 30-V inputs. Each driver converts TTL/CMOS input levels into TIA/EIA-232-F levels. The driver, receiver, and voltage-generator functions are available as cells in the Texas Instruments LinASIC library
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CHAPTER 6 Liquid Crystal Display

6.1.INTRODUCTION
An 8051 program must interact with the outside world using input and output devices that communicate directly with a human being. One of the most common devices attached to an 8051 is an LCD display. Some of the most common LCDs connected to the 8051 are 16x2 and 20x2 displays. This means 16 characters per line by 2 lines and 20 characters per line by 2 lines, respectively. Fortunately, a very popular standard exists which allows us to communicate with the vast majority of LCDs regardless of their manufacturer. The standard is referred to as HD44780U, which refers to the controller chip which receives data from an external source (in this case, the 8051) and communicates directly with the LCD. The 44780 standard requires 3 control lines as well as either 4 or 8 I/O lines for the data bus. The user may select whether the LCD is to operate with a 4-bit data bus or an 8bit data bus. If a 4-bit data bus is used the LCD will require a total of 7 data lines (3 control lines plus the 4 lines for the data bus). If an 8-bit data bus is used the LCD will require a total of 11 data lines (3 control lines plus the 8 lines for the data bus). The three control lines are referred to as EN, RS, and RW. The EN line is called "Enable." This control line is used to tell the LCD that you are sending it data. To send data to the LCD, your program should make sure this line is low (0) and then set the other two control lines and/or put data on the data bus. When the other lines are completely ready, bring EN high (1) and wait for the minimum amount of time required by the LCD datasheet (this varies from LCD to LCD), and end by bringing it low (0) again.
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The RS line is the "Register Select" line. When RS is low (0), the data is to be treated as a command or special instruction (such as clear screen, position cursor, etc.). When RS is high (1), the data being sent is text data which sould be displayed on the screen. For example, to display the letter "T" on the screen you would set RS high. The RW line is the "Read/Write" control line. When RW is low (0), the information on the data bus is being written to the LCD. When RW is high (1), the program is effectively querying (or reading) the LCD. Only one instruction ("Get LCD status") is a read command. All others are write commands--so RW will almost always be low. Finally, the data bus consists of 4 or 8 lines (depending on the mode of operation selected by the user). In the case of an 8-bit data bus, the lines are referred to as DB0, DB1, DB2, DB3, DB4, DB5, DB6,&DB7 .
6.1.1.block diagram
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6.1.2.pin assignment
6.2.Technical Specifications:

Power Requirements: 5 VDC Communication: 4-bit or 8-bit Parallel Interface

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Dimensions: ~3.25L x ~1.75W x 0.25H in (~85L x ~45W x ~6H mm) Operating Temperature: -32 to +158 F (0 to + 70 C)
6.3. interface timing:

.
6.3.interface timing
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6.4.FUNCTION DESCRIPTION:
The LCD display module is built in a LSI controller, the controller has two 8-bit registers, an instruction register (IR) and a DATA register (DR).The IR stores instruction codes, such as display clear and cursor shift, and address information for display data RAM (DDRAM) and character generator (CGRAM). The IR can only be written from MPU. The DR temporarily stores data to be written or read from DDRAM or CGRAM. When address information is written into the IR, then data is stored into the DR from DDRAM or CGRAM. By the register selector (RS) signal, these two registers can be selected.
6.4.1.LCD screen:
LCD screen consists of two lines with 16 characters each. Each character consists of 5x7 dot matrix. Contrast on display depends on the power supply voltage and whether messages are displayed in one or two lines. For that reason, variable voltage 0-Vdd is applied on pin marked as Vee. Trimmer potentiometer is usually used for that purpose. Some versions of displays have built in backlight (blue or green diodes). When used during operating, a resistor for current limitation should be used (like with any LE diode).
6.4.1.LCD screen 6.4.2.LCD Basic Commands

All data transferred to LCD through outputs D0-D7 will be interpreted as commands or as data, which depends on logic state on pin RS:
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RS = 1 - Bits D0 - D7 are addresses of characters that should be displayed. Built in processor addresses built in map of characters and displays corresponding symbols. Displaying position is determined by DDRAM address. This address is either previously defined or the address of previously transferred character is automatically incremented. RS = 0 - Bits D0 - D7 are commands which determine display mode. List of commands which LCD recognizes are given in the table below: Command Clear display Cursor home Entry mode set Display on/off control Cursor/Display Shift Function set Set CGRAM address Set DDRAM address Read BUSY flag (BF) RS RW D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 x Execution Time 1.64Ms 1.64mS 40uS 40uS 40uS 40uS 40uS 40uS 40uS 40uS
1 I/D S D U B x x
1 D/C R/L x F x
0 0 1 DL N 0 1 1
CGRAM address DDRAM address DDRAM address
1 BF
Write to CGRAM or DDRAM 1 Read from CGRAM or DDRAM I/D 1 = Increment (by 1) 0 = Decrement (by 1) S 1 = Display shift on 1
0 D7 D6 D5 D4 D3 D2 D1 D0 1 D7 D6 D5 D4 D3 D2 D1 D0
R/L 1 = Shift right 0 = Shift left DL 1 = 8-bit interface
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0 = Display shift off D 1 = Display on 0 = Display off U 1 = Cursor on 0 = Cursor off B 1 = Cursor blink on 0 = Cursor blink off
0 = 4-bit interface N 1 = Display in two lines 0 = Display in one line F 1 = Character format 5x10 dots 0 = Character format 5x7 dots D/C 1 = Display shift 0 = Cursor shift
6.4.3.LCD Connection
Depending on how many lines are used for connection to the microcontroller, there are 8-bit and 4-bit LCD modes. The appropriate mode is determined at the beginning of the process in a phase called initialization. In the first case, the data are transferred through outputs D0-D7 as it has been already explained. In case of 4-bit LED mode, for the sake of saving valuable I/O pins of the microcontroller, there are only 4 higher bits (D4-D7) used for communication, while other may be left unconnected. Consequently, each data is sent to LCD in two steps: four higher bits are sent first (that normally would be sent through lines D4-D7), four lower bits are sent afterwards. With the help of initialization, LCD will correctly connect and interpret each data received. Besides, with regards to the fact that data are rarely read from LCD (data mainly are transferred from microcontroller to LCD) one more I/O pin may be saved by simple connecting R/W pin to the Ground. Such saving has its price. Even though message displaying will be normally performed, it will not be possible to read from busy flag since it is not possible to read from display.
6.4.4.LCD Initialization
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Once the power supply is turned on, LCD is automatically cleared. This process lasts for approximately 15mS. After that, display is ready to operate. The mode of operating is set by default. This means that: 1. Display is cleared 2. Mode : DL = 1 Communication through 8-bit interface N = 0 Messages are displayed in one line F = 0 Character font 5 x 8 dots 3. Display/Cursor on/off D = 0 Display off U = 0 Cursor off B = 0 Cursor blink off 4. Character entry ID = 1 Addresses on display are automatically incremented by 1 S = 0 Display shift off Automatic reset is mainly performed without any problems. If for any reason power supply voltage does not reach full value in the course of 10mS, display will start perform completely unpredictably. If voltage supply unit cannot meet this condition or if it is needed to provide completely safe operating, the process of initialization by which a new reset enabling display to operate normally must be applied. Algorithm according to the initialization is being performed depends on whether connection to the microcontroller is through 4- or 8-bit interface. All left over to be done after that is to give basic commands and of course- to display messages.
6.4.5.Contrast control:
To have a clear view of the characters on the LCD, contrast should be adjusted. To adjust the contrast, the voltage should be varied. For this, a preset is used which can behave like a variable voltage device. As the voltage of this preset is varied, the contrast of the LCD can be adjusted.
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6.5.Interfacing LCD to 8051
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6.5 interfacing LCD to 8051
CHAPTER 7
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KEYPAD
7.1.INTRODUCTION This block comprises six buttons for controlling the arm manually. Each button is given specified function of moving the arm to left, right, up, down, pick and drop. Whenever the user wants the arm to be moved to left or right, up or down, pick or drop an object the assigned button is pressed. This process is controlled by microcontroller that is loaded with instructions needed for that operation to be performed based on button pressed. These instructions, which are outputs of microcontroller, are given to stepper motor driver through a latch so that it rotates the arm in specified direction.
7.2.4x4 Matrix Keypad:
7.2.1.Standard arrangement: As soon as number of key is greater than 4, a matrix keypad is more economical in term of I/O used. For example a 16key pad arranged as a 4 x 4 matrix can be implemented with only eight port pins. To minimize the number of pins required, the keys should be arranged in as a square matrix as shown in Figure 2. Row lines are connected to microcontroller inputs whereas column lines are connected to microcontroller outputs.
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1 4 7 E
2 5 8 0
3 6 9 F
A B C D
7.2.1.4*4keypad 7.2.2Algorithm: To detect and decode a key, only 4 interrupt routines are executed: the keyboard interrupt and the debounce timer routines both when the key is pressed down and released. A sensible issue when writing routines for keypad management is the mechanical key bounce (see Figure 6). The algorithm must then use a debounce timer to avoid multiple key press detection. The debounce delay depends on the keypad technology (silicon rubber, mechanical...) and how the keypad is used. 7.2.3.Key press detection: To detect a key, all row inputs are programmed in low level
interrupt. Column outputs are set to a low level. When key is pressed down, a keyboard interrupt is generated. Then interrupt is disabled and debounce timer is launched.
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7.2.4.Key release detection:
To detect a key release, active row input (the one on which
key is pressed) is programmed in high level interrupt. When the key is released, a keyboard interrupt is generated. Then interrupt is disabled and debounce timer is launched. 7.2.5.Key debounce: As soon as a key press has been detected (via keyboard
interrupt), a timer is started for the debounce delay. When the timer expires, an interrupt is generated and pressed key decoding is done. Debounce delay can be easily modified by changing the debounce delay definition in the keypad header file .In the demonstration software, timer 1 is used to manage the debounce delay. If the application needs to use the UART, TSC80251G1 embeds a baud rate generator that can be used instead of timer 1 to generate the serial clock. Any other timer than timer 1 can be used for the debounce delay: timer 0 or PCA timer. 7.2.6.Key decoding: A pressed down key is decoded by shifting a low level on columns and reading rows. If a logic 0 is read on a row then the key is decoded and converted to an ASCII value to be able to use it with ANSI C functions.
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7.3.BLOCK DIAGRAM:
A B C D PUSCE VCC GND A X A
KEY PAD
7.3.BLOCK DIAGRAM 7.4.KEYPAD SCHEMATIC DESCRIPTION: Rom the keypad schematic we can observe two 74HC573 latches U2 and U4 and two 74HC148 encoders U1 and U3 connected to pull-up resistors. The latch performs the same operation as buffer, but the only difference is latch amplifies the given input and gives the output. We need 16 by 4 encoder, but its availability in the market is very minimum and too expensive. So , we are using two 8 by 3 74HC148 encoders to satisfy our need. In keypad we totally have 16 switches in which first 8 are connected to U1 and the rest connected to U3 encoder. To know which latch is functioning we are using three NAND logic gates 74HC00 in which outputs E0 and GS are connected to the logic gates. The rest of the outputs of 74HC148 encoders are connected to the latches. These logic gates output , latches output and LED are connected to the connector which is connected to ATMEGA16 micro controller. The function of LED is to check the hardware operation.
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From the keypad schematic we can observe two 74HC573 latches U2 &U3 and two 74HC148 encoders U1 and U3 connected to pull-up resistors. The latch performs the same operation as buffer, but the only difference is latch amplifies the given input and gives the output. We need 16 by 4 encoder, but its availability in the market is very minimum and too expensive. So , we are using two 8 by 3 . 4HC148 encoders to satisfy our need to club the two 8 by 3 encoders we are using nand gates. In keypad we totally have 16 switches in which first 8 are connected to U1 and the rest connected to U3 encoder. To know which latch is functioning we are using three NAND logic gates 74HC00 in which outputs E0 and GS are connected to the logic gates. The rest of the outputs of 74HC148 encoders are connected to the latches. These logic gates output , latches output and LED are connected to the connector which is connected to AT89C51 micro controller. The function of LED is to check the hardware operation.
7.4.1.Function table of 74HC148:
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0 1 2 3 4 5 6 7 1 0 0 0 0 0 0 0 0 0 X 1 X X X X X X X 0 X X X X 1 1 X X 0 X 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X X X
A2 1 1 0 0 0 0 1 1 1 1
A1 1 1 0 0 1 1 0 0 1 1
A0 1 1 0 1 0 1 0 1 0 1
GS E0 1 1 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1
X X X X X X X X X X X X X X X X X 0 X 0 1 0 1 1 1 1 1 0 1 1 1 1
7.4.1. Interfacing the PC AT Keyboard
7.5.Features
Interfacing Standard PC AT Keyboard Requires Only Two I/O Pins. One of them must be an External Interrupt Pin No Extra Hardware Required Complete Example in C, Implementing a Keyboard to Serial Converter
7.6.Introduction:
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Most microcontrollers requires some kind of a human interface. This design note describes one way of doing this using a standard PC AT Keyboard
7.6.1.The Physical Interface: The physical interface between the keyboard and the host is shown in Figure 1. Two signal lines are used, clock and data. The signal lines are open connector, with pull-up resistors located in the keyboard. This allows either the keyboard or the host system to force a line to low level. Two connector types are available, the 5-pin DIN connector of 5D type. Figure 1. The Interface. Keyboard +5V, Clock, Data, GND
7.6.2.Interfacing PC AT Keyboard Application Note Timing: The timing for the data transferred from the keyboard to the host . The protocol is: one start bit (always 0), eight data bits, one odd parity bit and one stop bit (always 1). The data is valid during the low period of the clock pulse. The keyboard is generating the clock signal, and the clock pulses are typically 30-50 low and 30-50 high. The host s s system can send commands to the keyboard by forcing the clock line low. It then pulls the data line low (the start bit). Now, the clock line must be released. The keyboard will count 10 clock pulses. The data line must be set up to the right level by the host before the trailing edge of the clock pulse. After the 10th bit, the keyboard checks for a high level on the data line (the stop bit), and if it is high, it forces it low. This tells the host that the data is received by the keyboard. 7.6.3.Scan Codes: The AT keyboard has a scan code associated with each key. When a key is pressed, this code is transmitted. If a key is held down for a while, it starts repeating. The repeat rate
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is typically 10 per second. When a key is released, a break code ($F0) is transmitted followed by the key scan code. For most of the keys, the scan code is one byte. Some keys like the Home, Insert and Delete keys have an extended scan code, from two to five bytes. 7.6.4.The Software: The code supplied with this application note is a simple keyboard to RS-232 interface. The scan codes received from the keyboard are translated into appropriate ASCII characters and transmitted by the UART. The source code is written in C, and is easily modified and adaptable to all microcontrollers with SRAM. 7.6.5.The algorithm: keyboard reception is handled by the interrupt function 7.6.6.INT0_interrupt.: The reception will operate independent of the rest of the program. The algorithm is quite simple: Store the value of the data line at the leading edge of the clock pulse. This is easily handled if the clock line is connected to the INT0 or INT1 pin. The interrupt function will be executed at every edge of the clock cycle, and data will be stored at the falling edge. After all bits are received, the data can be decoded. This is done by calling the decode function. For character keys, this function will store an ASCII character in a buffer. It will take into account if the shift key is held down when a key is pressed. Other keys like function keys, navigation keys (arrow keys, page up/down keys etc.) and modifier keys like Ctrl and Alt are ignored. The mapping from scan codes to ascii characters are handled with table look-ups, one table for shifted characters and one for un-shifted.
7.7.Modifications and improvements

If the host falls out of sync with the keyboard, all subsequent data received will be wrong. One way to solve this is to use a time out. If 11 bits are not received within 1.5 ms, some error have occurred. The bit counter should be reset and the faulty data discarded. If
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keyboard parameters like typematic rate and delay are to be set, data must be sent to the keyboard. This can be done as described earlier. For the commands, see the keyboard manufacturers specifications. Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Parity Stop Start Clock - Data
Applications
1.System is very useful where the signal is not present 2.Used in emergency situations 3.Very useful in when the subscriber present in rural areas
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Conclusion
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In our daily life we are observing many situations where the signal is not available to make calls or sending messages.Previous existing systems are applicable inonlywhere the signal is present Hence we are using this project to sending sms in an emergency situations when present in the blockspot area.
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AREA IN AN INNOVATIVE MANNER

SENDING SMS THROUGH BLOCK SPOT

CHAPTER1 Sending SMS through black spot area in an innovative manner

AREA IN AN INNOVATIVE MANNER

SENDING SMS THROUGH BLOCK SPOT

1.4.SOFTWARE: EMBEDDED C RIDE TO WRITE CODE ISP TO BURN THE CHIP

1.6.BLOCK DIAGRAM OF TRANSMITER

AREA IN AN INNOVATIVE MANNER

SENDING SMS THROUGH BLOCK SPOT

KEYPAD TO TYPE THE MESSAGE

RPS 1.6.block diagram

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SENDING SMS THROUGH BLOCK SPOT

CHAPTER 2 EMBEDDED MICROCONTROLLER AND HARDWARE

AREA IN AN INNOVATIVE MANNER

SENDING SMS THROUGH BLOCK SPOT

2.2.MICROCONTROLLER (89C52): 2.2.1.Microprocessor has following instructions to perform:

AREA IN AN INNOVATIVE MANNER

SENDING SMS THROUGH BLOCK SPOT

AREA IN AN INNOVATIVE MANNER

SENDING SMS THROUGH BLOCK SPOT

2.2.4.8052 micro controller architecture:

AREA IN AN INNOVATIVE MANNER

SENDING SMS THROUGH BLOCK SPOT

2.2.4.Functional block diagram of micro controller

AREA IN AN INNOVATIVE MANNER

SENDING SMS THROUGH BLOCK SPOT

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SENDING SMS THROUGH BLOCK SPOT

i) TO (Timer 0 low/high, address 8A/8C h):

These two SFRs taken together

AREA IN AN INNOVATIVE MANNER

SENDING SMS THROUGH BLOCK SPOT

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SENDING SMS THROUGH BLOCK SPOT

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Address 0000 0003

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000B 0013 001B 0023

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CHARACTERS TICS 2.7.characteristics

AREA IN AN INNOVATIVE MANNER

SENDING SMS THROUGH BLOCK SPOT

2.8. Basic Components of Embedded System

2.9.1. MEMORY ORGANIZATION

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SENDING SMS THROUGH BLOCK SPOT

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SENDING SMS THROUGH BLOCK SPOT

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SENDING SMS THROUGH BLOCK SPOT

AREA IN AN INNOVATIVE MANNER

SENDING SMS THROUGH BLOCK SPOT

AREA IN AN INNOVATIVE MANNER