Lic Lab Manual

LINEAR INTEGRATED CIRCUITS LAB RECORD NOTE BOOK
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Pin Details of IC 741: Logic Symbol of IC 741:
Verification of Op-amp IC 741:
Specifications for IC 741
Supply Voltage 22 V
Input Voltage 15 V
Power Dissipation 500 mW
Operating Temperature Range -55C to 25C
Electrical Characteristics
S. No Characteristics Minimum Maximum
1 Input bias current 50nA 80 nA
2 Input Voltage range 12 V 15 V
3 Supply Current 1.7mA 2.8A
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OP AMP BASICS
Ideal Operational Amplifier:
The Operational Amplifier, or Op-amp as it is more commonly called, is one of the basic
building blocks of Analogue Electronic Circuits. It is a linear device that has all the properties
required for nearly ideal D.C. amplification and is used extensively in signal conditioning,
filtering or to perform mathematical operations such as add, subtract, integration and
differentiation. An Operational Amplifier is a 3-terminal device that consists basically of two high
impedance inputs, one an Inverting input marked with a negative sign, ("-") and the other a
Non-inverting input marked with a positive plus sign ("+"). An ideal Operational Amplifier also
has a Low Output Impedance that is referenced to a common ground terminal. They can also
operate from either a single or a dual () power supply.
An Operational Amplifier on its own has a very high open-loop d.c. gain and by applying
some form of negative feedback we can produce an amplifier circuit that has a very precise gain
characteristic. An operational amplifier only responds to the difference between the voltages on
its two input terminals, known commonly as the Differential Input Voltage and not to their
common potential. Thus, the gain of the Op-amp is known as the Open Loop Differential Gain,
and is given the symbol (Ao).
Ideal Operational Amplifier and its Idealized Characteristics
From these "idealized" characteristics below , we can see that the input resistance is
infinite, so no current flows into either input terminal (the current rule) and that the differential
input offset voltage is zero (the voltage rule). It is important to remember these two properties
as they help understand the workings of the circuit with regards to analysis and design of
operational amplifier circuits. However, real op-amps such as the uA741, for example do not
have infinite gain or bandwidth but have a typical "Open Loop Gain" which is defined as the
amplifiers output amplification without any external feedback signals connected to it and for a
typical operational amplifier is about 100dB at d.c. (zero Hz). This output gain decreases
linearly with frequency down to "Unity Gain" or 1, at about 1MHz and this is shown in the
following open loop gain response curve.
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Open-loop Frequency Response Curve
Operational Amplifier Bandwidth:
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Characteristics of Op-amp:
PARAMETER IDEALIZED CHARACTERISTICS
Voltage Gain, (A)
Infinite - The main function of an operational
amplifier is to amplify the input signal and the
more open loop gain it has the better, so for an
ideal amplifier the gain will be infinite.
Input Impedance, (Zin)
Infinite - Input impedance is assumed to be
infinite to prevent any current flowing from the
source supply into the amplifiers input circuitry.
Output Impedance, (Zout)
Zero - The output impedance of the ideal
operational amplifier is assumed to be zero so
that it can supply as much current as necessary
to the load.
Bandwidth, (BW)
Infinite - An ideal operational amplifier has an
infinite Frequency Response and can amplify any
frequency signal so it is assumed to have an
infinite bandwidth.
Offset Voltage, (Vio)
Zero - The amplifiers output will be zero when
the voltage difference between the inverting and
non-inverting inputs is zero.
From this frequency response curve we can see that the product of the gain against
frequency is constant at any point along the curve. Also that the unity gain (0dB) frequency,
determines the gain of the amplifier at any point along the curve. This constant is generally
known as the Gain Bandwidth Product or GBP. Therefore, GBP = Gain x Bandwidth or A x BW.
For example, from the graph above the gain of the amplifier at 100 KHZ = 20dB or 10,
then the GBP = 100,000Hz x 10 = 1,000,000. Similarly, a gain at 1 kHz = 60dB or 1000,
therefore the GBP = 1,000 x 1,000 = 1,000,000.
The Voltage Gain (A) of the amplifier Voltage Gain (A) = V out / V in and in Decibels or
(dB) is given as:
20 log (A) or 20 log (V out / V in) in dB
Operational Amplifier Bandwidth:
The bandwidth of an operational amplifier is the frequency range over which the voltage
gain of the amplifier is above 70.7% or -3dB (where 0dB is the maximum) of its maximum
output value as shown below.
Here we have used the 40dB line as an example. The -3dB or 70.7% of V max down
point from the frequency response curve is given as 37dB. Taking a line across until it intersects
with the main GBP curve gives us a frequency point just above the 10 KHZ line at about 12 to
15 KHZ. We can now calculate this more accurately as we already know the GBP of the
amplifier, in this particular case 1MHz.
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Circuit Diagram of Inverting Amplifier:
Design Procedure:
A
CL
= 1; R
1
= 1K
A
CL
= V
o
/ V
i
= - R
f
/ R
1
R
f
= A
CL
R
1
= 1K
Tabulation:
S. No
Input Voltage (V
in
)
in Volts
Output Voltage V
O
in Volts
Theoretical Value Practical Value
1
2
3
4
5
6
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EXP. NO : 01
INVERTING, NON - INVERTING AND DIFFERENTIAL
AMPLIFIERS
DATE :
Aim:
To design, construct and test the performance of Inverting, Non-inverting amplifier and
differential amplifiers using op-amp IC 741.
Components Required:
S. No Component Name Range Type Qty
1 Op-amp
2 Power Supply
3 Resistor
4 Capacitor
5 Voltmeter
6 Breadboard
7 Signal generator
Theory:
Inverting Amplifier:
The inverting amplifier is the most widely used in all the op-amp circuits.
The output voltage V
O
is fed back to inverting input terminal through the R
f
- R
1
network where
R
f
is the feedback resistor. The input signal V
i
is applied to the inverting input terminal through
R
1
and non-inverting input terminal of op-amp is grounded.
V
O
= (R
f
/ R
1
) V
i
A
CL
= Vo / V
i =
- R
f
/ R
1
The Negative sign indicates a phase shift of 180 between input (V
i
) and Output (Vo).
Non-Inverting Amplifier:
The non inverting amplifier circuit amplifies without inverting the input
signal. In this circuit, the input is applied to the non inverting input terminal and inverting input
terminal is grounded such a circuit is called non inverting amplifier. It is also having a negative
feedback system as output is fed back to the inverting input terminal.
V
O
= (1+ (R
f
/ R
1
) V
i
A
CL
= V
o
/ V
i
= 1+ (R
f
/ R
1
)
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Circuit Diagram of Non Inverting Amplifier:
Design Procedure:
A
CL
= 2; R
1
= 1K
A
CL
= V
o
/ V
i
= 1+ (R
f
/ R
1
) = 2
R
f
= (A
CL
-1) R
1
= 1K
Tabulation:
S. No
Input Voltage (V
in
)
in Volts
Output Voltage V
O
in Volts
1
2
3
4
5
6
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Differential Amplifier (Subtractor):
A circuit that amplifies the difference between the two signals is called
difference amplifier. This type of amplifiers is mostly used in instrumentation circuit.
V
O
= (R
f
/ R
1
) (V
1
-V
2
)
The main purpose of the difference amplifier stage is to provide high gain to the difference
mode signal and cancel the common mode signal i.e., it should have high CMRR.
Procedure:
1. Make the connections as per the circuit diagram.
2. Vary the input voltage using regulated DC power supply then measure and tabulate
the corresponding output voltage.
3. Compare theoretical Output with the actual output obtained from the circuit.
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Circuit Diagram for Differential Amplifier:
Design Procedure:
R
1
= R
2
= 1K
R
3
= R
f
= 4.7 K
V
O
= (R
f
/ R
1
) [V
1
- V
2
]
Tabulation:
S. No
Input Voltage (V
in
)
in Volts
Output Voltage V
O
in Volts
V
1
V
2
1
2
3
4
5
6
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Result:
Thus the inverting, non-inverting and differential amplifiers were designed, constructed
and its performance was tested using op-amp IC 741.
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Viva Questions and Answers:-
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Circuit Diagram for Differentiator:
Design:
dV
i
V = - R C
1 O f dt
R =1.6K
f
R =1K
1
1
f =1KHz =
2
R C
1 f
1
C = =0.16
f
1
2
f R
f
;
R R
1 f
R = =615
eq
R +R
1 f
Model Graph:
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EXP. NO : 02
DIFFERENTIATOR AND INTEGRATOR USING OP-AMPS
DATE :
Aim:
To design, construct and test the performance of Differentiator and Integrator using Op-
amp IC 741.
S. No Component Name Range Type Quantity
1 Op-amp
2 Power Supply
3 Resistor
4 Capacitor
5 Voltmeter
6 Breadboard
7 Signal generator
Theory:
Differentiator:
One of the simplest of the op-amp circuits that contain capacitor is the differentiating
amplifier or differentiator. As the name Differentiator suggests, the circuit performs the
mathematical operation of differentiation. That is, the output waveform is the derivative of input
waveform. But by using the differentiator at high frequencies, it may becomes unstable and
break into oscillation. The impedance at input also decreases with increase in frequency;
thereby making the circuit sensitive to high frequency noise.
Analysis of Practical Differentiator:
As the input current of op-amp is zero, there is no current input at node B. Hence it is at
the ground potential. From the concept of virtual ground, node A is also at the ground potential
and hence V
B
= V
A
= 0V.
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Circuit Diagram for Integrator:
Design: R
1
= 1K, C=1F and f = 1KHZ
T = 1/f
f=1/2 R
1
C
f
V
O
= V
in
T / (R
1
C
1
) = 1.6K
R
eq
= R
1
*R
f
/ (R
1
+R
f
) = 1.610
6
/2.610
3
= 615
Model Graph:
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For the current I, we can write,
in
V - V
in A
I = ----------------- V = 0
A
Z
1
V
in
I = Where Z = R in series with C
1 1 1
Z
1
So in Laplace domain we can write,
1+sR C
1
1 1
Z = R + =
1 1
sC sC
1 1
sC V (s)
1
I =
1+sR C
1 1
Now the current I is,
1
V - V V
A O O
I = = -
1
R R
f f
V (s)
O
In Laplace, I = -
1
R
f
d (V - V ) dV
A O O
and I = C = - C
2 f f
dt dt
Taling Laplace Transform we get,
I = - sC V (s)
o 2 f
Applying KCL
1
1
1
]
at node A,
I = I +I
1 2
V (s) sC Vin (s)
O 1
= - - sC V (s)
o f
1+sR C R
1 1 f
-sR C V (s)
1 in f
V (s) =
O
[1+ s C R ] [1+ s C R ]
1 1 f f
If C R = C R then
1 1 f f
1
]
1
1
1
]
-sR C V (s)
1 in f
V (s) =
O 2
1+ s C R
1 1
The time constant R C is much greater than R C or R C and hence
1 1 1 f f f
the equation becomes
V (s) =
O
- sR C V (s)
1 in f
The output voltage is the R C times the differentiation of the input.
1 f
dV (t) d
in
V (t) = - R C ------------ as s=
O f 1
dt dt
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Tabular Column: Differentiator
S.NO
Input Voltage (V
i
) in
volts
Output Voltage (V
o
)
in volts
Time period in ms
Tabular Column: Integrator
S.NO
Input Voltage (V
i
) in
volts
Output Voltage (V
o
)
in volts
Time period in ms
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Procedure for Differentiator and Integrator:
1. Make the Connections as per the circuit diagram.
2. Set the 1 KHz square wave input using function generator and obtain the output
waveform on the CRO.
3. Determine and tabulate the amplitude, time period of the output waveform.
4. Draw the graph for output.
Integrator:
One of the simple op-amp circuits that also contain the capacitor is known as integrator.
As the name integrator suggests, the circuit performs the mathematical operation of
integration. That is, the output waveform is the integration of input waveform.
Analysis of Practical Integrator:
As the input of op-amp is zero, the node B still at ground potential. Hence the node A is
also at the ground potential from the concept of virtual ground. So, V
A
= 0.
(V - V )
in A
I = ----------------- V = 0
A
R
1
V
in
I =
R
1
d (V - V )
A O
Similarly I = - C
1 f
dt
dV
A
= - C
f
dt
V - V
A O
And I =
2
R
f
V
O
= -
R
f
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At node A, applying KCL
I = I + I
1 2
dV V V
O O in
= - C -
f
R dt R
1 f
Taking Laplace transform of above Equation,
V (s)
O
V (s) / R = - s C V (s) -
in 1 O f
R
f
.
1
= - V (s) [s C + ]
O f
R
f
[1+ s C R ]
f f
= - V (s)
O
R
f
R
f
V (s) = - V (s)
in O
R [1+ s R C ]
1 f f
1
V (s) = - V (s)
in O
R
1
sR C +
1 f
R
f
} }
When R is very large than R / R can be neglected and hence circuit behaves like
1 f f
an ideal integrator as
1
V (s) = - V (s)
in O
sR C
1 f
1
V (t) = - V (t) dt --------- as 1/s = dt
O in
sR C
1 f
Result:
Thus the differentiator and integrator circuits were designed, constructed and its
performance was tested using op-amp IC 741.
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Circuit Diagram for Instrumentation Amplifier:
Design:
f1 f2 G
R =2K,R =1K and R =R =R =100K
1 2
1
1
1
]
1
]
1
1
1
]
1
]
R 2R
2 f
Gain = 1+
R R
1 G
Output Voltage (Vo)= Gain V -V
2 1
R 2R
2 f
Output Voltage (Vo)= 1+ V -V
2 1
R R
1 G
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EXP. NO : 03
INSTRUMENTATION AMPLIFIER USING OP-AMP
DATE :
Aim:
To design, construct and test the performance of Instrumentation amplifier using
operational amplifiers.
1 Op-amp
2 Power Supply
3 Resistor
4 Capacitor
5 Voltmeter
6 Breadboard
7 Connecting Wires
Theory:
Need for Instrumentation Amplifier:
The measurement of physical quantities is generally carried out with the help of a device
called as Transducer. A Transducer is a device which coverts one form of energy into electrical
energy. But most of the transducer outputs are generally of very low level signals (few mV or
V). Such a low level signals are not sufficient to drive the next stage of the system. The special
amplifier which is used for such a low level amplification with high CMRR, high input impedance
to avoid loading, low power consumption and some other features is called Instrumentation
amplifier.
The Commonly used instrumentation amplifier circuit is one using three op-amps. The
circuit provides high input resistance for accurate measurement of signals from the transducers.
In this circuit a non inverting amplifier is added to each of the basic difference amplifier input.
The circuit is shown in the following figure 1.
The op-amps A
1
and A
2
are the non inverting amplifiers forming the input or first stage of
the instrumentation amplifier. The op-amp A
3
is the normal difference amplifier forming the
output stage of the amplifier
Instrumentation Amplifier:
From the figure 1, the output state is a standard basic differential amplifier. If the output
of the op-amp A
1
is V
O1
and the output of the op-amp A
2
is V
O2
, We can write
1
]
R
2
Output Voltage (Vo)= V -V
O2 O1
R
1
--------- 1
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Tabular Column:
S. No
Input Voltage (V
in
)
in Volts
Output Voltage V
O
in Volts
V
1
V
2
1
2
3
4
5
6
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Figure: 1
1
]
R
2
Output Voltage (Vo)= V -V
O2 O1
R
1
--------- 1
The node A potential of op-amp A
1
is V
1
. From the realistic assumption the potential of
node B is also V
1
and hence potential of G also V
1
.
The node D potential of op-amp A
2
is V
2
. From the realistic assumption, the potential of
node C is also V
2
and hence potential of H is also V
2
.
The input current of op-amp A
1
and A
2
both are zero. Hence current I remain same
through R
f1
, R
G
and R
f2
.
Applying Ohms law between the nodes E and F we get,
V - V
O1 O2
I = - -(2)
R +R +R
G f1 f2
Let R =R =R - -(3)
f1 f2 f
V - V
O1 O2
I = - -(4)
2R +R
G f
from the observation of nodes G and H,
V - V V - V
H 1 G 2
I = = - -(5)
R R
G G
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Equating the two equations (4) and (5),
V - V V - V
1 O1 O2 2
= - -(6)
2R +R R
G G f
V - V V - V
1 O2 O1 2
= - -(7)
2R +R R
G G f
(V - V )(2R +R )
1 2 G f
V - V = --(8)
O2 O1
R
G
| | | |

\ . \ .
| | | |

\ . \ .
Substituting the V - V , in the equation (1),
O2 O1
2R +R R
f G 2
V =(V - V ) - -(9)
1 O 2
R R
G 1
2R R
f 2
V =(V - V ) 1+ - -(10)
1 O 2
R R
G 1
Result:
Thus the Instrumentation amplifier using operational amplifiers were designed,
constructed and its performance was verified.
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Circuit Diagram for Butterworth Active Low Pass Filter:
Design of Low Pass Filter:
1. Select f
H
= 3 KHz
2. Set R
2
= R
3
= R and C
2
= C
3
= C =0.01f (C is always 1f).
3. Calculate R from f
H
= 1 / 2RC
R = 1 / 2 f
H
C = 5.3K = R
2
= R
3
4. For Butterworth response
1
1
1
]
R
f
A =1+
F
R
1
= 1.586 ; R
f
= (1.586 -1) R
1
5. Choose R
1
=10 K then R
f
= 5.86 K
Model Graph:
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EXP. NO : 04 ACTIVE LOW PASS, HIGH PASS BAND PASS FILTERS USING
OP-AMP
DATE
:
Aim:
To design, construct and obtain the frequency response of active Low pass filter and
Band pass filter using operational amplifiers.
1 Op-amp
2 Power Supply
3 Resistor
4 Capacitor
5 Voltmeter
6 Breadboard
7 Signal Generator
Theory:
Low Pass Filter:
The practical response of the filter must be very close to an ideal one. In case of
low pass filter, it is always desirable that the gain rolls off very fast after the cut off frequency,
in the stop band. In case of first order filter, it rolls off at a rate of 20 dB/ decade. In case of
second order filter the gain rolls of at a rate of 40dB / decade. Thus the slope of the frequency
response after f=f
H
is -40dB / decade, for a second order low pass filter. The first order filter
can be converted to second order type by using an additional RC network. The gain of the
second order filter is determined by R
1
and R
f
. The f
H
is designed by R
2
, C
2
, R
3
, and C
3
as
follows.
1
f =
H
2
R R C C
2 3 2 3
. For a second order low pass Butterworth filter, the
voltage gain magnitude equation is
1
1
]
A V
F o
=
4
V
in
f
1+
f
H
Where
1
1
1
]
R
f
A =1+
F
R
1
Pass band gain of the filter
1
f =
H
2
R R C C
2 3 2 3
--High Cutoff frequency in Hz and F=Input Frequency (Hz)
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Tabular Column: Low Pass Filter
V
in
=
S.No Frequency in Hz
Output Voltage
(V
O
) in Volts
Gain = 20 log
(V
O
/V
in
) dB.
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Procedure: Low Pass Filter
2. Vary the frequency of input signal and note the corresponding output voltage.
3. Calculate the gain and draw the graph.
4. Find the Higher cut off frequency.
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Circuit Diagram for 2
nd
order Butterworth Active High Pass Filter:
Design of High Pass Filter:
1. Select f
L
= 3 KHz
2. Set R
2
= R
3
= R and C
2
= C
3
= C =0.01f (C is always 1f).
3. Calculate R from f
L
= 1 / 2RC
R = 1 / 2 f
L
C = 5.3K = R
2
= R
3
4. For Butterworth response
1
1
1
]
R
f
A =1+
F
R
1
= 1.586 ; R
f
= (1.586 -1) R
1
5. Choose R
1
=10 K then R
f
= 5.86 K
Model Graph:
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High Pass Filter:
A second order high pass filter can be obtained from a second order low pass
filter simply by interchanging the frequency determining resistors and capacitors. The Voltage
gain magnitude of the second order high pass filter is given by
1
1
]
A V
F o
=
V 4
in
f
L
1+
f
Where A
F
= 1.586 Pass band gain; f
L
= Low cutoff frequency and f= frequency of the input
signal
1
f =
L
2
R R C C
2 3 2 3
Since second order low pass and high pass filters are alike except that the positions of resistors
and capacitors are being interchanged, the design and frequency scaling procedures are same
for high pass filter as those for the low pass filter.
Procedure: High Pass Filter
2. The input voltage is set to the constant value say 2V.
3. Vary the frequency of input signal and note the corresponding output voltage.
4. Calculate the gain and draw the graph.
5. Find the Low and High cut off frequencies.
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Tabular Column: High Pass Filter
V
in
=
Output Voltage
(V
O
) in Volts
Gain = 20 log
(V
O
/V
in
) dB.
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Circuit Diagram for Butterworth Wide Band Pass Filter:
Design of Wide Band Pass Filter:
1. Select f
L
= 3 KHz and f
H
= 10 KHz.
2. Choose C
1
= C
2
= 0.01f.
3. f
L
= 1 / 2 R
2
C
2
then R
2
=1 / 2 f
L
C
2
= 5.3K
4. f
H
= 1 / 2 R
1
C
1
then R
1
=1 / 2 f
H
C
1
= 1.6K
5. Band Width= f
H
- f
L
MODEL GRAPH:
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Tabular Column: Band Pass Filter
V
in
=
Output Voltage
(V
O
) in Volts
Gain = 20 log
(V
O
/V
in
) dB.
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Result:
Thus the active low pass, High pass and band pass filter circuits were designed,
constructed and tested the performance using op-amps and cut off frequencies were found.
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Circuit Diagram for Astable Multivibrator Using Op-amp:
Design:
R =R = R = 6.8K
1 2
C=0.01
f
R
2
= =0.5
R + R
1 2
1
1
]
1+
T = 2RC ln =0.15ms
1-
1
Frequency(f)= =6.7KHz
T
Model Graph:
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EXP. NO : 05 ASTABLE, MONOSTABLE MULTIVIBRATORS AND SCHMITT
TRIGGER USING OP-AMPS
DATE :
Aim:
To design, construct and test the performance of astable and monostable multivibrators
using operational amplifier.
1 Op-amp
2 Power Supply
3 Resistor
4 Capacitor
5 Voltmeter
6 Breadboard
7 Signal generator
Theory:
Astable Multivibrator:
Astable Multivibrator is a square wave generator. A simple op-amp square
wave generator is also called a free running generator. The principle of generation of square
wave output is to force an op-amp to operate in saturation region. = R
2
/ (R
1
+R
2
) of output is
feedback to the positive input terminal. Thus the reference voltage V
R
is V
O
and may takes
value as + V
sat
or - V
sat
. The output is also feedback to the negative input terminal. After
interchanging by means of the low pass RC combination whenever input at negative input
terminal slightly exceeds reference voltage then switching takes place resulting in square wave
output in astable multivibrator both states are quasi states.
Procedure:
2. Switch on the regulated power supply and observe the output in CRO.
3. Calculate the output frequency and verify it with the theoretical frequency
obtained from the design steps.
4. Draw the graph for output.
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Circuit Diagram for Monostable Multivibrator Using Op-amp:
Model Graph:
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Monostable Multivibrator:
In monostable multivibrator the diode D
1
is connected across the
capacitor(C). The diode clamps the capacitor voltage to 0.7V. When the output is at +V
sat
,
narrow negative triggering pulse V
t
is applied to non inverting terminal through diode D
2
. Let us
assume the output voltage V
O
is at +V
sat
in its stable state. The diode D
1
conducts and the
voltage across the capacitor(C) is V
C
gets clamped to 0.7V. The voltage at non inverting input
terminal is controlled by potentiometer divides of R
1
R
2
to V
O
. i.e. + V
sat
in stable state. If V
t
is a negative trigger of amplitude so that effective voltage at this terminal is less than 0.7V (+
V
sat
+ (-V
t
) then the output of the op-amp changes its state from +V
sat
to -V
sat
. The diode is now
reverse biased and the capacitor starts charging exponentially to -V
sat
through resistance R. The
time constant of charging is zero.
Procedure:
2. Using the function generator Apply the trigger input to the non inverting input
terminal of op-amp.
3. Measure the output from CRO.
4. Characteristics of Input, output versus time are drawn from the readings
observed in CRO.
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Circuit Diagram for Schmitt Trigger:
Model Graph:
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Schmitt Trigger:
In Schmitt trigger circuit, the input voltage is applied to the negative terminal
of op-amp and resistor R is chosen equal to R
1
||R
2
to compensate the input bias current. The
input V
in
trigger the output V
O
, every time it exceeds a certain voltage level and these voltage
levels are called upper threshold voltage and lower threshold voltage. The hysteresis width is
the difference between these two voltage levels.
Design:
1 1
1 1
1 1
] ]
R
2
V =V + (V - V )
sat UT ref ref
R +R
1 2
1 1
1 1
1 1
] ]
R
2
V =V - (V +V )
sat LT ref ref
R +R
1 2
V =0 V
ref
R =100K
2
R =10K
1
V =1V
sat
1 1
1 1
1 1
] ]
R
2
V =V + (V - V ) =+0.9
sat UT ref ref
R +R
1 2
1 1
1 1
1 1
] ]
R
2
V =V - (V +V ) =-0.9
sat LT ref ref
R +R
1 2
V = - V =0.9=-0.9
UT LT
Threshold Voltage:
The threshold voltages are calculated as follows for the output V
O
= +V
sat
, the input
voltage at the positive terminal is called as upper threshold voltage and given by V
UT
= V
ref
+
[{R
2
/ (R
1
+R
2
)} {+V
sat
- V
ref
}].
As long as V
i
is less than V
UT
, the output remains at +V
sat
and when V
i
is slightly greater
than V
UT
, the output switches to -V
sat
and remains at same level till V
i
>V
UT
.
For the output V
O
= -V
sat
, the input voltage at the +ve terminal is called lower threshold
voltage is given by,
V
LT
= V
ref
[{R
2
/ (R
1
+R
2
)} {+V
sat
- V
ref
}]
As long as V
i
is less than V
LT
, the output remains at -V
sat
and when V
i
is slightly greater
than V
LT
, the output switches to +V
sat
and remains at that level till V
i
>V
LT
.
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Tabular Column: Astable Multivibrator
S.NO
Capacitor
Voltage (V
C
) in
volts
Time in ms
Output Voltage
(V
O
) in volts
Time in ms
ON OFF ON OFF
Tabular Column: Monostable Multivibrator
S.NO
Input Voltage
(V
i
) in volts
Output Voltage
(V
O
) in volts
Time in ms
T
ON
Tabular Column: Schmitt Trigger
S.No
Input Voltage
(V
i
) in volts
Output Voltage
(V
O
) in volts
Threshold Voltage in Volts
V
UT
V
LT
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Result:
Thus the astable, monostable multivibrators and Schmitt trigger circuits were designed
and tested the performance using operational amplifier.
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Circuit Diagram for RC Phase Shift Oscillator:
Design:
f = 1 KHz, C = 0.01f (Std. Value), R
1
= 2.2K and R
f
= 29 R
1
= 292.2K = 63.8K
1
f =
2
R C 6
1
R =
2
f C 6
= 6.5K
> A 29= >
R
f
29
R
1
=
63.8K
2.2K
=29(Condition >
R
f
29
R
1
was satisfied)
Tabular Column:
S.No
Output Voltage
(V
O
) in Volts
Time in ms
Designed
Frequency
Observed
Frequency
Model Graph:
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EXP. NO : 06 PHASE SHIFT AND WIEN BRIDGE OSCILLATORS
USING OP-AMPS
DATE :
Aim:
To design, construct and test the performance of RC phase shift oscillator and Wien
bridge oscillator using operational amplifiers.
1 Op-amp
2 Power Supply
3 Resistor
4 Capacitor
5 Voltmeter
6 Breadboard
7 Signal Generator
Theory:
RC Phase Shift Oscillator:
1
=
29
; Condition for Oscillation= > A
1
> A
1
>
1
A > A 29
RC phase shift oscillator which uses a common emitter single stage amplifier and phase
shifting network consists of the identical RC sections. The output of the feedback network gets
loaded to the low output impedance of transistor. Hence an emitter follows input stage before
the common emitter amplifier stage can be used to avoid the problem of the low input
impedance. A phase shifting network is feedback network, so output of the amplifier is given as
an input to the feedback is given as an input to the amplifier. Practically the resistance R
f
of the
inverting amplifier is designed by, by making current through it, much larger than input bias
current of the op-amp. Let the current through R
f
is I
1
then, I
1
= 100 I
b
(max)
Without amplitude stabilization, the output of the oscillator oscillates between the levels V
sat
.
V
O
= +V
O
(sat); R
f
= - V
O
(sat) / I
1
-- [+V
O
(sat) can be assumed 1Volt < V
CC
]
Now, >
1
A
CL
29
>
R
f
29
R
1
.
Design the value of R
1
from gain requirement. To prevent loading of the amplifier
because RC networks, it is necessary that R
1
10 R.
R = R
1
/ 10; Now
1
C =
2
f R 6
gives required value of capacitor.
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Circuit Diagram for Wien Bridge Oscillator:
Design:
f = 5 KHz, R
f
= 10K, R
1
=3.3K and C = 0.01f (Std. Value)
1
f =
2
R C
1
R =
2
f C
= 3.2K (Use Std. Value 3.3K)
A 3 = >
R
f
1+ 3
R
1
= >
10K
3.3K
1+ 3A=4(Barkhausen criterion was satisfied (A3))
Tabular Column:
S.No
Output Voltage
(V
O
) in Volts
Time in ms
Designed
Frequency
Observed
Frequency
Model Graph:
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Wien Bridge Oscillator:
A basic Wien bridge is used in this stage as amplifier. The output of amplifier is applied
between terminal 1 and 3, which is input of feedback network. While amplifier input is applied
from diagonal terminals 2 and 4, which is the output from the feedback network. Thus two arms
of the bridge namely R
1
C
1
in series and R
2
C
2
in parallel are called frequency sensitive arms.
Because of components of these two arms decides the frequency of oscillation. Let us find out
the gain of the feedback network. As seen earlier input V
in
to the feedback network is between 1
and 3 while output V
f
of the feedback network is between 2 and 4. Such a feedback network
called lead-lag network. This is because at very low frequency it acts like a lead while at very
high frequency it acts like a lag. Another important advantage of Wien bridge oscillator on
varying the two capacitors simultaneously by mounting them on the common shaft, different
frequency range can be provided. To satisfy Barkhausen criterion that A 1. It is necessary
that the gain of the non inverting op-amp amplifier must be minimum 3.
> A 3
CL
>
R
f
1+ 3
R
1
>
R
f
2
R
1
The frequency of Oscillation is given by
1
f =
2
R C
Procedure:
2. Supply Voltage is set as 12V using Dual power supply.
3. Calculate output voltage and time (ms) for both RC phase shift oscillator and
Wien bridge oscillator.
4. Draw the graph between output voltage and time.
Result:
Thus the RC phase shift oscillator and Wien bridge oscillator using operational were
designed, constructed and performance was verified.
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Circuit Diagram for Astable Multivibrator Using IC 555:
Design:
R
A
= 1K, R
B
= 2.2 K and C = 0.01f
1 1.45
f = =
O T (R + 2 R )C
A B
= 26.85 KHz
R + R
A B
R + 2 R
A B
% Duty Cycle = 100 = 59.25%
Model Graph:
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EXP. NO : 07 ASTABLE AND MONOSTABLE MULTIVIBRATORS
USING NE555 TIMER
DATE :
Aim:
To design, construct and obtain the frequency response and test performance of astable
and monostable multivibrator using IC 555 timer.
1 Timer IC
2 Power Supply
3 Resistor
4 Capacitor
5 CRO
6 Breadboard
7 Signal Generator
Theory:
Astable Multivibrator:
Comparing with monostable operation timing resistor is split into two
sections R
A
and R
B
. Pin 7, discharging transistor Q
1
is connected to the junction of R
A
and R
B
.
When the power supply V
CC
is connected, the external timing capacitor C charges towards V
CC
with the time constant (R
A
+R
B
) C. During this time output (pin 3) is high as Reset R=0, S=1
and this combination makes Q = 0 which has unclamped timing capacitor C.
When the capacitor voltage equals 2/3 V
CC
, upper comparator triggers the control flip-
flop so that Q = 1. This turns make transistor Q
1
ON and capacitor C starts discharging towards
ground through R
B
and a transistor Q
1
with a time constant R
B
C and current also flowing
through R
A
. Resistor R
A
and R
B
must be large enough to limit this current and prevent damage
to discharge transistor Q
1
. From the figure, we can observe that the capacitor is periodically
charged and discharged between 2/3 V
CC
and 1/3 V
CC
respectively. The required between the
capacitor charges from 1/3 V
CC
to 2/3 V
CC
is given by (Output High)
t
C
= 0.69 (R
A
+R
B
) C = T
ON
The time during which the capacitor discharges from 2/3 V
CC
to 1/3 V
CC
is equal to
(Output Low)
t
d
=0.69 (R
B
) C = T
OFF
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Circuit Diagram for Monostable Multivibrator Using IC 555:
Design:
Pulse Width (T
P
) = 1.1 R C = 1.110010
3
10010
-6
= 11 Seconds
Model Graph:
The total period of the waveform is,
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T = t + t =0.69(R + 2 R )C
A B C d
---------- T = T
ON
+ T
OFF
The frequency of Oscillation is,
1 1.45
f = =
O T (R + 2 R )C
A B
The duty cycle is the ratio of the time t
C
during which the output is high to the total period T. It
is given by
R + R
A B
R + 2 R
A B
t
C
% Duty Cycle = 100
T
= 100
Monostable Multivibrator:
A 555 timer is connected for monostable operation and its functional
diagram. In the stand by state, FF holds transistor Q
1
ON, thus clamping the external trigger
timing capacitor C to ground. The output remains at the ground potential i.e low. As the trigger
passes through V
CC
/3, FF is set Q=0. This makes the transistor Q
1
OFF and the short circuit
across the timing capacitor C is relaxed. As Q is low, output goes high i.e equal to V
CC
. The
timing cycle now begins. Since C is unclamped, Voltage across it exponentially through R
towards V
CC
with a time constant RC. After a time period T, the capacitor voltage is slightly
greater than (2/3) V
CC
and the upper comparator resets the FF that is R
1
=0, S=0. This makes
Q=1 transistor Q
1
goes on there by discharging the capacitor C rapidly to ground potential. The
output returns to the stand by state on ground potential. It is evident from that the timing
interval is independent of supply voltage. It may also be noted that once triggered, the output
remain in HIGH state until time T.
T
P
= 1.1 R C Seconds
Procedure:
2. Switch ON the Dual power supply observe the output on CRO.
3. Calculate the output frequency from CRO and verify it with frequency calculated
theoretically.
4. Follow the above steps for both Astable and Monostable Multivibrator.
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Tabular Column: Astable Multivibrator:
S.No
Capacitor
Voltage (V
C
) in
volts
Time in ms
Output Voltage
(V
O
) in volts
Time in ms
Frequency in
Hz
T
ON
T
OFF
T
ON
T
OFF
Tabular Column: Monostable Multivibrator
S.No
Capacitor
Voltage (V
C
) in
volts
Time in sec
Output Voltage
(V
O
) in volts
Time in sec
Pin Diagram of 555 Timer:
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Result:
Thus the multivibrator circuits using 555 Timer were designed, constructed and tested
the performance using 555 timer.
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Circuit Diagram for PLL characteristics:
Tabulation:
S.NO INPUT (Vin) DEMODULATED OUTPUT (Vo) VCO OUTPUT (fo)
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EXP. NO : 08 PLL CHARACTERISTICS AND ITS USE AS A FREQUENCY
MULTIPLIER
DATE :
Aim:
To design, construct and obtain characteristics of NE / SE 565 PLL IC and perform
frequency multiplication using NE / SE 565 PLL IC.
1 PLL IC
2 Power Supply
3 Resistor
4 Capacitor
5 CRO
6 Function Generator
7 Breadboard
8 Connecting Wires
Theory:
The basic block schematic of the PLL is shown in figure. This feedback system consists of
phase detector/comparator, a low pass filter, an error amplifier and voltage controlled oscillator
(VCO).
The VCO is a free running multivibrator and operates at a set frequency f
O
called free
running frequency. This frequency is determined by an external timing capacitor and an
external resistor. It can also be shifted to either side by applying a DC control voltage V
C
to an
appropriate terminal of the IC. The frequency deviation is directly proportional to the DC control
voltage and hence it is called a Voltage Controlled Oscillator (VCO).
If an input signal V
S
of frequency f
S
is applied to the PLL, the phase detector compares
the phase and frequency of the incoming signal to that of the output V
O
of the VCO. If the two
signals differ in frequency and/or phase an error voltage V
e
is generated. The phase detector is
basically a multiplier and produces sum (f
S
+ f
O
) and difference (f
S
- f
O
) components at its
output. The high frequency component (f
S
+ f
O
) is removed by the low pass filter and the
difference frequency component is amplified and then applied as control voltage V
C
to VCO. The
signal V
C
shifts the VCO frequency in a direction to reduce the frequency difference between f
S
and f
O
. Once this action starts, we can say that the signal is in the capture range.
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Circuit Diagram for Frequency Multiplier Using NE / SE 565 PLL IC:
Tabulation:
S.NO INPUT FREQUENCY OUTPUT FREQUENCY
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The VCO continues to change frequency till its output frequency is exactly the same as
the input signal frequency. The circuit is then said to be locked. Once locked, the output
frequency f
O
of VCO is identical to f
S
except for a finite phase difference . This phase difference
generates a corrective control voltage V
C
to shift the VCO frequency from f
O
to f
S
and thereby
maintain the lock. Once locked, PLL tracks the frequency changes of the input signal. Important
definitions related to PLL are (i) Lock in range, (ii) capture range and (iii) Pull in time.
Lock in range:
The range of frequencies over which the PLL can maintain the lock with incoming signal
is called lock in range or tracking range.
Capture range:
The range of frequencies over which the PLL can acquire lock with an input signal is
called the capture range.
Pull in time:
The total time taken by the PLL to establish lock is called pull in time.
Frequency Multiplication:
The block diagram of a frequency multiplier using PLL is shown in the figure. A divide by
N network is inserted between the VCO output and the phase comparator input. In the locked
state, the VCO output frequency f
O
is given by, f
O
= N f
S
The multiplication factor can be obtained by selecting a proper scaling factor N of the
counter. Frequency multiplication can also be obtained by using PLL in its harmonic locking
mode. If the input signal is rich in harmonics e.g. square wave, pulse train etc. then VCO can be
directly locked to the n-th harmonic of the input signal without connecting any frequency divider
in between. How ever, as the amplitude of the higher order harmonics becomes less, effective
locking may not takes place for high values of n. Typically n is kept less than 10. The same
circuit can also be used for frequency division. Since the VCO output (a square wave) rich in
harmonics, it is possible to lock the m-th harmonic of the VCO output with the input signal f
S
.
The output f
O
of VCO is now given by,
f
O
= f
S
/ m
Procedure: PLL Characteristics
2. Measure the free running frequency of VCO at pin 4, with the input signal V
in
set equal to
zero. Compare it with the calculated value = 0.25 / R
T
C
T
.
3. Now apply the input signal of 1 V
PP
square wave at a 1 KHz to pin 2. Connect one
channel of the CRO to pin 2 and display the signal on the CRO.
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Pin Diagram of NE / SE 565 PLL IC:
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4. Gradually increase the input frequency till the PLL is locked to input frequency. This
frequency f
1
gives the lower end of the capture range. Go on increasing the input
frequency, till PLL tracks the input signal, say, to a frequency f
2
. This frequency f
2
gives
the upper end of the lock in range. If the input frequency is increased further, the loop
will get unlocked.
5. Now gradually decrease the input frequency till the PLL is again locked. This is the
frequency f
3
, the upper end of the capture range. Keep on decreasing the input
frequency until the loop is unlocked. This frequency f
4
gives the lower end of the lock in
range.
6. The lock in range f
L
= (f
2
- f
4
). Compare it with the calculated value of f
L
=
7.8f
0
/ 12. Also the capture range is f
C
= (f
3
- f
1
). Compare it with the calculated value
of capture change.
1
1
]
1
2 f
L
f =
C 3
2
3.610 C
Procedure: Frequency Multiplication
2. Set the input signal at 1 V
PP
square wave at 500Hz.
3. Vary the VCO frequency by adjusting the 20k potentiometer till the PLL is locked.
4. Measure the output frequency (It should be equal to 5 times the input frequency).
5. Repeat the steps 2, 3 and 4 for input frequency of 1 KHz and 1.5 KHz.
Result:
Thus the PLL characteristics and frequency multiplication using PLL NE / SE 565 PLL IC
were designed, performed and their characteristics were obtained.
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Circuit Diagram for DC Power Supply Using LM 723:
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EXP. NO : 09 DC POWER SUPPLY USING LM 723 AND LM 317
DATE :
Aim:
To design, construct the DC power supply using LM 723 and LM 317 and test its
performance using the same.
1 Regulator IC
2 Diode
3 Transformer
4 Transistor
5 Resistor
6 Capacitor
7 Voltmeter
8 Breadboard
9 Connecting wires
Theory:
LM 723 Regulators:
LM723 a positive NPN standard voltage regulator mainly designed for series regulator
applications which can be utilized for both fold back and linear current limiting due to its very
low standby current drain circuit.
Voltage Regulator an electrical or electronic device created for the purpose of
maintaining a constant voltage level of a power source within the suitable limits.
The integrated voltage regulator LM723 will supply 150 mA of output currents but any
desired load current can be provided by adding external transistors for output currents in
excess of 10A. This can be used as a linear or switching regulator since its output voltage can
be adjusted from 2 Volts to 37 Volts while the input voltage can be at 40 Volts maximum. The
range of variations of input voltage and load current can be kept at constant using this voltage
regulator.
Application:
The LM723 voltage regulators are widely used for wide range of applications such as a
temperature controller, a current regulator, or a shunt regulator. Also, DC power supplies in
electronic equipment are using voltage regulators.
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Circuit Diagram for DC Power Supply Using LM 317:
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LM 317 Regulators:
Besides fixed voltage regulators, IC voltage regulators are available which allow the
adjustment of the output voltage. The output voltage can be adjusted from 1.2V to 57V with
the help of such regulators. In such regulator ICs the common terminal plays a role of control
input and hence called as ADJUSTMENT (ADJ) terminal. The LM 317 series is the most
commonly used three terminal adjustable regulators. These devices are available in a variety of
packages which can be easily mound and handled. The power rating of such regulators is 1.5A.
The maximum input voltage of LM 317 is 40V and its output voltage varies between 1.2V to
57V.
Tabulation:
S.NO
LM 723 Power Supply LM 317 Power Supply
R in K V
O
in Volts R in K V
O
in Volts
Result:
Thus the DC power supply using LM 723 and LM 317 was designed, constructed and
tested its performance using the same.
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Block Diagram of SMPS Control Circuit SG 3524:
Pin Diagram of SMPS Control Circuit SG 3524:
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EXP. NO : 10 STUDY OF SWITCHED MODE POWER SUPPLY
DATE :
Aim:
To study about the operation of Switched Mode Power Supply (SMPS) IC
SG3524/SH3525 and its characteristics.
1 SMPS Control IC
2 Power Supply
3 Resistor
4 Capacitor
5 Breadboard
6 Connecting wires
Theory:
Description:
This monolithic integrated circuit contains all the control circuitry for a regulating power
supply inverter or switching regulator. Included in a 16-pin dual-in-line package is the voltage
reference, error amplifier, oscillator, pulse-width modulator, pulse steering flip-flop, dual
alternating output switches and current-limiting and shut-down circuitry. This device can be
used for switching regulators of either polarity, transformer-coupled DC-to-DC converters,
transformer less voltage doublers and polarity converters, as well as other power control
applications. The SG3524 is designed for commercial applications of 0C to +70C.
Features:
Complete PWM power control circuitry
Single ended or push-pull outputs
Line and load regulation of 0.2%
1% maximum temperature variation
Total supply current is less than 10mA
Operation beyond 100 kHz
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Voltage Reference
An internal series regulator provides a nominal 5V output which is used both to generate
a reference voltage and is the regulated source for all the internal timing and controlling
circuitry. This regulator may be bypassed for operation from a fixed 5V supply by connecting
Pins 15 and 16 together to the input voltage. In this configuration, the maximum input voltage
is 6.0V. This reference regulator may be used as a 5V source for other circuitry. It will provide
up to 50mA of current itself and can easily be expanded to higher currents with an external PNP
as shown in Figure 3.
Figure3. Expanded Reference Current Capability
Oscillator:
The oscillator in the SG3524 uses an external resistor (R
T
) to establish a constant
charging current into an external capacitor (C
T
). While this uses more current than a series-
connected RC, it provides a linear ramp voltage on the capacitor which is also used as a
reference for the comparator. The charging current is equal to 3.6 V / R
T
and should be kept
within the approximate range of 30mA to 2mA; i.e., 1.8k<R
T
<100k. The range of values for C
T
also has limits as the discharge time of C
T
determines the pulse-width of the oscillator output
pulse. This pulse is used (among other things) as a blanking pulse to both outputs to insure that
there is no possibility of having both outputs on simultaneously during transitions.
Figure 5. Output Stage Dead Time as a Function of the Timing Capacitor Value
This output dead time relationship is shown in Figure 5. A pulse width below
approximately 0.5ms may allow false triggering of one output by removing the blanking pulse
prior to the flip-flops reaching a stable state. If small values of CT must be used, the pulse-
width may still be expanded by adding a shunt capacitance (@100pF) to ground at the oscillator
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output. [(Note: Although the oscillator output is a convenient oscilloscope sync input, the cable
and input capacitance may increase the blanking pulse-width slightly.)] Obviously, the upper
limit to the pulse width is determined by the maximum duty cycle acceptable. Practical values of
CT fall between 0.001 and 0.1 mF. The oscillator period is approximately t=R
T
C
T
where t is in
microseconds when R
T
=W and C
T
=mF.
Figure 6. Oscillator Period as a Function of RT and CT
The use of Figure 6 will allow selection of RT and CT for a wide range of operating
frequencies. Note that for series regulator applications, the two outputs can be connected in
parallel for an effective 0-90% duty cycle and the frequency of the oscillator is the frequency of
the output. For push-pull applications, the outputs are separated and the flip-flop divides the
frequency such that each outputs duty cycle is 0-45% and the overall frequency is one-half
that of the oscillator.
External Synchronization
If it is desired to synchronize the SG3524 to an external clock, a pulse of @+3V may be
applied to the oscillator output terminal with RTCT set slightly greater than the clock period. The
same considerations of pulse-width apply. The impedance to ground at this point is
approximately 2kW. If two or more SG3524s must be synchronized together, one must be
designated as master with its RTCT set for the correct period. The slaves should each have an
RTCT set for approximately 10% longer period than the master with the added requirement that
CT(slave)=one-half CT (master). Then connecting Pin 3 on all units together will insure that the
master output pulsewhich occurs first and has a wider pulse widthwill reset the slave units.
Error Amplifier
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Figure7. Amplifiers Open-Loop Gain as a Function of Frequency and Loading on Pin 9
This circuit is a simple differential input transconductance amplifier. The output is the
compensation terminal, Pin 9, which is a high-impedance node (R
L
= 5M). The gain is
and can easily be reduced from a nominal of 10,000 by an external shunt resistance from Pin 9
to ground, as shown in Figure 7. In addition to DC gain control, the compensation terminal is
also the place for AC phase compensation. The frequency response curves of Figure 7 show the
uncompensated amplifier with a single pole at approximately 200Hz and a unity gain crossover
at 5MHz. typically, most output filter designs will introduce one or more additional poles at a
significantly lower frequency. Therefore, the best stabilizing network is a series RC combination
between Pin 9 and ground which introduces a zero to cancel one of the output filter poles. A
good starting point is 50k plus 0.001mF.
One final point on the compensation terminal is that this is also a convenient place to
insert any programming signal which is to override the error amplifier. Internal shutdown and
current limit circuits are connected here, but any other circuit which can sink 200mA can pull
this point to ground, thus shutting off both outputs. While feedback is normally applied around
the entire regulator, the error amplifier can be used with conventional operational amplifier
feedback and is stable in either the inverting or non-inverting mode. Regardless of the
connections, however, input common-mode limits must be observed or output signal inversions
may result. For conventional regulator applications, the 5V reference voltage must be divided
down as shown in Figure 8. The error amplifier may also be used in fixed duty cycle applications
by using the unity gain configuration shown in the open-loop test circuit.
Current Limiting
Figure9. Current Limiting Circuitry of the SG3524
The current limiting circuitry of the SG3524 is shown in Figure 9. By matching the base-
emitter voltages of Q1 and Q2, and assuming a negligible voltage drop across R1:
Threshold=V
BE
(Q
1
) + I
1
R
2
-V
BE
(Q
2
) =I
1
R
2
= 200mV Although this circuit provides a relatively
small threshold with a negligible temperature coefficient, there are some limitations to its use,
the most important of which is the 1V common-mode range which requires sensing in the
ground line. Another factor to consider is that the frequency compensation provided by R
1
C
1
and
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Q
1
provides a roll-off pole at approximately 300Hz. Since the gain of this circuit is relatively low,
there is a transition region as the current limit amplifier takes over pulse width control from the
error amplifier. For testing purposes, threshold is defined as the input voltage required getting
25% duty cycle with the error amplifier signaling maximum duty cycle. In addition to constant
current limiting, Pins 4 and 5 may also be used in transformer-coupled circuits to sense primary
current and to shorten an output pulse, should transformer saturation occur. Another
application is to ground Pin 5 and use Pin 4 as an additional shutdown terminal: i.e., the output
will be off with Pin 4 open and on when it is grounded. Finally, fold back current limiting can be
provided with the network of Figure 10. This circuit can reduce the short-circuit current (I
SC
) to
approximately one-third the maximum available output current (I
MAX
).
Fold back current limiting can be used to reduce power dissipation under shorted output
conditions.
Figure10. Fold back Current Limiting
Result:
Thus the operation of Switched Mode Power Supply (SMPS) control IC SG3524 and its
characteristics were studied.
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