This document provides instructions for creating a VHDL-based component in Multisim using the VHDL Module. It describes how to create a state machine model in VHDL Module, verify it in a test bench, and generate a component that can be used in Multisim schematics. The component represents a simple analog-to-digital converter (ADC) with two states, modeled as a finite state machine in VHDL.
This document provides instructions for creating a VHDL-based component in Multisim using the VHDL Module. It describes how to create a state machine model in VHDL Module, verify it in a test bench, and generate a component that can be used in Multisim schematics. The component represents a simple analog-to-digital converter (ADC) with two states, modeled as a finite state machine in VHDL.
This document provides instructions for creating a VHDL-based component in Multisim using the VHDL Module. It describes how to create a state machine model in VHDL Module, verify it in a test bench, and generate a component that can be used in Multisim schematics. The component represents a simple analog-to-digital converter (ADC) with two states, modeled as a finite state machine in VHDL.
This document provides instructions for creating a VHDL-based component in Multisim using the VHDL Module. It describes how to create a state machine model in VHDL Module, verify it in a test bench, and generate a component that can be used in Multisim schematics. The component represents a simple analog-to-digital converter (ADC) with two states, modeled as a finite state machine in VHDL.
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Document Type: Tutorial NI Supported: Yes Publish Date: Jan 9, 2007
Creating A VHDL-Based Component For Multisim Using The VHDL Module
Overview The VHDL Module can be used as a stand-alone application, or together with Multisims SPICE simulator using patented co-simulation. It is perfect for teaching HDLs, digital logic, programmable logic design or for creating simulation models for complex digital ICs not practically modeled in SPICE. Co-simulation allows you to introduce VHDL modeled components into mixed-mode circuits and to demonstrate the performance of a FPGA/CPLD in the real (SPICE modeled) circuit in which it will be used. Table of Contents 1. 2. 3. 4. 5. 6. Before you start: Create a new VHDL Module project using the State Machine Editor Use the Graphical Testbench to verify model behaviour Use Multisims Component Wizard to create a new VHDL-based component Simulate your new VHDL-based component with Multisim Additional Resources
Before you start: If you install the VHDL Module on a non English OS or in a directory other than the default directory you will need to recompile the Library files. VHDL Module library files (.LIB files) are ASCII text files where each line includes a reference to a specific design unit located in the library and a corresponding reference to a compiled VHDL source file (an .AN file). The information in the library file is used by the VHDL Module analyzer and elaborator (during the compile and link processes) to locate and use externally-referenced design units such as packages, components and lower-level entities. 1. 2. 3. 4. Delete the existing *.lib files in the folders ..\VHDL Module8\IEEE87 and ..\VHDL Module8\IEEE93 Set write access rights for the folders ..\VHDL Module8\IEEE87 and ..\VHDL Module8\IEEE93 Start VHDL Module and confirm the dialog to re-compiling the libraries After re-compiling has finished, you are ready to start
Note: Due to the file structure of the VHDL Module, you are not allowed to use blanks ( ) in folder or file names associated with a VHDL project. It is recommended to unpack the attached file "vhdl_adc.zip" to "C:\VHDL_Demo".
Create a new VHDL Module project using the State Machine Editor Start VHDL Module (from Windows or Multisim > Simulate > VHDL Simulation) Create a new project (File > New Project) and save it as c:\VHDL_Demo\ADC\ Simple ADC.acc (File > Save Project) Create a new state machine (File > New Module) an Save it as ADC_StateMachine.VSM 1. Define the entities (inputs and outputs signals) of your VHDL component 2. 1. Inputs: AI, Clk, Res 2. Output: DO 3. Define the architecture (States) of your VHDL component (left double click opens properties) 4. 1. State1: (Name: LOW) (Action: DO<='0') 2. State2: (Name: HIGH) (Action: DO<='1') 5. Define the Transitions of your VHDL component. Draw transitions with the right mouse button pressed 6. 1. Transition1: from LOW to HIGH (Condition: AI='1') 2. Transition2: from HIGH to LOW (Condition: AI='0' 7. Set properties for State Machine (FSM > Properties) 8. View the source code the State Machine has created for you (FSM > View Source)
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Save State Machine (File > Save Module) and close the State Machine Editor Create Entity and Architecture out of the State Machine by rebuilding the hierarchy (File > Rebuild Hierarchy or right mouse click on module in project view) Compile and link your project by selecting the entity in the project view and press compile and link button
The model file C:\VHDL_Demo\ADC\ADC_STATEMACHINE.VX has been created and can now be linked to a Multisim VHDL component
Use the Graphical Testbench to verify model behaviour Before you create your Multisim component, you can use VHDL Module's build in Graphical Test Bench to verify the component model behaviour. Add a Graphical test bench (File > New Module, select test bench Wizard (Graphical)) Save it as ADC_Test.WTB Step through the Wizard (set simulation time to 1 us) Set the signals for the graphical test bench 1. Use the 1 0 Button to set the signal profile for AI and Res. 2. Double click on signal Clk and set the stimulus type to Clock 3. Double click on signal DO and set the stimulus type to None
Save and close the test bench window. Create Entity and Architecture out of the Test bench by rebuilding the hierarchy (File > Rebuild Hierarchy or right mouse click on module in project view) After rebuilding the hierarchy, press Load Selected button (Simulate > Load Selected) to compile and link the test bench. Select the objects (signals and variables) to be displayed and press the CLOSE button to continue
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Click the GO button (Simulate > GO) to run the simulate. (Your State Machine Module will now be simulated for the specified simulation time with the signals set in the graphical test bench) View the simulation results. Use cursor to move along the timeline or set time measurements between cursor (left mouse click)
You can now close all windows and VHDL Module as the model file has already been generated. Save Project if asked.
Use Multisims Component Wizard to create a new VHDL-based component 1. Open Multisim and start the component wizard (Tools > Component Wizard) 2. Step through the wizard and complete the steps as shown 1. Step 1: Component Information (Select VHDL as Component Type) 2. Step 2: Footprint Information (Select Footprint Type: DIP-6 from the Master Database) 3. Step 3: Symbol Information (Select GND and VCC as hidden Ground and Power Pins, Use the build in Symbol Editor to change Symbol if necessary) 4. Step 4: Pin Parameters (Pin types determine the high and low voltage levels of your VHDL component) 5. Step 5: Symbol to Footprint pin mapping 6. Step 6: Simulation Information (Select model created by VHDL Module (ADC_Statemachine.vx)) 7. Step 7: Symbol to Model pin mapping (model nodes follow VHDL port order) 8. Step 8: Save Component ((Add Family if necessary)
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Simulate your new VHDL-based component with Multisim
Build schematic as shown to test your VHDL component (Alternative: Load VHDL ADC.ms10 and replace existing component with your newly created one).
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Additional Resources Extending The Breadth of Circuit Simulation By Using NI Multisim Co-Simulation
Downloads vhdl_adc.zip
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