APPLICATION NOTE

VIPer100 THE MOST ADVANCED MONLITHIC SOLUTION FOR OFF-LINE PRIMARY CONVERTERS
by A. Russo, A. Bailly, A. Vitanza, R. Musarra

INTRODUCTION Following the ever increasing consumer market needs for Advanced - albeit cost effective solutions for Off Line Switch Mode Power Supplies, SGS-THOMSON Microelectronics has developed the VIPerXX0 family of monolithic devices for SMPS applications. These devices were developed using the well consolidated VIPower M0 technology.

VIPer100/100A and VIPer50/50A combines on the same silicon chip a state-of-the-art PWM circuit with current mode control and a dedicated compensation path together with an optimized high voltage avalanche rugged Vertical Power MOSFET. Housed in the 5 lead TO-220 as well as in the PowerSO-10 surface mounting package, they both offer maximum flexibility to designers allowing a primary or secondary regulation loop despite using around 50% less components when compared with a discrete implementation.

Figure 1. VIPower M0 technology Cross Section

Driving c irc uitry

Enhancement and depletion NM OS

P owe r sta ge
V DM O S

p-

w e ll n - ty pe e pil a ye r

n + substrate

P owe r s ta ge output
The VIPower M0 technology uses enhancement and depletion N-MOS signal transistors for the logic section built into a p-well buried layer, and a Vertical DMOS power transistor as the output stage. The voltage capability for this technology ranges from 30V to 1,200V, while the vertical Power MOSFET output stage - the same as for the discrete counterpart - allows high power level handling. Start up of the circuit is insured by an internal high voltage current source which is switched off during normal operation. Adjustable switching frequency up to 200KHz is achieved by an external R-C network. Synchronisation to an external clock generator is also possible. Built-in overtemperature protection offers excellent safety and silicon self protection in the case of abnormal operating conditions.

AN946

1/31

APPLICATION NOTE
Burst mode operation is an additional feature of this device, offering the possibility to operate in stand-by mode without extra components and allowing the VIPerXX0 to meet the new Germanys Blue Angel Eco Norm with less than 1W total power dissipation for the system when working in that condition. TYPE BVDSS IDmin RDS(on) @ TJ = 250C 2.5 @ D = 2 3.3 @ D = 2 5 @ D = 1 6.6 @ D = 1 Set Top Box Satellite Receivers, Decoders, Video Recorders, Digital Video Disk, Laptops, Monitors, Camcorders, Television sets, Battery chargers, and Open frame power supply represent only a small selection of products that can be easily equipped with a VIPerXX0 benefitting from all the advantages of the best integrated solution available on the market. There is a greatly increased overall reliability of the system due to an approximately 50% reduction in the components used with respect to a similar discrete implementation and complete protections built into the silicon. Additional advantages of VIPerXX0 family devices, when compared to existing monolithic solutions, include: a) The useful duty cycle range extends from 0 to about 90% for VIPerXX0 versus the 3% to 70% available on the market. The main benefit for users is the possibility to operate in stand-by mode with nearly zero power output.

VIPer100/SP

600V

3A 3A 1.5A 1.5A

VIPer 100A/ASP 670V VIPer50/SP VIPer 50A/ASP 600V 670V

The VIPer100 can be efficiently used for implementing a current mode flyback configuration in the discontinuous inductor current mode, with a power capability of 100W on a European voltage range (180 to 270VAC) and 50W for a universal input voltage range (85 to 270VAC).

Figure 2. VIPer100 - chip layout and suitable packages

PW-HV

PowerSO-10

2/31

APPLICATION NOTE
b) Larger regulation loop bandwidth. VIPerXX0 provides a specific path for compensation components (COMP pin), offering a maximum of freedom for the users to adjust the regulation bandwidth with good repetitivity. c) Excellent good line regulation because of the current mode control topology. d) Better regulation point voltage because of the higher value of this voltage when compared with monolithic solutions available on the market. This allows greater precision of the output voltage especially in the case of a primary regulation. A constant RDS(ON) value versus drain current is also assured. VIPer100 Family Highlights: * ADJUSTABLE SWITCHING FREQUENCY UP TO 200 KHZ * CURRENT MODE CONTROL * SOFT START AND SHUT DOWN CONTROL * AUTOMATIC BURST MODE OPERATION IN STAND-BY CONDITION ABLE TO MEET BLUE ANGEL NORM (<1W TOTAL POWER CONSUMPTION) * INTERNALLY TRIMMED ZENER REFERENCE * UNDERVOLTAGE LOCK-OUT WITH HYSTERESIS * INTEGRATED START UP SUPPLY * AVALANCHE RUGGED * OVERTEMPERATURE PROTECTION * LOW STAND-BY CURRENT * ADJUSTABLE CURRENT LIMITATION Typical Application Circuits: Two typical application examples for secondary and primary regulation are given for figures 3 and 4. Both circuits are current mode Flyback Converters operating in the discontinuous inductor current mode. For both circuits the switching frequency was fixed to 100KHz. Main advantages of the Flyback Converters operating in the discontinuous inductor current mode are: * All outputs will track each other within +/- 510% without post-regulation. Dynamic crossregulation is also very good; * The flyback transformer used in the discontinuous mode can be much smaller because the stored inductive energy is lower with respect to the energy required in comparable continuous mode circuits; * Load current in the Power MOSFET output stage is zero during turn-on avoiding turn-on losses or turn-on snubber circuits. Conducted EMI is also reduced; * Regulation loop is easy to compensate because of the single pole (resulting in a single capacitor filter); *

Transient response is excellent.

3/31

APPLICATION NOTE
Figure 3. Off-Line Flyback SMPS with secondary regulation - Wide Voltage Input Range - 50W Power Output.
F1 C1
AC MAIN

L1

BR1 TR1 D1 C2 Rx D3 C3 R4 C10 C9 C7 C8 GND D2 L2 +Vcc

R1

R2 1

IC1 VIPer100 2
Vdd OSC DRAIN

13V
COMP SOURCE

C4 C5

5 C6 R3

R6 ISO1 R8

R7

R5

Secondary Regulation - RCD Snubber - TL431 Programmable Zener

Cx IC2

Component List:
F1 = 2A , 250VAC L1 = RN114-2/02 SCHAFFNER L2 = 1H C1 = 0.1F, 400VAC C2 = 150 F, 400V C3 = 47 F, 16 V3.9nF, 200V C4 = 4.7nF C5 = 68 nF C6 = 1 F, 10V C7 = 2,200+1,000 mF - 16V, EKR C8 = 470F - 16V, EKR C9 = 1nF - 400V Class Y C10 = 5.6nF - 200V Cx = 100nF BR1 = 400V, 1A D1 = BYT11-600 D2 = BYW81-100
4/31

D3 = 1N4448 IC1 = VIPer100 IC2 = TL431 ISO1 = 4N25 R1 = 20+ R2 = 5.6K+, 1/8W R3 = 1K+, 1/8W R4 = 10+, 1/8W R5 = 4.7K+, 1/8W R6 = 82K+, 1/8W R7 = 18K+, 1/4W R8 = 1.2K+, 1/4W Rx =2.2K+ T1 = Transformer LP = 150H NP/NS = 7.83 (See Transformer section)

APPLICATION NOTE
Figure 4. Off-Line Flyback SMPS with primary regulation, Wide Input Voltage Range, 50W Power Output
F1 C1 AC MAIN R1 C2 Rx GND D3 C3 C10 C9 R4 D1 C7 C8 L1 BR1 TR1 D2 L2 +Vcc

R2

IC1 VIPer100 2 1
Vdd OSC DRAIN

13V
COMP SOURCE

C4 C5

5
C6 R3

Primary Regulation RCD Snubber

Component List :
F1 = 2A , 250VAC L1 = RN114-2/02 SCHAFFNER L2 = 1H C1 = 0.1F, 400VAC C2 = 150 F, 400V C3 = 47 F, 16 V3.9nF, 200V C4 = 4.7nF C5 = 18 nF C6 = 560nF C7 = 2,200+1,000 F - 16V, EKR C8 = 470F - 16V, EKR C9 = 1nF - 400V Class Y C10 = 5.6nF - 200V BR1 = 400V, 1A D1 = BYT11-600 D2 = BYW81-100 D3 = 1N4448 IC1 = VIPer100 R1 = 20+ R2 = 5.6K+, 1/8W R3 = 3.9K+, 1/8W R4 = 10+, 1/8W Rx = 2.2K+ T1 = Transformer LP = 150H NP/NS = 7.83 (See Transfomer section)

5/31

APPLICATION NOTE
VIPerXXX FAMILY PINS FUNCTIONAL DESCRIPTION: Figure 5. VIPer100 - Internal Block Diagram
OSC DRAIN

ON/OFF OSCILLATOR SECURITY LATCH

VDD

PWM LATCH S R1 FF Q R2 R3

UVLO LOGIC

FF R/S S

OVERTEMP. DETECTOR 0.5V _ + + _

0.5 V ERROR _ AMPLIFIER 13 V +

+ _

14 s DELAY

300 ns BLANKING

1 V/A

CURRENT AMPLIFIER

COMP

SOURCE

* Drain pin : Integrated power MOSFET drain pin. It provides internal bias current during start-up via an integrated high voltage current source which is switched off during normal operation.The device is able to handle an unclamped current during its normal operation, assuring self protection against voltage surges, PCB stray inductance, and allowing a snubberless operation for low output power. * Source pin : Power MOSFET source pin. Primary side circuit common ground connection. * VDD pin : This pin provides two functions : It corresponds to the low voltage supply of the control part of the circuit. If VDD goes below 8V, the start-up current source is activated and the output power MOSFET is switched off until the Vdd voltage reaches 11V. During this phase, the internal current consumption is reduced, the VDD pin is sourcing a current of about 1mA and the COMP pin is shorted to ground. After that, the current source is shut down, and the device tries to start up by switching again.
6/31

This pin is also connected to the error amplifier, in order to allow primary as well as secondary regulation configurations. In case of primary regulation, an internal 13V trimmed reference voltage is used to maintain VDD at 13V. For secondary regulation, a voltage between 8.5V and 12.5V will be put on VDD pin by transformer design, in order to stick the output of the transconductance amplifier to the high state. The COMP pin behaves as a constant current source, and can easily be connected to the output of an optocoupler. Note that any overvoltage due to regulation loop failure is still detected by the error amplifier through the Vdd voltage, which cannot surpass 13V. The output voltage will be somewhat higher than the nominal one, but still under control. * Comp pin : This pin provides two functions : It is the output of the error transconductance amplifier, and allows for the connection of a compensation network to provide the desired transfer function of the regulation loop. Its' bandwidth can be easily adjusted to the needed value with the usual components value.

FC00230

4.5 V

APPLICATION NOTE
As stated above, secondary regulation configurations are also implemented through the COMP pin. When the COMP voltage goes below 0.5V, the shut-down of the circuit occurs, with a zero duty cycle for the power MOSFET. This feature can be used to switch off the converter, and is automatically activated by the regulation loop (whatever the configuration) to provide a burst mode operation in case of negligible output power or open load condition. * Osc pin : An RT -CT network must be connected on that pin to define the switching frequency. Note that despite the connection of RT to V DD, no significant frequency change occurs for VDD varying from 8V to 15V. It provides also a synchronisation capability, when connected to an external frequency source.

For RT > 1.2 K+ the switching frequency can be calculated as: 2.3 Fsw = R C DMAX T T

DMAX = 1 -

550 RT - 150

where the recommended oscillator Duty Cycle at FSW = 100KHz is: DMAX > 80%.

Figure 6. Switching frequency versus RT for different values of CT

Oscillator frequency vs Rt and Ct

1,000
Ct = 1.5 nF

FC00030

500
Ct = 2.7 nF

Frequency (kHz)

300 200
Ct = 4.7 nF

Ct = 10 nF

100

50 30

10

20

30

50

Rt (k)
7/31

APPLICATION NOTE
Figure 7. Maximum Duty Cycle Versus RT

Maximum duty cycle vs Rt

1

FC00040

0.9

0.8

Dmax

0.7

0.6

0.5

10

20

30

50

Rt (k)
Operational Description: Current mode topology : The current mode control method, like the one integrated in the VIPer100/100A uses two control loops - an inner current control loop and an outer loop for voltage control. When the Power MOSFET output transistor is on, the inductor current (primary side of the transformer) is monitored with the SenseFET technique and converted into a voltage Vs proportional to this current. When Vs reaches VCOMP (the amplified output voltage error) the power switch is switched off. Thus, the outer voltage control loop defines the level at which the inner loop regulates peak current through the power switch and the primary winding of the transformer. Excellent open loop D.C. and dynamic line regulation is ensured due to the inherent input voltage feedforward characteristic of the current mode control. This results in an improved line regulation, instantaneous correction to line changes and better stability for the voltage regulation loop. Current mode topology also ensures good limitation in the case of short circuit. During a first phase the output current increases slowly following the dynamic of the regulation loop. Then it reaches the maximum limitation current internally set and finally stops because the power supply on VDD is no longer correct.
8/31

For specific applications the maximum peak current internally set can be overridden by externally limiting the voltage excursion on the COMP pin. An integrated blanking filter inhibits the PWM comparator output for a short time after the integrated Power MOSFET is switched on. This function prevents anomalous or premature termination of the switching pulse in the case of current spikes caused by primary side capacitance or secondary side rectifier reverse recovery time. Stand-by Mode : Stand-by operation in nearly open load condition automatically leads to a burst mode operation allowing voltage regulation on the secondary side. The transition from normal operation to burst mode operation happens for a power Pstby given by :
2 PSTBY = LP ISTBY FSW

where : LP is the primary inductance of the transformer.

FSW

is the nominal switching frequency.

APPLICATION NOTE

is the minimum controllable current, corresponding to the minimum on time that the device is able to provide in normal operation. This current can be computed as : L P tb + td is the sum of the blanking time and of the propagation time of the internal current sense and comparator, and represents roughly the minimum on time of the device. Note that PSTBY may be affected by the efficiency of the converter at low load, and must include the power drawn on the primary auxiliary voltage. As soon as the power goes below this limit, the auxiliary secondary voltage starts to increase above the 13V regulation level forcing the output voltage of the transconductance amplifier to low state (VCOMP < VCOMPth). This situation leads to the shutdown mode where the power switch is maintained in the off state, resulting in missing cycles and zero duty cycle. As soon as VDD gets back to the regulation level and the V COMPth threshold is reached, the device operates again. The above cycle repeats indefinitely, providing a burst mode of which the effective duty cycle is much lower than the minimum one when in normal operation. The equivalent switching frequency is also lower than the normal one, leading to a reduced consumption on the input main lines.

ISTBY

ISTBY =

(tb + td) X V

IN

This mode of operation allows the VIPerXX0 devices to meet the new German Blue Angel Norm with less than 1W total power consumption for the system when working in stand-by mode. The output voltage remains regulated around the normal level, with a low frequency ripple corresponding to the burst mode. The amplitude of this ripple is very low (< 10mV RMS), because of the output capacitors and of the low output current drawn in such conditions. The normal operation resumes automatically when the power get back to higher levels than Pstby. High Voltage start-up Current Source : An integrated high voltage current source provides a bias current from the DRAIN pin during the start-up phase. This current is partially absorbed by internal control circuits which are placed into a standby mode with reduced consumption and also provided to the external capacitor connected to the VDD pin. As soon as the voltage on this pin reaches the high voltage threshold VDDon of the UVLO logic, the device turns into active mode and starts switching. The start up current generator is switched off, and the converter should normally provide the needed current on the VDD pin through the auxiliary winding of the transformer, as shown in figure 8.

Figure 8. Behaviour of the high voltage current source at start-up

P start up~ 0.6 W for 230 V m ains

MAX

VDD VDDo n VDDo ff

2 mA 13 m A

VDD
1 mA 13 mA

3 mA

DRAIN

Ref. t Aux iliary p rim ary winding UNDERVOLTAG E LOCK OUT LOG IC

VIPer100

SOU RCE

Start up duty cycle ~ 12%

9/31

APPLICATION NOTE
In case of an abnormal condition where the auxiliary winding is unable to provide the low voltage supply current to the VDD pin (i.e. short circuit on the output of the converter), the external capacitor discharges itself down to the low threshold voltage VDDoff of the UVLO logic, and the device goes back to the inactive state where the internal circuits are in standby mode and the start up current source is activated. The converter enters an endless start up cycle, with a start-up duty cycle defined by the ratio of charging current towards discharging when the VIPerXX0 device tries to start. This ratio is fixed by design from 2 to 15, which gives a 12% start up duty cycle while the power dissipation at start up is approximately 0.6W, for a 230Vrms input voltage. This low value of start-up duty cycle prevents the stress of the output rectifiers and of the transformer when in short circuit. The external capacitor CVDD on the VDD pin must be sized according to the time needed by the converter to start up, when the device starts switching. This time tss depends on many parameters, among them which transformer design, output capacitors, soft start feature and compensation network implemented on the COMP pin. The following formula can be used for defining the minimum capacitor needed : IDD tss where: CVDD > V DDhys IDD is the consumption current on the VDD pin when switching. Refer to specified IDD1 and IDD2 values. Figure 9. Mixed Soft Start and Compensation
U1 D3
DRAIN

tSS is the start up time of the converter when the device begins to switch. Worst case is generally at full load. V DDhys is the voltage hysteresis of the UVLO logic. Refer to the minimum specified value. Soft start feature can be implemented on the COMP pin through a simple capacitor which will be also used as the compensation network. In this case, the regulation loop bandwidth is rather low, because of the large value of this capacitor. In case a large regulation loop bandwidth is mandatory, the schematics of figure 9 can be used. It mixes a high performance compensation network together with a separate high value soft start capacitor. Both soft start time and regulation loop bandwidth can be adjusted separately. If the device is intentionally shut down by putting the COMP pin to ground, the device is also performing start-up cycles, and the VDD voltage is
oscillating between VDDon and VDDoff. This voltage can be used for supplying external functions, provided that their consumption doesnt exceed 0.5mA. Figure 10 shows a typical application of this function, with a latched shut down. Once the Shutdown signal has been activated, the device remains in the off state until the input voltage is removed.

Figure 10. Latched Shut Down

VIPER100 VIPer100
VDD

U1 R1 R3
VDD

OSC 13V

VIPer100 VIPER100
DRAIN OSC 13V

+
COMP SOURCE

Q2 D1 R3 R2

+
COMP SOURCE

R1 R2 + C3 C1 + C2
Shutdown

R4 Q1 D1

AUXILIARY W INDING

10/31

APPLICATION NOTE
Transconductance Error Amplifier The VIPer100/100A includes a transconductance error amplifier. Transconductance Gm is the change in output current (ICOMP ) versus change in input voltage (VDD). Thus: bICOMP

GM =

Gm is well defined by specification, but ZCOMP and therefore AVOL are subject to large tolerances. An impedance Z can be connected between the COMP pin and ground in order to define more accurately the transfer function F of the error amplifier, according to the following equation, very similar to the one above :

bV DD

The output impedance ZCOMP at the output of this amplifier (COMP pin) can be defined as : bV COMP bVCOMP 1 ZCOMP = bI = G x bV DD m COMP This last equation shows that the open loop gain AVOL can be related to Gm and ZCOMP :

F(s) = Gm X Z(s)
The error amplifier frequency / phase response is reported in figures 11 and 12 for different values of a simple resistance connected on the COMP pin. The unloaded transconductance error amplifier shows an internal ZCOMP of about 330 K+.

AVOL = Gm X ZCOMP
where the Gm value for VIPer100TM is typically 1.5 mA/V.

Figure 11. Error Amplifier Frequency Response

FC00200

60
RCOMP = +

Voltage Gain (dB)

40

RCOMP = 270k RCOMP = 82k RCOMP = 27k

20

RCOMP = 12k

(20) 0.001

0.01

0.1 1 10 Frequency (kHz)

100

1,000

11/31

APPLICATION NOTE
Figure 12. Error amplifier Phase response
F C0 021 0

20 0
R C O M P = +

15 0 P h as e () 10 0 50 0 (50 ) 0.0 0 1

R C O M P = 270k R C O M P = 82k R C O M P = 27k R C O M P = 12k

0.01

0.1 1 10 Fre qu en cy (k H z)

10 0

1,00 0

12/31

APPLICATION NOTE
More complex impedance can be connected on the COMP pin to achieve different compensation laws. A capacitor will provide an integrator function, thus eliminating the DC static error, and a resistance in series leads to a flat gain at higher frequency, insuring a correct phase margin. This configuration is illustrated in figure 13. It is interesting to implement a slope compensation when working in continuous mode with a duty cycle higher than 50%. Figure 14 shows such a configuration. Note that R1 and C2 build the classical compensation network, and Q1 is injecting the slope compensation with the correct polarity from the oscillator sawtooth. External Clock Synchronization: The OSC pin provides a synchronisation capability, when connected to an external frequency source. Figure 15 shows one possible schematic to be adapted depending the specific needs. If the proposed schematic is used, the pulse duration must be kept at a low value (500ns is sufficient) for minimizing consumption. The optocoupler must be able to provide 20mA through the optotransistor. Figure 15. External clock synchronization
R1

Figure 13. Typical compensation network.

U1 VIPER100 VIPer100
VDD OSC 13V DRAIN

+
COMP SOURCE

U1
C1

VIPER100 VIPer100
VDD OSC DRAIN

13V

+
COMP SOURCE

10 k

Figure 14. Slope compensation Primary Peak Current limitation: The primary IDPEAK current and, as resulting effect, the output power can be limited using the simple circuit shown in figure 16. The circuit based on Q1, R1 and R2 clamps the voltage on the COMP pin in order to limit the primary peak current of the device to a value:

R2

R1
VDD OSC 13V

U1

VIPer100 VIPER100
DRAIN

+
COMP SOURCE

IDpeak =
where:

(VCOMP-0.5) HID
R1 + R2 R2

C2

Q1

VCOMP = 0.6 X

C1

R3

The suggested value for R1+R2 is in the range of 220Kohm.

13/31

APPLICATION NOTE
Figure 16. Output Power limitation
U1 VIPer100 VIPER100
VDD DRAIN

Over-temperature protection: Over-temperature protection is based on chip temperature sensing. The minimum junction temperature at which over-temperature cut-out occurs is 140 C while the typical value is 160 C. The device is automatically restarted when the junction temperature decreases to the restart temperature threshold that is typically 22 C below the shutdown value (see figure 17).

OSC 13V

+
COMP SOURCE

R1 Q1 R2

Figure 17. Sequence of operation in the case of thermal shutdown.

14/31

APPLICATION NOTE
Design Guidelines: With reference to the two schematics shown in figures 3 and 4, the basic design guidelines are given hereafter. This procedure can be easily adapted to modify the circuit according specific needs. The same procedures were applied for a Windows based design software. Topology: Capacitor voltage ripple at full load =Vripple = VPEAK - VMIN =120-70=50V Since C2 must provide all energy requirement of the power supply during its discharge phase, the required energy for each charging phase (2 times for each line cycle) is: 50 Power_out WIN = Efficiency TD = 0.75 TD where TD is the discharging time of C2 at each half line cycle. It can be computed as V MIN arcsin VPEAK T = 5ms 1 +
D

Flyback Converter operating in the discontinuous inductor current mode.

In the discontinuous inductor current mode all the energy stored in the primary inductance of the flyback transformer must be zero at the end of each switching cycle. During the on time, all the energy taken from the input is stored in the transformer according the equation E=1/2LIP2. When the output Power MOSFET is switched off , the stored energy is for a major part delivered to the load and for a part is dissipated on the primary side because of the undesiderable leakage inductance. The power output to the load is equal to the energy stored in the inductance times the frequency and the efficiency: POUT=2*1/2LIp2*fSW. 2 To assure discontinous operation and core reset, the Volt*second product across the primary of the transformer during reset must be equal or exceeding the Volt*second applied during the on time of the Power MOSFET output stage:

= 7ms

90
2

and the capacitor value can be calculated from:

WIN = C2 V2 - VMIN = 465mJ PEAK

Therefore :

C2 =

2 WIN V2 PEAK

V2 MIN

= 1202 702

0.931

= 98F
In the application a standard value of 150F, 400V is suggested which allows a good design margin and takes into account that the worst case condition for a standard electrolitic capacitor is CMIN=(CNOMINAL .-20%) leading to a worst case value for C2MIN of 120F. According to this definitive value for C2MIN, the new discharging time of C2 can be computed as the solution of the equation :
2 VPEAK

VFL treset 8 VIN(min) ton

Input Section: A standard input line filter, to reduce EMC down the maximum allowable value, is obtained with C1 and L1, and also with the common mode capacitor C9. AC line voltage is rectified and filtered by the full bridge BR1 and C2 in order to create a highvoltage DC ranging - in the case of a wide input voltage range - from 120 to 380VDC. The value of C2 is determined by fixing the minimum input voltage for the converter circuit at full load, fixed to V MIN=70V for this example. The worst case condition is fixed by the minimum line voltage of 85VAC, 50Hz. In this situation we have: RMS line voltage = IRMS = 85VAC Peak no-load voltage on filter capacitor = VPEAK = 120V

2 Power_out TD 2C2MIN

= VPEAK sin( F TD

; ) 2

successive approximation with a dichotomic method. With the above values, TD is about 7.3ms. VMIN can now be computed

; )= 2 ; = 120 sin(2 ; 50 0.0073 - ) = 2 = 79.6V VMIN = VPEAK sin( F TD

15/31

APPLICATION NOTE
Transformer The aim of this paragraph is to calculate the primary inductance of the transformer and to fix all boundary design constraints including the core choice, turns calculation and windings AWG datas. The maximum allowable duty cycle is defined by the breakdown capability of the output Power MOSFET (BV DSS=600V min). At turn off the voltage across the power switch is V DS = VDCmax + Flyback voltage + Leakage inductance spike. Since VDCmax is 380V, we can fix by design: VFL = Flyback voltage = 100V Vpp = Leakage inductance spike = 600 - 380 - 100 = 120V No margins are needed with respect to the breakdown voltage because of the avalanche capability of the device. Under the above condition and for a minimum DC input voltage of 79.6V we can calculate the maximum duty cycle to stay in discontinuous mode operation,

The leakage inductance, Lpl , can be assumed with good approximation equal to 5% of L p having : Lpl = 0.05 Lp = 7.3H A possible core selection for a similar transformer is the very common ETD29 core with a ferrite grade 3C85 that is able to work at FSW = 100KHz with acceptable core losses. From the ETD29 datasheets we have: * Effective Area * Suggested Flux density limit core losses); * Average lenght of turn Ae = 76mm2; Bmax = 0.125T (to LAVG = 53mm.

The primary turns NP can be calculated as:

NP =

LP Ipk BMAX Ae 10-6

147 10-6 3.0 = 0.125 76 10-6

47

DMAX = =

VFL (VMIN - VTR) + VFL

The power secondary turns N spower can be calculated as:

NSPOWER = =
100

NP (Vout + Vdiode) V FL

100 = 55.7% 79.6 + 100

47 (12 + 0.7)

=6

Where VTR is the voltage drop on the MOSFET power stage at Ipk. For this example VTR = 0V. The peak current on the primary inductance at full load (P0=50W) and for a given ( 2 = 0.75 ) is:

and for primary regulation,

NPaux =

NP (13 + Vdiode) V FL NP (11 + Vdiode) V FL

47 13.7 100

= 6.44

Ipk =

2P0 2 (VMIN DMAX)

while for secondary regulation,

= NSaux =

100 = = 3.0A 0.75 79.6 0.557

The primary inductance can then be calculated as:

47 11.7 100

= 5.50

The air gap can be calculated as,

LP =

VMIN DMAX

Ipk FSW = 0.147mH

79.6 0.557 = 3.0 100000

AG =

4 & NP Ipk BMAX 104

3.0 = 4 & 47104 = 1.42mm 0.125

16/31

APPLICATION NOTE
At this point it is possible to choice the copper section for primary and secondary windings. Under the condition to accept 1W copper lossess in the worst case condition we can easily calculate the theoretical copper section. Our simplified choice is to split the losses between the primary and the secondary windings (0.5+0.5W) and to use several wires of little section paralleled together. . This in order to minimize the skin effect or penetration depth (0.024cm @ 100KHz) otherwise resulting in un-acceptable AC resistance. Taking as example the primary winding and considering 0.5W total copper losses we can calculate the resulting allowable resistance: 7.3 10-6 32 = 0.00477F 5.6nF 1202 The resistor Rx is calculated under the hypothesis to discharge C10 during a period leaving a residual voltage of Vfl at the time of the next turn-off.

C10 =

Rx =

T C10 ln 1+ VPP V FL

10 10

-6

5.6 10-9 ln 1 + 120 100

=2289+ = 2.2k +

RP = =

PP I2RMS

PP Ipk

(D MAX/3)

The power dissipated in Rx is the energy discharged from C10 times the switching frequency, here fixed by design to 100KHz :

0.5 3.0 (0.556/3)

= 0.3044+

Pd = C10 (VFL + VPP)2 - V2 = 10.53W

FL

f=

and considering that we have 47 turns with an average length of 53mm,

RP/cm = 47 P = 0.00122+/cm 5.3

, this resistance value can be achieved using 4 paralled AWG29 wires. Withe the same procedure we can calculate for the power secondary winding that are needed 7 paralleled AWG24 wires. Snubbing Circuit: The network D1, Rx, C10 limits the voltage spike at turn-off caused by the leakage inductance Lpl of the power transformer T1. The energy stored in the leakage inductance, is transferred to the capacitor C10 which is dimensioned according the following equation (taking into consideration that capacitor has a residual voltage egual to V fl at turn off). 2 Lpl Ipk (max)

This value is rather pessimistic because part of the leakage energy is absorbed by local parasitic capacitance, and an another part is restituted back to the secondary side because of the recovery time of the diode D1. The computed values here above gives a first guess of what could be the sizing of the snubber. Practical measurements will provide the final components choice. Another topology can be used for clamping the voltage on the drain of the device, with transil. Suited types (1.5KExxx or BZW80/xxx) are available from ST, and offers good operation in every condition (input voltage and/or output power variations). Particular care should be taken to the design of the snubber circuit, when low mains power is required in converter stand by mode. In this case, the transil device is definitively the better one.

C10 =

where:

2 Vpp

Lpl= Leakage inductance = 7.3 H ; Vpp = Allowable Voltage spike due to leakage inductance = 120V for this example

17/31

APPLICATION NOTE
Output Filter: The network C7+C7', L2, C8 in figure 4, provides filtering of the output voltage to meet the output ripple specification. To calculate the capacitors values it is necessary to consider that these components are not ideal. Each capacitor has resistance R0 and inductance L 0 in series. These are referred to as the equivalent series resistance (ESR) and equivalent series inductance or (ESL). Up to 200KHz operation L0 can be neglected for the output ripple determination. This means that we have two ripple components due to R0 and C0 not in phase. For a worst case comparison, however, it can be assumed that they are in phase. From the practical point of view it is possible to demonstrate that to calculate the capacitor value it is enough to calculate the ESR value for having a certain output ripple and choose in the capacitor catalogue that value of capacitor that shows the needed ESR at the switching frequency. More commonly, it is possible to find in the catalogues the value R0*C0 [+*F]. If we need to have a voltage ripple, V 07pp, of 0.50V across C7 we can calculate: In order to further reduce the output ripple it is possible to add an additional L-C filter. In our example we need a ripple value across C8 (and the load) of V08pp=0.10V. For 100KHz operation a practical value of 1mH can be used for the series inductance. At 100KHz operation 1mH inductance leads to a resistance of RL2=0.63+. Once again we can consider that the main source for the ripple on C8 is the ESR of the capacitor. If we consider the equivalent circuit showing only the resistive components of L2 and C8 at 100KHz, we can calculate ESRC8:

ESRC8 = R08 = V = 0.16 +

Therefore:

V08pp RL2 - V08pp 07pp

0.1 0.63 0.5 - 0.1

C08 =

65 0.16

= 414F

The value used in the application is C8 =470F. The same results apply also to figure 3 where: C7 = 2,200F, C7' = 1,000F, L2 = 1H, C8 = 470F. Closing the Feedback loop: The objective of this paragraph is to give guidelines to design a closed-loop negative feedback system around the VIPer100. As shown in the next figure, the closed loop feedback system can be described in terms of 3 major elements: G1: PWM, Integrated Power MOSFET and Transformer; G2(s): Error amplifier and Compensation Network; He(s): Output filter. The gain loop parameters (gain and phase shift) can be represented using Bode plots. Since G1 and He(s) are predetermined by the application and the circuit topology, the task in closing the feedback loop is to define the characteristics of the error amplifier (if external) and related compensation network, G2(s), that results in the optimum closed loop gain-bandwidth for good dynamic response, line and load regulation and stability.

ESRC7 = R07 =
Where: 2 Iout (1 - Dmax)

V07pp ISpk

ISpk =

2 4.16 (1 - 0.557)

= 18.80A

Therefore: 0.50 18.80 = 0.027+ Considering that an average quality capacitor suitable for 100KHz operation shows a value R0*C0 = 65 [+*F] , we can calculate : 65 C07 = C7 = 0.019 = 2,445F

ESRC7 = R07 =

For the real application are used two capacitor in parallel (C7 and C7') respectively of 2,200F and 1,000F, 16V.

18/31

APPLICATION NOTE
Figure 18. Control loop block diagram

PWM - Power Switch Transformer

Output Filter He(s) V0

Vin

G1

G2(s)
Compensated Error Amplifier
A common approach to design the desired closed loop characteristic is the following: 1) Represent the Bode plot of the transfer function G1*He(s); 2) Define the optimum transfer characteristic to achieve good dynamic response, line and load regulation and stability; 3) Design the compensation network G2(s) in such a way that the sum of the gain of G2(s) and G1*He(s), matches the transfer characteristic defined at point 2.The phase margin must be verified as well. At this point we need to know how to calculate the tranfer functions G1*He(s). We can make the following considerations: 2 V0 (2), Ipk = K VCOMP (1), P = R 0 0
2 P0 = LP Ipk f 2

Vref

And combining (1), (2) and (3) LP I 2 R0 f 2 PK 2 LP R0 f 2 2

V0 = = IPK

2 Thus, considering also the power transformer turns ratio n=Np/Ns, and that the values of primary inductance, filter capacitance and load resistance must be referred into the output we are monitoring according their respective turns ratios squared, V L R f 2 P 0 G1 = V D = K n = 2 COMP

= K VCOMP

LP R 0 f 2

(3)

1 HID

LP R0 f 2 2 1 + (s/F z)) 1 + (s/F p))

(4)

And, where K=1/HID

He(s) = Z=

, P = &RC (5),
0 0

1 2 & (ESR) C 0

(6)

19/31

APPLICATION NOTE
where (ESR*C0) in formula (6) is the (R0*C0) in [+*F] related to the used capacitors (for our example 65*106 [+*F] ) To underline that, as reported in formula (5), the effective power cell pole of a discontinuous flyback is the double of the one of the load itself, when this load is constituted of a filtering capacitor and the load resistor. The theoretical explanation and some experimental measurements are reported in Appendix A. Primary Regulation: In the case of the application in fig. 2 (primary regulation), we have: K=1 (see VIPer100 datasheet); n = Np/Ns = 47/7 =6.7; C0' = 47 + 3670*(6/7)2 = 2743F; R0' = (13)2 / 50 = 3.38+ (min) ; R0 = (13)2 / 5 = 33.8+ (max); Therefore, 2450 3

fCO = = 14.82dB

= 817Hz

G2(s)817Hz = [(log817 - log34) 20 -13] =

At this point, since we know gm = 1.5 mA/V, we can fix R3

R3 gm = 14.82dB resulting in: R3 3.9K +

According the point 1), the pole of G2(s) is fixed by C6' 1 C5 = 2 & 3.9 103 2450 18nF (rounded to a commercial value) According the point 3), the zero of G2(s) is fixed by C6

C6 = 2 & 3.9 103 80 = 500nF 560nF

An additional pole is added at very low frequency by C5 in parallel to C6 and the internal resistance of the COMP pin that is equal to 330K+. 1 p= = 0.83Hz 2 & 330 103 578 10-9 The phase margin for the overall transfer function at fC0 can be calculated as:

G1 = 1

147 3.38 0.1 0.75 2

= 4 13dB

at max load The pole frequency of the output filter capacitance and load resistance is:
1 1 p = & R C =3.14 3.38 0.002743= 34Hz
0

The zero frequency of the output filter capacitance and associated ESR is:

M(@) = 817 = 3600 - 1800 -tg-1( 0.83 ) - tg-1(817 ) + 34 + tg-1(

817 80

) = 86.80

Z = 2 & ESR C=

1 6.28 65 10-6

=2,450Hz

The same procedure can be repeated at min load (for this example 5W that leads to a R0=33.8+ The gain Bode diagrams at max load and min load are represented in figures 19 and 20, while the phase Bode diagram for both cases is represented in figure 21.

The second step is to design the feedback transfer function G2(s) and to choose the values for the network R3 - C5 -C6 The following procedure can be applied: 1)To fix a pole of G2(s) at the zero of G1*He(s); 2)To cross 0dB for the overall transfer function at 1/3 of the frequency where is located the zero of G1*He(s). The crossing frequency is named fC0; 3)To fix a zero of G2(s) at 1/10 of f C0; Therefore,

20/31

APPLICATION NOTE
Figure 19. Gain Bode Plot at Max Load

Gain Bode Plot - Max Load

80 Control to Output 60 Feedback 40

Gain (dB)

Overall 20 0 -20 -40 -60

10

100

1,000

10,000

100,000

Frequency (Hz)
Figure 20. Gain Bode Plot at Min Load

Gain Bode Plot - Min Load

100 Control to Output 80 60 Feedback Overall

Gain (dB)

40 20 0 -20 -40 -60 1 10 100 1,000 10,000 100,000

Frequency (Hz)

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APPLICATION NOTE
Figure 21. Phase Bode Plot

Phase Margin Bode Plot

140 Overall @ Max Load 120 Overall @ Min Load

Phase (Deg)

100 80 60 40 20

10

100

1000

10000

100000

Frequency (Hz)

22/31

APPLICATION NOTE
Secondary Regulation: In the case of the application in fig. 1 (secondary regulation), we have: K=1 (see VIPer100 datasheet); n = Np/Ns = 47/6 =7.83; C0' = 3670 +47*(5/6)2 = 3,702 F; R0' = (12)2 / 50 = 2.88+ (min) ; 28.8+ (max); Therefore, R0 = (12)2 / 5 = Compensation network Built around R3, C5 and C6. Basically, it is possible to eliminate C5 and C6, but : *C5 is needed because of noise filtering. It will be also used for setting a pole at the same place than the zero of the power cell, due to the ESR of the filtering output capacitor. *In the general case, C6 will be used to build a soft start, because it is not really needed to provide the zero of the regulation loop. Its value will be in the range of a few mF, according to the following formula : I t

G1(s) = 1

147 2.88 0.1 0.75 2

= 3.98 12dB at max load

C6 =

COMPHI

SS

NOM VCOMP - VCOMPth

where :

Figure 22. Secondary feedback and compensation network

VDD

D R A IN

OSC

U1 V IPer1 0 0

13 V

+
CO M P SO URC E

C6

R3

R7 IS O 1

R8

C7 C8 U2 T L 43 1

R4

Vo u t

R5

The pole frequency of the output filter capacitance and load resistance is: 1 1 p = & R C = 3.14 2.88 0.003702 0

ICOMPHI and VCOMPth are given in the VIPer100 or VIPer50 datasheeets (They do not depend on the type of VIPer). tSS is the desired soft start time (Input parameter).
NOM VCOMP is the nominal voltage on the compensation pin when in steady state. It can be computed from the other parameters of the software with the following formula : NOM VCOMP

30Hz

The zero frequency of the output filter capacitance and associated ESR is: 1 1 Z = 2 & ESR C = =2,450Hz 6.28 65 10-6 The second step is to design the feedback transfer function G2(s) and to choose the value of all involved parts. For a better understanding of the applied procedure some basic considerations should be considered with reference to figure 22.

= HID IP + VCOMPoff

where : HID and VCOMPoff are given in the VIPer100 or VIPer50 datasheeets (They do not depend on the type of VIPer).
23/31

APPLICATION NOTE
tSS is the desired soft start time (Input parameter).
NOM VCOMP is

where : ICOMPHI is given in the VIPer100 or VIPer50 datasheeets (It doesnt depend on the type of VIPer).
ISO1 VFB and GISO1 are respectively the forward voltage of the diode and the current gain of the optocoupler ISO1. IU2 is the needed biasing current of the TL431. It B is about 1mA for classical devices. R6 will be computed for loop stability purpose.

the nominal voltage on the compensation pin when in steady state. It can be computed from the other parameters of the software with the following formula :
NOM VCOMP=

HID IP + VCOMPoff

where:

HID and VCOMPoff are given in the VIPer100 or VIPer50 datasheeets ( HID depends on the type of VIPer). IP is the peak primary current in steady state. As we have : VCOMPoff VCOMPth it comes :

TL431 and optocoupler transfer function The optocoupler diode current Id can be written as follows :

C6 =

ICOMPHI tSS HID IP

Id =

R3 will always have the same value, we suggest 1k+. This value avoids that at start up, the soft start function is hidden by too high an immediate voltage on the compensation pin (I COMPHI R3) and provides correct large signal dynamic behaviour in case of large output current changes. According to this value, C6 will always have a minimum value of 1F, in order to avoid any interference with the higher frequency poles and zeros of the overall regulation loop. This will be the value by default, if no soft start is needed, or if the desired soft start time leads to a lower value. For our example, considering tss= 5msec, we have 600 10-6 5 10-3 C6 = = 1F 13 that is also the minimum allowed value for this specific suggested compensation network. TL431 biasing R8 provides a supplementary biasing current for the TL431. This biasing current is the sum of the one delivered by R8 and the one needed by the diode of the optocoupler. A good characteristic of the VIPer family is that this current is fixed (When in steady state) and doesnt depend on the output load. Therefore, a simple formula can be used to compute the value of this resistance, with sufficient margin for the large signal dynamic behaviour : ICOMPHI VISO1 + R6 FB GISO1 R8 = U2 IB

Vout - F(s) Vout 1- F(s) = R R6 6

Vout

where F(s) is the transfer function of the TL431 and associated components. 1 We have : F(s) = - R C s and therefore :
7 X

Id = R
6

1 + R7 CX s R 7 CX s

Vout

Note that R5 never impacts on the small signal transfer function. It only sets the DC value of the output voltage. Its value can be fixed at 4.7k+ and the one of R7 is defined accordingly : R7 = R5 Vout -1 where: Vref

Vout is the desired output voltage. Vref is the reference voltage of the used programmable zener. Either 2.5V (The most conventional) or 1.25V (For micropower models). For our example, considering a standard TL431 and Vout=12V, we have: R7 = 4.7 12 -1 18K + 2.5

24/31

APPLICATION NOTE
The overall transfer function of the TL431 and the optocoupler can be expressed as follows :

G2(s) =

V COMP Vout

V COMP Id

Id
out

= -G

ISO1

1 + R3 C6 s (C5 + C6) s 1 + R3

C5 C6 C5 + C6

1 R6

1+R7CXs R7CXs

Taking into account that C5 is much smaller than C6 :

G2(s) = -GISO1

1 + R3 C6 s C6 s (1 + R 3 C6 s)

1 R6

1+ R7 CX s R7 CX s

This transfer function can be represented by the following theoretical phase and gain diagram (The formula for the negative sign has been omitted) :

Figure 23. Theoretical Gain and Phase behaviour

G2(s) gain

ISO1

R3 R6 F1 F2 1 1 2..R3.C6 2..R7.Cx F3 1 2..R3.C5 F

G2(s) phase 0 F

-90

-180

25/31

APPLICATION NOTE
As it can be seen, a flat gain with a zero phase value extends from F2 to F3. The bandwidth of the regulation loop must lie in this range. First set of components value : And, considering an optotransistor with GISO1 = 0.5, 1 3 = 0.5 6.86 10 82 + G2(s)F CO At this point, considering VFBISO1 = 1V, we can calculate R8 as, ICOMPHI VISO1 + R6 GISO1 FB GISO R3

1)To fix F3 at the zero of the power cell. This gives C5. 2)To cross 0 dB for the overall transfer function at 1/3 of the frequency where is located the zero of the power cell. This crossing frequency is named Fco. This gives R6. 3)To fix F2 at 1/10 of Fco. This gives Cx. Therefore, for the condition 2), we have: FCO = 2450 = 817Hz 3

R6 =

R8 =

IU2 B 600 10-6 0.5

1 + 82

G2(s)817Hz = [(log817 - log30) 20 - 12] = = 16.73dB

At this point we can calculate C5, R6 and Cx: 1 1 C5 = 2 & R F3 = 6.28 1 103 2450 3

1 10-3 The last step is to calculate the zero due to R3 and C6, as: 1 1 F1 = 2 R C = 6.28 1 103 1 10-6 = & 3 6

1.2K +

= 159Hz
The same procedure can be repeated at min load (for this example 5W that leads to a R0=28.8+ The gain Bode diagrams at max load and min load are represented in figures 24 and 25, while the phase Bode diagram for both cases is represented in figure 26.

68nF and, Cx = 2 & R 1 (F

7

CO /10)

1 6.28 18 103 80

100nF

Figure 24. Gain Bode Plot at Max Load

Gain Bode Plot - Max Load

80 Control to Output 60 40 Feedback Overall

Gain (dB)

20 0 -20 -40

10

100

1000

10000

100000

Frequency (Hz)
26/31

APPLICATION NOTE
Figure 25. Gain Bode Plot at Min Load

Gain Bode Plot - Min Load

80 Control to Output 60 Feedback 40

Gain (dB)

Overall 20 0 -20 -40 -60

10

100

1000

10000

100000

Frequency (Hz)

Figure 26. Phase Margin Bode Plot

Phase Margin Bode Plot

100 Overall @ Max Load Overall @ Min Load

50

Phase (Deg)

-50

-100

10

100

1000

10000

100000

Frequency (Hz)

27/31

APPLICATION NOTE

Appendix A:
OUTPUT LOAD DOUBLING IN DISCONTINUOUS FLYBACK Scope This document gives some explanation on the fact that the effective power cell pole of a discontinuous flyback is the double of the one of the load itself, when this load is constituted of a filtering capacitor and the load resistor. It can be also extended very easily to other types of loads, like constant current or constant voltage absorber (Batteries). Pole doubling explanation A discontinuous flyback can be considered as a constant power source. Each cycle delivers always the same energy, whatever the output voltage. This elementary energy can be conventionally expressed as : A modulation of the input (Compensation voltage) of the power cell makes some small changes on the Ip value, thus modifying the level of energy sent on secondary side. Therefore, in figure 27 the following curves can be established, showing the U-I characteristics of the converter output. The tangential slopes to the constant power curves at the working point give the equivalent characteristic of the power cell. The constant power curves being hyperbolas, it can be demonstrated that the intersection of these slopes with the X and Y axis are respectively 2*Iout and 2*Uout. Therefore, the power cell can be identified with a voltage generator of which the value is 2*Uout, and the output impedance Zout is : 2 Uout
out

EOUT = LP

2 IP

Zout = 2 I

= RL

Figure 27. U-I characteristics of the converter output :

2*Uout Small signal working area

Uout

Constant output power variation due to Ip variation

Iout

2*Iout Equivalent loading slopes at the working point

28/31

APPLICATION NOTE
Measurement A transferometer has been used to verify the above results. This apparatus has a sinusoidal generator and two analyser channels. It is able to give directly the transfer function of a circuit by doing the phase and gain ratio between the two channels. The schematics have been used with the standard 12V VIPer100 demoboard. The generator is connected on the VDD supply, after the filtering capacitor. By doing so, the normal working point of the converter is not changed. The first analyser channel is connected on the compensation pin, and the second one on the output. The transfer function of the power cell is CH2/CH1. The results can be seen in figure 30. The pole is a little bit more than 20Hz, and the zero at 550Hz. This can be observed from the phase crossing the -45 axis, or from gain variation of 3 dB. Here are the computations from standard formulas : 1 and 2 & R5 C6 = 10.6Hz 2 & R4 C6 = 557Hz

Where RL is the output load. The total equivalent schematics of the converter power cell can be represented in the following manner in figure 28. And the output power cell pole FP can be computed as : 1 1 RL & RL C C 2 It appears that this pole has a value twice higher than the conventional one computed directly from the simple observation of the output filter. The ESR of the capacitor C can also be added. 2 & Figure 28. equivalent schematics of the converter power cell

FP =

RL

2*U OUT C

RL

Power cell

Output filter cell

The output load RL can be replaced by a constant current source or a constant voltage to obtain the corresponding transfer functions of the total power cell. Note that in the case of a constant current source, we find a pole at: 1 2 & RL C

p=

which is not so easy to guess from the normal schematics, and which really exists!

29/31

APPLICATION NOTE
Figure 29. Measurement Schematic
TR1 G6118-00 OREGA D1 BZW50-180 BYT11/600 Analyser GENERATOR D4
D2

Vin

D3 BYW81/100

C6 2200uF 16V R1 10 R4 0.13

R5 6.8

Analyser CH2

1N4448

C1 22uF 16V U1 R2 3.9K VIPer100 C2 100nF 1 5 C5 100nF R3 5.1K 4 2 3

C3 4.7nF Analyser CH1 C4 10nF

Figure 30. Transfer function of the power cell

+30 dB O

Gain 0 dB -45

Phase

-30 dB 1 10 100 Frequency (Hz) 1k

-90 10k

30/31

APPLICATION NOTE

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics.

1997 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved

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