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STM32F103V8T6 STMicroelectronics
STM32F103V8T6 STMicroelectronics
1
STM32F103x8
STM32F103xB
Medium-density performance line ARM-based 32-bit MCU with 64 or
128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces
Features
ARM 32-bit Cortex-M3 CPU Core
72 MHz maximum frequency,
1.25 DMIPS/MHz (Dhrystone 2.1)
performance at 0 wait state memory
access
Single-cycle multiplication and hardware
division
Memories
64 or 128 Kbytes of Flash memory
20 Kbytes of SRAM
Clock, reset and supply management
2.0 to 3.6 V application supply and I/Os
POR, PDR, and programmable voltage
detector (PVD)
4-to-16 MHz crystal oscillator
Internal 8 MHz factory-trimmed RC
Internal 40 kHz RC
PLL for CPU clock
32 kHz oscillator for RTC with calibration
Low power
Sleep, Stop and Standby modes
V
BAT
supply for RTC and backup registers
2 x 12-bit, 1 s A/D converters (up to 16
channels)
Conversion range: 0 to 3.6 V
Dual-sample and hold capability
Temperature sensor
DMA
7-channel DMA controller
Peripherals supported: timers, ADC, SPIs,
I
2
Cs and USARTs
Up to 80 fast I/O ports
26/37/51/80 I/Os, all mappable on 16
external interrupt vectors and almost all
5 V-tolerant
Debug mode
Serial wire debug (SWD) & JTAG interfaces
7 timers
Three 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input
16-bit, motor control PWM timer with dead-
time generation and emergency stop
2 watchdog timers (Independent and
Window)
SysTick timer 24-bit downcounter
Up to 9 communication interfaces
Up to 2 x I
2
C interfaces (SMBus/PMBus)
Up to 3 USARTs (ISO 7816 interface, LIN,
IrDA capability, modem control)
Up to 2 SPIs (18 Mbit/s)
CAN interface (2.0B Active)
USB 2.0 full-speed interface
CRC calculation unit, 96-bit unique ID
Packages are ECOPACK
Table 1. Device summary
Reference Part number
STM32F103x8
STM32F103C8, STM32F103R8
STM32F103V8, STM32F103T8
STM32F103xB
STM32F103RB STM32F103VB,
STM32F103CB, STM32F103TB
BGA100 10 10 mm
BGA64 5 5 mm
VFQFPN48 7 7 mm
VFQFPN36 6 6 mm
LQFP100 14 14 m
LQFP64 10 10 m
LQFP48 7 7 m
www.st.com
Contents STM32F103x8, STM32F103xB
2/99 Doc ID 13587 Rev 13
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.1 ARM
A
)
2 V
2.4 V
3 V
3.6 V
ai17351
Electrical characteristics STM32F103x8, STM32F103xB
44/99 Doc ID 13587 Rev 13
Figure 18. Typical current consumption in Stop mode with regulator in Run mode versus
temperature at V
DD
= 3.3 V and 3.6 V
Figure 19. Typical current consumption in Stop mode with regulator in Low-power mode versus
temperature at V
DD
= 3.3 V and 3.6 V
0
50
100
150
200
250
300
-45 25 70 90 110
Temperature (C)
C
o
n
s
u
m
p
t
i
o
n
(
A
)
3.3 V
3.6 V
0
50
100
150
200
250
300
-40 0 25 70 85 105
Temperature (C)
C
o
n
s
u
m
p
t
i
o
n
(
A
)
3.3 V
3.6 V
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 13 45/99
Figure 20. Typical current consumption in Standby mode versus temperature at
V
DD
= 3.3 V and 3.6 V
Typical current consumption
The MCU is placed under the following conditions:
All I/O pins are in input mode with a static value at V
DD
or V
SS
(no load).
All peripherals are disabled except if it is explicitly mentioned.
The Flash access time is adjusted to f
HCLK
frequency (0 wait state from 0 to 24 MHz, 1
wait state from 24 to 48 MHz and 2 wait states above).
Ambient temperature and V
DD
supply voltage conditions summarized in Table 9.
Prefetch is ON (Reminder: this bit must be set before clock setting and bus prescaling)
When the peripherals are enabled f
PCLK1
= f
HCLK
/4, f
PCLK
2 = f
HCLK
/2, f
ADCCLK
=
f
PCLK2
/4
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
45 C 25 C 85 C 105 C
Temperature (C)
C
o
n
s
u
m
p
t
i
o
n
(
A
)
3.3 V
3.6 V
Electrical characteristics STM32F103x8, STM32F103xB
46/99 Doc ID 13587 Rev 13
Table 17. Typical current consumption in Run mode, code with data processing
running from Flash
Symbol Parameter Conditions f
HCLK
Typ
(1)
1. Typical values are measures at T
A
= 25 C, V
DD
= 3.3 V.
Unit
All peripherals
enabled
(2)
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
All peripherals
disabled
I
DD
Supply
current in
Run mode
External clock
(3)
3. External clock is 8 MHz and PLL is on when f
HCLK
> 8 MHz.
72 MHz 36 27
mA
48 MHz 24.2 18.6
36 MHz 19 14.8
24 MHz 12.9 10.1
16 MHz 9.3 7.4
8 MHz 5.5 4.6
4 MHz 3.3 2.8
2 MHz 2.2 1.9
1 MHz 1.6 1.45
500 kHz 1.3 1.25
125 kHz 1.08 1.06
Running on high
speed internal RC
(HSI), AHB
prescaler used to
reduce the
frequency
64 MHz 31.4 23.9
mA
48 MHz 23.5 17.9
36 MHz 18.3 14.1
24 MHz 12.2 9.5
16 MHz 8.5 6.8
8 MHz 4.9 4
4 MHz 2.7 2.2
2 MHz 1.6 1.4
1 MHz 1.02 0.9
500 kHz 0.73 0.67
125 kHz 0.5 0.48
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 13 47/99
Table 18. Typical current consumption in Sleep mode, code running from Flash or
RAM
Symbol Parameter Conditions f
HCLK
Typ
(1)
1. Typical values are measures at T
A
= 25 C, V
DD
= 3.3 V.
Unit
All peripherals
enabled
(2)
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
All peripherals
disabled
I
DD
Supply
current in
Sleep mode
External clock
(3)
3. External clock is 8 MHz and PLL is on when f
HCLK
> 8 MHz.
72 MHz 14.4 5.5
mA
48 MHz 9.9 3.9
36 MHz 7.6 3.1
24 MHz 5.3 2.3
16 MHz 3.8 1.8
8 MHz 2.1 1.2
4 MHz 1.6 1.1
2 MHz 1.3 1
1 MHz 1.11 0.98
500 kHz 1.04 0.96
125 kHz 0.98 0.95
Running on high
speed internal RC
(HSI), AHB prescaler
used to reduce the
frequency
64 MHz 12.3 4.4
48 MHz 9.3 3.3
36 MHz 7 2.5
24 MHz 4.8 1.8
16 MHz 3.2 1.2
8 MHz 1.6 0.6
4 MHz 1 0.5
2 MHz 0.72 0.47
1 MHz 0.56 0.44
500 kHz 0.49 0.42
125 kHz 0.43 0.41
Electrical characteristics STM32F103x8, STM32F103xB
48/99 Doc ID 13587 Rev 13
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 19. The MCU is placed
under the following conditions:
all I/O pins are in input mode with a static value at V
DD
or V
SS
(no load)
all peripherals are disabled unless otherwise mentioned
the given value is calculated by measuring the current consumption
with all peripherals clocked off
with only one peripheral clocked on
ambient operating temperature and V
DD
supply voltage conditions summarized in
Table 6
Table 19. Peripheral current consumption
(1)
1. f
HCLK
= 72 MHz, f
APB1
= f
HCLK
/2, f
APB2
= f
HCLK
, default prescaler value for each peripheral.
Peripheral Typical consumption at 25 C Unit
APB1
TIM2 1.2
mA
TIM3 1.2
TIM4 0.9
SPI2 0.2
USART2 0.35
USART3 0.35
I2C1 0.39
I2C2 0.39
USB 0.65
CAN 0.72
APB2
GPIO A 0.47
mA
GPIO B 0.47
GPIO C 0.47
GPIO D 0.47
GPIO E 0.47
ADC1
(2)
2. Specific conditions for ADC: f
HCLK
= 56 MHz, f
APB1
= f
HCLK
/2, f
APB2
= f
HCLK
, f
ADCCLK
= f
APB2/4
, ADON bit
in the ADC_CR2 register is set to 1.
1.81
ADC2 1.78
TIM1 1.6
SPI1 0.43
USART1 0.85
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 13 49/99
5.3.6 External clock source characteristics
High-speed external user clock generated from an external source
The characteristics given in Table 20 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 9.
Low-speed external user clock generated from an external source
The characteristics given in Table 21 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 9.
Table 20. High-speed external user clock characteristics
Symbol Parameter Conditions Min Typ Max Unit
f
HSE_ext
User external clock source
frequency
(1)
1 8 25 MHz
V
HSEH
OSC_IN input pin high level voltage 0.7V
DD
V
DD
V
V
HSEL
OSC_IN input pin low level voltage V
SS
0.3V
DD
t
w(HSE)
t
w(HSE)
OSC_IN high or low time
(1)
1. Guaranteed by design, not tested in production.
5
ns
t
r(HSE)
t
f(HSE)
OSC_IN rise or fall time
(1)
20
C
in(HSE)
OSC_IN input capacitance
(1)
5 pF
DuCy
(HSE)
Duty cycle 45 55 %
I
L
OSC_IN Input leakage current V
SS
V
IN
V
DD
1 A
Table 21. Low-speed external user clock characteristics
Symbol Parameter Conditions Min Typ Max Unit
f
LSE_ext
User External clock source
frequency
(1)
1. Guaranteed by design, not tested in production.
32.768 1000 kHz
V
LSEH
OSC32_IN input pin high level
voltage
0.7V
DD
V
DD
V
V
LSEL
OSC32_IN input pin low level
voltage
V
SS
0.3V
DD
t
w(LSE)
t
w(LSE)
OSC32_IN high or low time
(1)
450
ns
t
r(LSE)
t
f(LSE)
OSC32_IN rise or fall time
(1)
50
C
in(LSE)
OSC32_IN input capacitance
(1)
5 pF
DuCy
(LSE)
Duty cycle 30 70 %
I
L
OSC32_IN Input leakage
current
V
SS
V
IN
V
DD
1 A
Electrical characteristics STM32F103x8, STM32F103xB
50/99 Doc ID 13587 Rev 13
Figure 21. High-speed external clock source AC timing diagram
Figure 22. Low-speed external clock source AC timing diagram
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Table 22. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
ai14143
OSC_IN
EXTERNAL
STM32F103xx
CLOCK SOURCE
V
HSEH
t
f(HSE)
t
W(HSE)
I
L
90%
10%
T
HSE
t
t
r(HSE)
t
W(HSE)
f
HSE_ext
V
HSEL
ai14144b
OSC32_IN
EXTERNAL
STM32F103xx
CLOCK SOURCE
V
LSEH
t
f(LSE)
t
W(LSE)
I
L
90%
10%
T
LSE
t
t
r(LSE)
t
W(LSE)
f
LSE_ext
V
LSEL
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 13 51/99
For C
L1
and C
L2
, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 23). C
L1
and C
L2
are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C
L1
and C
L2
. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
C
L1
and C
L2
. Refer to the application note AN2867 Oscillator design guide for ST
microcontrollers available from the ST website www.st.com.
Figure 23. Typical application with an 8 MHz crystal
1. R
EXT
value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Table 23. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 22. HSE 4-16 MHz oscillator characteristics
(1) (2)
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Based on characterization, not tested in production.
Symbol Parameter Conditions Min Typ Max Unit
f
OSC_IN
Oscillator frequency 4 8 16 MHz
R
F
Feedback resistor 200 k
C
Recommended load capacitance
versus equivalent serial
resistance of the crystal (R
S
)
(3)
3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a
humid environment, due to the induced leakage and the bias condition change. However, it is
recommended to take this point into account if the MCU is used in tough humidity conditions.
R
S
= 30 30 pF
i
2
HSE driving current
V
DD
= 3.3 V, V
IN
= V
SS
with 30 pF load
1 mA
g
m
Oscillator transconductance Startup 25 mA/V
t
SU(HSE
(4)
4. t
SU(HSE)
is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
startup time V
DD
is stabilized 2 ms
ai14145
OSC_OUT
OSC_IN
f
HSE
C
L1
R
F
STM32F103xx
8 MHz
resonator
R
EXT
(1)
C
L2
Resonator with
integrated capacitors
Bias
controlled
gain
Electrical characteristics STM32F103x8, STM32F103xB
52/99 Doc ID 13587 Rev 13
Note: For C
L1
and C
L2
it is recommended to use high-quality ceramic capacitors in the 5 pF to
15 pF range selected to match the requirements of the crystal or resonator. C
L1
and C
L2,
are
usually the same size. The crystal manufacturer typically specifies a load capacitance which
is the series combination of C
L1
and C
L2
.
Load capacitance C
L
has the following formula: C
L
= C
L1
x C
L2
/ (C
L1
+ C
L2
) + C
stray
where
C
stray
is the pin capacitance and board or trace PCB-related capacitance. Typically, it is
between 2 pF and 7 pF.
Caution: To avoid exceeding the maximum value of C
L1
and C
L2
(15 pF) it is strongly recommended
to use a resonator with a load capacitance C
L
7 pF. Never use a resonator with a load
capacitance of 12.5 pF.
Example: if you choose a resonator with a load capacitance of C
L
= 6 pF, and C
stray
= 2 pF,
then C
L1
= C
L2
= 8 pF.
Table 23. LSE oscillator characteristics (f
LSE
= 32.768 kHz)
(1)
(2)
Symbol Parameter Conditions Min Typ Max Unit
R
F
Feedback resistor 5 M
C
Recommended load capacitance
versus equivalent serial
resistance of the crystal (R
S
)
R
S
= 30 K 15 pF
I
2
LSE driving current
V
DD
= 3.3 V
V
IN
= V
SS
1.4 A
g
m
Oscillator transconductance 5 A/V
t
SU(LSE)
(3)
Startup time
V
DD
is
stabilized
T
A
= 50 C 1.5
s
T
A
= 25 C 2.5
T
A
= 10 C 4
T
A
= 0 C 6
T
A
= -10 C 10
T
A
= -20 C 17
T
A
= -30 C 32
T
A
= -40 C 60
1. Based on characterization, not tested in production.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 Oscillator design guide for
ST microcontrollers.
3. t
SU(LSE)
is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 13 53/99
Figure 24. Typical application with a 32.768 kHz crystal
5.3.7 Internal clock source characteristics
The parameters given in Table 24 are derived from tests performed under ambient
temperature and V
DD
supply voltage conditions summarized in Table 9.
High-speed internal (HSI) RC oscillator
ai14146
OSC32_OUT
OSC32_IN
f
LSE
C
L1
R
F
STM32F103xx
32.768 kHz
resonator
C
L2
Resonator with
integrated capacitors
Bias
controlled
gain
Table 24. HSI oscillator characteristics
(1)
1. V
DD
= 3.3 V, T
A
= 40 to 105 C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
f
HSI
Frequency 8 MHz
DuCy
(HSI)
Duty cycle 45 55 %
ACC
HSI
Accuracy of the HSI
oscillator
User-trimmed with the RCC_CR
register
(2)
2. Refer to application note AN2868 STM32F10xxx internal RC oscillator (HSI) calibration available from
the ST website www.st.com.
1
(3)
3. Guaranteed by design, not tested in production.
%
Factory-
calibrated
(4)
4. Based on characterization, not tested in production.
T
A
= 40 to 105 C 2 2.5 %
T
A
= 10 to 85 C 1.5 2.2 %
T
A
= 0 to 70 C 1.3 2 %
T
A
= 25 C 1.1 1.8 %
t
su(HSI)
(4)
HSI oscillator
startup time
1 2 s
I
DD(HSI)
(4)
HSI oscillator power
consumption
80 100 A
Electrical characteristics STM32F103x8, STM32F103xB
54/99 Doc ID 13587 Rev 13
Low-speed internal (LSI) RC oscillator
Wakeup time from low-power mode
The wakeup times given in Table 26 is measured on a wakeup phase with a 8-MHz HSI RC
oscillator. The clock source used to wake up the device depends from the current operating
mode:
Stop or Standby mode: the clock source is the RC oscillator
Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under ambient temperature and V
DD
supply
voltage conditions summarized in Table 9.
Table 25. LSI oscillator characteristics
(1)
1. V
DD
= 3 V, T
A
= 40 to 105 C unless otherwise specified.
Symbol Parameter
Min
Typ Max Unit
f
LSI
(2)
2. Based on characterization, not tested in production.
Frequency 30 40 60 kHz
t
su(LSI)
(3)
3. Guaranteed by design, not tested in production.
LSI oscillator startup time 85 s
I
DD(LSI)
(3)
LSI oscillator power consumption 0.65 1.2 A
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 13 55/99
5.3.8 PLL characteristics
The parameters given in Table 27 are derived from tests performed under ambient
temperature and V
DD
supply voltage conditions summarized in Table 9.
5.3.9 Memory characteristics
Flash memory
The characteristics are given at T
A
= 40 to 105 C unless otherwise specified.
Table 26. Low-power mode wakeup timings
Symbol Parameter Typ Unit
t
WUSLEEP
(1)
1. The wakeup times are measured from the wakeup event to the point in which the user application code
reads the first instruction.
Wakeup from Sleep mode 1.8 s
t
WUSTOP
(1)
Wakeup from Stop mode (regulator in run mode) 3.6
s
Wakeup from Stop mode (regulator in low power
mode)
5.4
t
WUSTDBY
(1)
Wakeup from Standby mode 50 s
Table 27. PLL characteristics
Symbol Parameter
Value
Unit
Min
(1)
1. Based on characterization, not tested in production.
Typ Max
(1)
f
PLL_IN
PLL input clock
(2)
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by f
PLL_OUT
.
1 8.0 25 MHz
PLL input clock duty cycle 40 60 %
f
PLL_OUT
PLL multiplier output clock 16 72 MHz
t
LOCK
PLL lock time 200 s
Jitter Cycle-to-cycle jitter 300 ps
Table 28. Flash memory characteristics
Symbol Parameter Conditions Min
(1)
Typ Max
(1)
Unit
t
prog
16-bit programming time T
A
= 40 to +105 C 40 52.5 70 s
t
ERASE
Page (1 KB) erase time T
A
= 40 to +105 C 20 40 ms
t
ME
Mass erase time T
A
= 40 to +105 C 20 40 ms
Electrical characteristics STM32F103x8, STM32F103xB
56/99 Doc ID 13587 Rev 13
Table 29. Flash memory endurance and data retention
5.3.10 EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the
device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V
DD
and
V
SS
through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 30. They are based on the EMS levels and classes
defined in application note AN1709.
I
DD
Supply current
Read mode
f
HCLK
= 72 MHz with 2 wait
states, V
DD
= 3.3 V
20 mA
Write / Erase modes
f
HCLK
= 72 MHz, V
DD
= 3.3 V
5 mA
Power-down mode / Halt,
V
DD
= 3.0 to 3.6 V
50 A
V
prog
Programming voltage 2 3.6 V
1. Guaranteed by design, not tested in production.
Symbol Parameter Conditions
Value
Unit
Min
(1)
1. Based on characterization, not tested in production.
Typ Max
N
END
Endurance
T
A
= 40 to +85 C (6 suffix versions)
T
A
= 40 to +105 C (7 suffix versions)
10 kcycles
t
RET
Data retention
1 kcycle
(2)
at T
A
= 85 C
2. Cycling performed over the whole temperature range.
30
Years 1 kcycle
(2)
at T
A
= 105 C 10
10 kcycles
(2)
at T
A
= 55 C 20
Table 28. Flash memory characteristics (continued)
Symbol Parameter Conditions Min
(1)
Typ Max
(1)
Unit
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 13 57/99
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 30. EMS characteristics
Symbol Parameter Conditions
Level/
Class
V
FESD
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
V
DD
= 3.3 V, T
A
= +25 C,
f
HCLK
= 72 MHz
conforms to IEC 61000-4-2
2B
V
EFTB
Fast transient voltage burst limits to be
applied through 100 pF on V
DD
and V
SS
pins to induce a functional disturbance
V
DD
= 3.3 V, T
A
= +25 C,
f
HCLK
= 72 MHz
conforms to IEC 61000-4-4
4A
Table 31. EMI characteristics
Symbol Parameter Conditions
Monitored
frequency band
Max vs. [f
HSE
/f
HCLK
]
Unit
8/48 MHz 8/72 MHz
S
EMI
Peak level
V
DD
= 3.3 V, T
A
= 25 C,
LQFP100 package
compliant with
IEC 61967-2
0.1 to 30 MHz 12 12
dBV 30 to 130 MHz 22 19
130 MHz to 1GHz 23 29
SAE EMI Level 4 4 -
Electrical characteristics STM32F103x8, STM32F103xB
58/99 Doc ID 13587 Rev 13
5.3.11 Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 32. ESD absolute maximum ratings
Symbol Ratings Conditions Class Maximum value
(1)
1. Based on characterization results, not tested in production.
Unit
V
ESD(HBM)
Electrostatic discharge
voltage (human body model)
T
A
= +25 C
conforming to
JESD22-A114
2 2000
V
V
ESD(CDM)
Electrostatic discharge
voltage (charge device
model)
T
A
= +25 C
conforming to
JESD22-C101
II 500
Table 33. Electrical sensitivities
Symbol Parameter Conditions Class
LU Static latch-up class T
A
= +105 C conforming to JESD78A II level A
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 13 59/99
5.3.12 I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V
SS
or
above V
DD
(for standard, 3 V-capable I/O pins) should be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibilty to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into the
I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (>5
LSB TUE), out of spec current injection on adjacent pins or other functional failure (for
example reset, oscillator frequency deviation).
The test results are given in Table 34
Table 34. I/O current injection susceptibility
Symbol Description
Functional susceptibility
Unit
Negative
injection
Positive
injection
I
INJ
Injected current on OSC_IN32,
OSC_OUT32, PA4, PA5, PC13
-0 +0
mA
Injected current on all FT pins -5 +0
Injected current on any other pin -5 +5
Electrical characteristics STM32F103x8, STM32F103xB
60/99 Doc ID 13587 Rev 13
5.3.13 I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 35 are derived from tests
performed under the conditions summarized in Table 9. All I/Os are CMOS and TTL
compliant.
Table 35. I/O static characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
IL
Standard IO input low
level voltage
0.3 0.28*(V
DD
-2 V)+0.8 V V
IO FT
(1)
input low level
voltage
0.3 0.32*(V
DD
-2V)+0.75 V V
V
IH
Standard IO input high
level voltage
0.41*(V
DD
-2 V)+1.3 V V
DD
+0.3 V
IO FT
(1)
input high level
voltage
V
DD
> 2 V
0.42*(V
DD
-2 V)+1 V
5.5
V
V
DD
2 V 5.2
V
hys
Standard IO Schmitt
trigger voltage
hysteresis
(2)
200 mV
IO FT Schmitt trigger
voltage hysteresis
(2)
5% V
DD
(3)
mV
I
lkg
Input leakage current
(4)
V
SS
V
IN
V
DD
Standard I/Os
1
A
V
IN
= 5 V
I/O FT
3
R
PU
Weak pull-up equivalent
resistor
(5)
V
IN
= V
SS
30 40 50 k
R
PD
Weak pull-down
equivalent resistor
(5)
V
IN
= V
DD
30 40 50 k
C
IO
I/O pin capacitance 5 pF
1. FT = Five-volt tolerant. In order to sustain a voltage higher than V
DD
+0.3 the internal pull-up/pull-down resistors must be
disabled.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
3. With a minimum of 100 mV.
4. Leakage could be higher than max. if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimum (~10% order).
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 13 61/99
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 25 and Figure 26 for standard I/Os, and
in Figure 27 and Figure 28 for 5 V tolerant I/Os.
Figure 25. Standard I/O input characteristics - CMOS port
Figure 26. Standard I/O input characteristics - TTL port
ai17277b
V
DD
(V)
1.3
0.8
2 3.6
nput range
not guaranteed
1.59
1
2.7
V
H
=0.41(V
DD
-2)+1.3
3
0.7
CMOS standard requirement V
H
=0.65V
DD
3.3
V
H
/V
L
(V)
CMOS standard requirement V
L
=0.35V
DD
l.25
l.96
l.7l
l.7l
l.59
l
l.08
l.08
v
Lmax
v
Hmin
V
DD
-2)+0.8
=0.28(V
L
ai17278
2 3.6
nput range
not guaranteed
V
H
/V
L
(V)
1.3
2.0
0.8
2.16
1.96
1.25
TTL requirements V
H
=2V
V
H
=0.41(V
DD
-2)+1.3
V
L
=0.28(V
DD
-2)+0.8
TTL requirements V
L
=0.8V
V
DD
(V)
v
Lmax
v
Hmin
Electrical characteristics STM32F103x8, STM32F103xB
62/99 Doc ID 13587 Rev 13
Figure 27. 5 V tolerant I/O input characteristics - CMOS port
Figure 28. 5 V tolerant I/O input characteristics - TTL port
VDD
1.3
2 3.6
CMOS standard requirements V
H
=0.65V
DD
CMOS standard requirment V
L
=0.35V
DD
1.67
1
2.7
0.7
3 3.3
1
0.75
1.295
0.975
1.42
1.07
1.55
1.16
V
H
/V
L
(V)
V
DD
(V)
nput range
not guaranteed
ai17279b
V
H
=0.42(V
DD
-2)+1
V
L
=0.32(V
DD
-2)+0.75
2.0
0.8
2 3.6 2.16
not guaranteed
nput range
1.67
1
0.75
TTL requirement V
H
=2V
V
H
=0.42*(V
DD
-2)+1
V
L
=0.32*(V
DD
-2)+0.75
TTL requirements V
L
=0.8V
V
H
/V
L
(V)
V
DD
(V)
v
Lmax
v
Hmin
ai17280
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 13 63/99
Output driving current
The GPIOs (general-purpose inputs/outputs) can sink or source up to 8 mA, and sink or
source up to 20 mA (with a relaxed V
OL
/V
OH
).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
The sum of the currents sourced by all the I/Os on V
DD,
plus the maximum Run
consumption of the MCU sourced on V
DD,
cannot exceed the absolute maximum rating
I
VDD
(see Table 7).
The sum of the currents sunk by all the I/Os on V
SS
plus the maximum Run
consumption of the MCU sunk on V
SS
cannot exceed the absolute maximum rating
I
VSS
(see Table 7).
Output voltage levels
Unless otherwise specified, the parameters given in Table 36 are derived from tests
performed under ambient temperature and V
DD
supply voltage conditions summarized in
Table 9. All I/Os are CMOS and TTL compliant.
Table 36. Output voltage characteristics
Symbol Parameter Conditions Min Max Unit
V
OL
(1)
1. The I
IO
current sunk by the device must always respect the absolute maximum rating specified in Table 7
and the sum of I
IO
(I/O ports and control pins) must not exceed I
VSS
.
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
CMOS port
(2)
,
I
IO
= +8 mA
2.7 V < V
DD
< 3.6 V
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
0.4
V
V
OH
(3)
3. The I
IO
current sourced by the device must always respect the absolute maximum rating specified in
Table 7 and the sum of I
IO
(I/O ports and control pins) must not exceed I
VDD
.
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
V
DD
0.4
V
OL
(1)
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
TTL port
(2)
I
IO
=+ 8mA
2.7 V < V
DD
< 3.6 V
0.4
V
V
OH
(3)
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
2.4
V
OL
(1)(4)
4. Based on characterization data, not tested in production.
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
I
IO
= +20 mA
2.7 V < V
DD
< 3.6 V
1.3
V
V
OH
(3)(4)
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
V
DD
1.3
V
OL
(1)(4)
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
I
IO
= +6 mA
2 V < V
DD
< 2.7 V
0.4
V
V
OH
(3)(4)
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
V
DD
0.4
Electrical characteristics STM32F103x8, STM32F103xB
64/99 Doc ID 13587 Rev 13
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 29 and
Table 37, respectively.
Unless otherwise specified, the parameters given in Table 37 are derived from tests
performed under the ambient temperature and V
DD
supply voltage conditions summarized
in Table 9.
Table 37. I/O AC characteristics
(1)
1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a
description of GPIO Port configuration register.
MODEx[1:0]
bit value
(1)
Symbol Parameter Conditions Min Max Unit
10
f
max(IO)out
Maximum frequency
(2)
2. The maximum frequency is defined in Figure 29.
C
L
= 50 pF, V
DD
= 2 V to 3.6 V 2 MHz
t
f(IO)out
Output high to low
level fall time
C
L
= 50 pF, V
DD
= 2 V to 3.6 V
125
(3)
3. Guaranteed by design, not tested in production.
ns
t
r(IO)out
Output low to high
level rise time
125
(3)
01
f
max(IO)out
Maximum frequency
(2)
C
L
= 50 pF, V
DD
= 2 V to 3.6 V 10 MHz
t
f(IO)out
Output high to low
level fall time
C
L
= 50 pF, V
DD
= 2 V to 3.6 V
25
(3)
ns
t
r(IO)out
Output low to high
level rise time
25
(3)
11
F
max(IO)out
Maximum frequency
(2)
C
L
= 30 pF, V
DD
= 2.7 V to 3.6 V 50 MHz
C
L
= 50 pF, V
DD
= 2.7 V to 3.6 V 30 MHz
C
L
= 50 pF, V
DD
= 2 V to 2.7 V 20 MHz
t
f(IO)out
Output high to low
level fall time
C
L
= 30 pF, V
DD
= 2.7 V to 3.6 V 5
(3)
ns
C
L
= 50 pF, V
DD
= 2.7 V to 3.6 V 8
(3)
C
L
= 50 pF, V
DD
= 2 V to 2.7 V 12
(3)
t
r(IO)out
Output low to high
level rise time
C
L
= 30 pF, V
DD
= 2.7 V to 3.6 V 5
(3)
C
L
= 50 pF, V
DD
= 2.7 V to 3.6 V 8
(3)
C
L
= 50 pF, V
DD
= 2 V to 2.7 V 12
(3)
- t
EXTIpw
Pulse width of
external signals
detected by the EXTI
controller
10 ns
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 13 65/99
Figure 29. I/O AC characteristics definition
5.3.14 NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R
PU
(see Table 35).
Unless otherwise specified, the parameters given in Table 38 are derived from tests
performed under the ambient temperature and V
DD
supply voltage conditions summarized
in Table 9.
ai14131
10%
90%
50%
t
r(I O)out
External
Output
on 50pF
Maximum frequency is achieved if (t
r
+ t
f
) 2/3)T and if the duty cycle is (45-55%)
10%
50%
90%
when loaded by 50 pF
T
t
r(I O)out
Table 38. NRST pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
IL(NRST)
(1)
1. Guaranteed by design, not tested in production.
NRST Input low level voltage 0.5 0.8
V
V
IH(NRST)
(1)
NRST Input high level voltage 2 V
DD
+0.5
V
hys(NRST)
NRST Schmitt trigger voltage
hysteresis
200 mV
R
PU
Weak pull-up equivalent resistor
(2)
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
V
IN
= V
SS
30 40 50 k
V
F(NRST)
(1)
NRST Input filtered pulse 100 ns
V
NF(NRST)
(1)
NRST Input not filtered pulse 300 ns
Electrical characteristics STM32F103x8, STM32F103xB
66/99 Doc ID 13587 Rev 13
Figure 30. Recommended NRST pin protection
2. The reset network protects the device against parasitic resets.
3. The user must ensure that the level on the NRST pin can go below the V
IL(NRST)
max level specified in
Table 38. Otherwise the reset will not be taken into account by the device.
5.3.15 TIM timer characteristics
The parameters given in Table 39 are guaranteed by design.
Refer to Section 5.3.12: I/O current injection characteristics for details on the input/output
alternate function characteristics (output compare, input capture, external clock, PWM
output).
ai14132d
STM32F10x
R
PU
NRST
(2)
V
DD
Filter
Internal reset
0.1 F
External
reset circuit
(1)
Table 39. TIMx
(1)
characteristics
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers.
Symbol Parameter Conditions Min Max Unit
t
res(TIM)
Timer resolution time
1 t
TIMxCLK
f
TIMxCLK
= 72 MHz 13.9 ns
f
EXT
Timer external clock
frequency on CH1 to CH4
0 f
TIMxCLK
/2 MHz
f
TIMxCLK
= 72 MHz 0 36 MHz
Res
TIM
Timer resolution 16 bit
t
COUNTER
16-bit counter clock period
when internal clock is
selected
1 65536 t
TIMxCLK
f
TIMxCLK
= 72 MHz 0.0139 910 s
t
MAX_COUNT
Maximum possible count
65536 65536 t
TIMxCLK
f
TIMxCLK
= 72 MHz 59.6 s
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 13 67/99
5.3.16 Communications interfaces
I
2
C interface characteristics
Unless otherwise specified, the parameters given in Table 40 are derived from tests
performed under the ambient temperature, f
PCLK1
frequency and V
DD
supply voltage
conditions summarized in Table 9.
The STM32F103xx performance line I
2
C interface meets the requirements of the standard
I
2
C communication protocol with the following restrictions: the I/O pins SDA and SCL are
mapped to are not true open-drain. When configured as open-drain, the PMOS connected
between the I/O pin and V
DD
is disabled, but is still present.
The I
2
C characteristics are described in Table 40. Refer also to Section 5.3.12: I/O current
injection characteristics for more details on the input/output alternate function characteristics
(SDA and SCL).
Table 40. I
2
C characteristics
Symbol Parameter
Standard mode I
2
C
(1)
1. Guaranteed by design, not tested in production.
Fast mode I
2
C
(1)(2)
2. f
PCLK1
must be higher than 2 MHz to achieve standard mode I
2
C frequencies. It must be higher than
4 MHz to achieve fast mode I
2
C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz
maximum I2C fast mode clock.
Unit
Min Max Min Max
t
w(SCLL)
SCL clock low time 4.7 1.3
s
t
w(SCLH)
SCL clock high time 4.0 0.6
t
su(SDA)
SDA setup time 250 100
ns
t
h(SDA)
SDA data hold time 0
(3)
3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
period of SCL signal.
0
(4)
4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
900
(3)
t
r(SDA)
t
r(SCL)
SDA and SCL rise time 1000 20 + 0.1C
b
300
t
f(SDA)
t
f(SCL)
SDA and SCL fall time 300 300
t
h(STA)
Start condition hold time 4.0 0.6
s
t
su(STA)
Repeated Start condition
setup time
4.7 0.6
t
su(STO)
Stop condition setup time 4.0 0.6 s
t
w(STO:STA)
Stop to Start condition time
(bus free)
4.7 1.3 s
C
b
Capacitive load for each bus
line
400 400 pF
Electrical characteristics STM32F103x8, STM32F103xB
68/99 Doc ID 13587 Rev 13
Figure 31. I
2
C bus AC waveforms and measurement circuit
1. Measurement points are done at CMOS levels: 0.3V
DD
and 0.7V
DD
.
Table 41. SCL frequency (f
PCLK1
= 36 MHz.,V
DD
= 3.3 V)
(1)(2)
1. R
P
= External pull-up resistance, f
SCL
= I
2
C speed,
2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the
tolerance on the achieved speed 2%. These variations depend on the accuracy of the external
components used to design the application.
f
SCL
(kHz)
I2C_CCR value
R
P
= 4.7 k
400 0x801E
300 0x8028
200 0x803C
100 0x00B4
50 0x0168
20 0x0384
ai14133d
Start
SDA
100
4.7k
IC bus
4.7k
100
V
DD
V
DD
STM32F10x
SDA
SCL
t
f(SDA)
t
r(SDA)
SCL
t
h(STA)
t
w(SCLH)
t
w(SCLL)
t
su(SDA)
t
r(SCL)
t
f(SCL)
t
h(SDA)
Start repeated
Start
t
su(STA)
t
su(STO)
Stop
t
su(STO:STA)
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 13 69/99
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 42 are derived from tests
performed under the ambient temperature, f
PCLKx
frequency and V
DD
supply voltage
conditions summarized in Table 9.
Refer to Section 5.3.12: I/O current injection characteristics for more details on the
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 42. SPI characteristics
Symbol Parameter Conditions Min Max Unit
f
SCK
1/t
c(SCK)
SPI clock frequency
Master mode 18
MHz
Slave mode 18
t
r(SCK)
t
f(SCK)
SPI clock rise and fall
time
Capacitive load: C = 30 pF 8 ns
DuCy(SCK)
SPI slave input clock
duty cycle
Slave mode 30 70 %
t
su(NSS)
(1)
1. Based on characterization, not tested in production.
NSS setup time Slave mode 4t
PCLK
ns
t
h(NSS)
(1)
NSS hold time Slave mode 2t
PCLK
t
w(SCKH)
(1)
t
w(SCKL)
(1)
SCK high and low time
Master mode, f
PCLK
= 36 MHz,
presc = 4
50 60
t
su(MI)
(1)
t
su(SI)
(1)
Data input setup time
Master mode 5
Slave mode 5
t
h(MI)
(1)
Data input hold time
Master mode 5
t
h(SI)
(1)
Slave mode 4
t
a(SO)
(1)(2)
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
Data output access
time
Slave mode, f
PCLK
= 20 MHz 0 3t
PCLK
t
dis(SO)
(1)(3)
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
Data output disable
time
Slave mode 2 10
t
v(SO)
(1)
Data output valid time Slave mode (after enable edge) 25
t
v(MO)
(1)
Data output valid time Master mode (after enable edge) 5
t
h(SO)
(1)
Data output hold time
Slave mode (after enable edge) 15
t
h(MO)
(1)
Master mode (after enable edge) 2
Electrical characteristics STM32F103x8, STM32F103xB
70/99 Doc ID 13587 Rev 13
Figure 32. SPI timing diagram - slave mode and CPHA = 0
Figure 33. SPI timing diagram - slave mode and CPHA = 1
(1)
1. Measurement points are done at CMOS levels: 0.3V
DD
and 0.7V
DD
.
ai14134c
S
C
K
I
n
p
u
t CPHA=0
MOSI
I NPUT
MISO
OUT PUT
CPHA=0
MSB OUT
MSB IN
BI T6 OUT
LSB IN
LSB OUT
CPOL=0
CPOL=1
BI T1 IN
NSS input
t
SU(NSS)
t
c(SCK)
t
h(NSS)
t
a(SO)
t
w(SCKH)
t
w(SCKL)
t
v(SO)
t
h(SO)
t
r(SCK)
t
f(SCK)
t
dis(SO)
t
su(SI)
t
h(SI)
ai14135
S
C
K
I
n
p
u
t CPHA=1
MOSI
I NPUT
MISO
OUT PUT
CPHA=1
MSB OUT
MSB IN
BI T6 OUT
LSB IN
LSB OUT
CPOL=0
CPOL=1
BI T1 IN
t
SU(NSS) t
c(SCK)
t
h(NSS)
t
a(SO)
t
w(SCKH)
t
w(SCKL)
t
v(SO)
t
h(SO)
t
r(SCK)
t
f(SCK)
t
dis(SO)
t
su(SI)
t
h(SI)
NSS input
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 13 71/99
Figure 34. SPI timing diagram - master mode
(1)
1. Measurement points are done at CMOS levels: 0.3V
DD
and 0.7V
DD
.
USB characteristics
The USB interface is USB-IF certified (Full Speed).
Table 43. USB startup time
Symbol Parameter Max Unit
t
STARTUP
(1)
1. Guaranteed by design, not tested in production.
USB transceiver startup time 1 s
ai14136
S
C
K
I
n
p
u
t CPHA=0
MOSI
OUTUT
MISO
INPUT
CPHA=0
MSBIN
MSB OUT
BI T6 IN
LSB OUT
LSB IN
CPOL=0
CPOL=1
BI T1 OUT
NSS input
t
c(SCK)
t
w(SCKH)
t
w(SCKL)
t
r(SCK)
t
f(SCK)
t
h(MI)
High
S
C
K
I
n
p
u
t CPHA=1
CPHA=1
CPOL=0
CPOL=1
t
su(MI)
t
v(MO)
t
h(MO)
Electrical characteristics STM32F103x8, STM32F103xB
72/99 Doc ID 13587 Rev 13
Figure 35. USB timings: definition of data signal rise and fall time
5.3.17 CAN (controller area network) interface
Refer to Section 5.3.12: I/O current injection characteristics for more details on the
input/output alternate function characteristics (CAN_TX and CAN_RX).
Table 44. USB DC electrical characteristics
Symbol Parameter Conditions Min.
(1)
1. All the voltages are measured from the local ground potential.
Max.
(1)
Unit
Input levels
V
DD
USB operating voltage
(2)
2. To be compliant with the USB 2.0 full-speed electrical specification, the USBDP (D+) pin should be pulled
up with a 1.5 k resistor to a 3.0-to-3.6 V voltage range.
3.0
(3)
3. The STM32F103xx USB functionality is ensured down to 2.7 V but not the full USB electrical
characteristics which are degraded in the 2.7-to-3.0 V V
DD
voltage range.
3.6 V
V
DI
(4)
4. Guaranteed by design, not tested in production.
Differential input sensitivity I(USBDP, USBDM) 0.2
V V
CM
(4)
Differential common mode range Includes V
DI
range 0.8 2.5
V
SE
(4)
Single ended receiver threshold 1.3 2.0
Output levels
V
OL
Static output level low R
L
of 1.5 k to 3.6 V
(5)
5. R
L
is the load connected on the USB drivers
0.3
V
V
OH
Static output level high R
L
of 15 k to V
SS
(5)
2.8 3.6
Table 45. USB: Full-speed electrical characteristics
(1)
1. Guaranteed by design, not tested in production.
Symbol Parameter Conditions Min Max Unit
Driver characteristics
t
r
Rise time
(2)
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
C
L
= 50 pF
4 20 ns
t
f
Fall time
(2)
C
L
= 50 pF 4 20 ns
t
rfm
Rise/ fall time matching t
r
/t
f
90 110 %
V
CRS
Output signal crossover voltage 1.3 2.0 V
ai14137
t
f
Differential
data lines
V
SS
V
CRS
t
r
Crossover
points
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 13 73/99
5.3.18 12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 46 are derived from tests
performed under the ambient temperature, f
PCLK2
frequency and V
DDA
supply voltage
conditions summarized in Table 9.
Note: It is recommended to perform a calibration after each power-up.
Table 46. ADC characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
DDA
Power supply 2.4 3.6 V
V
REF+
Positive reference voltage 2.4 V
DDA
V
I
VREF
Current on the V
REF
input pin 160
(1)
220
(1)
A
f
ADC
ADC clock frequency 0.6 14 MHz
f
S
(2)
Sampling rate 0.05 1 MHz
f
TRIG
(2)
External trigger frequency
f
ADC
= 14 MHz 823 kHz
17 1/f
ADC
V
AIN
(3)
Conversion voltage range
0 (V
SSA
or V
REF-
tied to ground)
V
REF+
V
R
AIN
(2)
External input impedance
See Equation 1 and
Table 47 for details
50 k
R
ADC
(2)
Sampling switch resistance 1 k
C
ADC
(2)
Internal sample and hold
capacitor
8 pF
t
CAL
(2)
Calibration time
f
ADC
= 14 MHz 5.9 s
83 1/f
ADC
t
lat
(2)
Injection trigger conversion
latency
f
ADC
= 14 MHz 0.214 s
3
(4)
1/f
ADC
t
latr
(2)
Regular trigger conversion
latency
f
ADC
= 14 MHz 0.143 s
2
(4)
1/f
ADC
t
S
(2)
Sampling time
f
ADC
= 14 MHz 0.107 17.1 s
1.5 239.5 1/f
ADC
t
STAB
(2)
Power-up time 0 0 1 s
t
CONV
(2)
Total conversion time
(including sampling time)
f
ADC
= 14 MHz 1 18 s
14 to 252 (t
S
for sampling +12.5 for
successive approximation)
1/f
ADC
1. Based on characterization, not tested in production.
2. Guaranteed by design, not tested in production.
3. In devices delivered in VFQFPN and LQFP packages, V
REF+
is internally connected to V
DDA
and V
REF-
is internally
connected to V
SSA
. Devices that come in the TFBGA64 package have a V
REF+
pin but no V
REF-
pin (V
REF-
is internally
connected to V
SSA
), see Table 5 and Figure 6.
4. For external triggers, a delay of 1/f
PCLK2
must be added to the latency specified in Table 46.
Electrical characteristics STM32F103x8, STM32F103xB
74/99 Doc ID 13587 Rev 13
Equation 1: R
AIN
max formula:
The formula above (Equation 1) is used to determine the maximum external impedance allowed for an
error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Table 47. R
AIN
max for f
ADC
= 14 MHz
(1)
1. Based on characterization, not tested in production.
T
s
(cycles) t
S
(s) R
AIN
max (k)
1.5 0.11 0.4
7.5 0.54 5.9
13.5 0.96 11.4
28.5 2.04 25.2
41.5 2.96 37.2
55.5 3.96 50
71.5 5.11 NA
239.5 17.1 NA
Table 48. ADC accuracy - limited test conditions
(1)
(2)
1. ADC DC accuracy values are measured after internal calibration.
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-
robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for I
INJ(PIN)
and I
INJ(PIN)
in Section 5.3.12 does not
affect the ADC accuracy.
Symbol Parameter Test conditions Typ Max
(3)
3. Based on characterization, not tested in production.
Unit
ET Total unadjusted error
f
PCLK2
= 56 MHz,
f
ADC
= 14 MHz, R
AIN
< 10 k,
V
DDA
= 3 V to 3.6 V
T
A
= 25 C
Measurements made after
ADC calibration
1.3 2
LSB
EO Offset error 1 1.5
EG Gain error 0.5 1.5
ED Differential linearity error 0.7 1
EL Integral linearity error 0.8 1.5
R
AIN
T
S
f
ADC
C
ADC
2
N 2 +
( ) ln
-------------------------------------------------------------- R
ADC
<
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 13 75/99
Figure 36. ADC accuracy characteristics
Table 49. ADC accuracy
(1)
(2)
(3)
1. ADC DC accuracy values are measured after internal calibration.
2. Better performance could be achieved in restricted V
DD
, frequency and temperature ranges.
3. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-
robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for I
INJ(PIN)
and I
INJ(PIN)
in Section 5.3.12 does not
affect the ADC accuracy.
Symbol Parameter Test conditions Typ Max
(4)
4. Based on characterization, not tested in production.
Unit
ET Total unadjusted error
f
PCLK2
= 56 MHz,
f
ADC
= 14 MHz, R
AIN
< 10 k,
V
DDA
= 2.4 V to 3.6 V
Measurements made after
ADC calibration
2 5
LSB
EO Offset error 1.5 2.5
EG Gain error 1.5 3
ED Differential linearity error 1 2
EL Integral linearity error 1.5 3
E
O
E
G
1 LSB
IDEAL
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
E
T
=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
E
O
=Offset Error: deviation between the first actual
transition and the first ideal one.
E
G
=Gain Error: deviation between the last ideal
transition and the last actual one.
E
D
=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
E
L
=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
4095
4094
4093
5
4
3
2
1
0
7
6
1 2 3 4 5 6 7 4093 4094 4095 4096
(1)
(2)
E
T
E
D
E
L
(3)
V
DDA
V
SSA ai14395b
V
REF+
4096
(or depending on package)]
V
DDA
4096
[1LSB
IDEAL
=
Electrical characteristics STM32F103x8, STM32F103xB
76/99 Doc ID 13587 Rev 13
Figure 37. Typical connection diagram using the ADC
1. Refer to Table 46 for the values of R
AIN
, R
ADC
and C
ADC
.
2. C
parasitic
represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high C
parasitic
value will downgrade conversion accuracy. To remedy
this, f
ADC
should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 38 or Figure 39,
depending on whether V
REF+
is connected to V
DDA
or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 38. Power supply and reference decoupling (V
REF+
not connected to V
DDA
)
1. V
REF+
and V
REF
inputs are available only on 100-pin packages.
ai14150c
STM32F103xx
V
DD
AINx
I
L
1 A
0.6 V
V
T
R
AIN
(1)
C
parasitic
V
AIN
0.6 V
V
T
R
ADC
(1)
12-bit
converter
C
ADC
(1)
Sample and hold ADC
converter
V
REF+
(see note 1)
STM32F103xx
V
DDA
V
SSA
/V
REF
(see note 1)
1 F // 10 nF
1 F // 10 nF
ai14388b
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 13 77/99
Figure 39. Power supply and reference decoupling (V
REF+
connected to V
DDA
)
1. V
REF+
and V
REF
inputs are available only on 100-pin packages.
5.3.19 Temperature sensor characteristics
V
REF+
/V
DDA
STM32F103xx
1 F // 10 nF
V
REF
/V
SSA
ai14389
(See note 1)
(See note 1)
Table 50. TS characteristics
Symbol Parameter Min Typ Max Unit
T
L
(1)
1. Based on characterization, not tested in production.
V
SENSE
linearity with temperature 1 2 C
Avg_Slope
(1)
Average slope 4.0 4.3 4.6 mV/C
V
25
(1)
Voltage at 25 C 1.34 1.43 1.52 V
t
START
(2)
2. Guaranteed by design, not tested in production.
Startup time 4 10 s
T
S_temp
(3)(2)
3. Shortest sampling time can be determined in the application by multiple iterations.
ADC sampling time when reading the
temperature
17.1 s
Package characteristics STM32F103x8, STM32F103xB
78/99 Doc ID 13587 Rev 13
6 Package characteristics
6.1 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
is an ST trademark.
STM32F103x8, STM32F103xB Package characteristics
Doc ID 13587 Rev 13 79/99
1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead solder joint life.
Figure 40. VFQFPN36 6 x 6 mm, 0.5 mm pitch,
package outline
(1)
Figure 41. Recommended footprint
(dimensions in mm)
(1)(2)
Seating plane
ddd C
C
A3 A1
A A2
Pin # 1 ID
R = 0.20
ZR_ME
E2
b
1 9
10
18
27
28
36
19
D2
E
D
e
L
0.30
6.30
0.50
1.00 4.30
4.30
4.80
4.80
4.10
4.10
1
28
9
19
ai14870b
36
27
18
10
0.75
Table 51. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data
Symbol
millimeters inches
(1)
Min Typ Max Min Typ Max
A 0.800 0.900 1.000 0.0315 0.0354 0.0394
A1 0.020 0.050 0.0008 0.0020
A2 0.650 1.000 0.0256 0.0394
A3 0.250 0.0098
b 0.180 0.230 0.300 0.0071 0.0091 0.0118
D 5.875 6.000 6.125 0.2313 0.2362 0.2411
D2 1.750 3.700 4.250 0.0689 0.1457 0.1673
E 5.875 6.000 6.125 0.2313 0.2362 0.2411
E2 1.750 3.700 4.250 0.0689 0.1457 0.1673
e 0.450 0.500 0.550 0.0177 0.0197 0.0217
L 0.350 0.550 0.750 0.0138 0.0217 0.0295
ddd 0.080 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Package characteristics STM32F103x8, STM32F103xB
80/99 Doc ID 13587 Rev 13
1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead solder joint life.
Figure 42. VFQFPN48 7 x 7 mm, 0.5 mm pitch, package
outline
(1)
Figure 43. Recommended footprint
(dimensions in mm)
(1)(2)
Seating
Plane
C
A
3
A
1
A
2
A
d
d
d
C
Pin no. 1 ID
R = 0.20
Bottom View
1
48
e
E
L
L
12
13
D2
b
24
25
b
E
2
36
37
e
D
V0_ME
0.50
7.30
0.75
5.80
5.80
6.20
6.20
5.60
5.60
13
1
24
37
ai15799
12
48
36
25
0.55
0.30
0.20
Table 52. VFQFPN48 7 x 7 mm, 0.5 mm pitch, package mechanical data
Symbol
millimeters inches
(1)
Min Typ Max Min Typ Max
A 0.800 0.900 1.000 0.0315 0.0354 0.0394
A1 0.020 0.050 0.0008 0.0020
A2 0.650 1.000 0.0256 0.0394
A3 0.250 0.0098
b 0.180 0.230 0.300 0.0071 0.0091 0.0118
D 6.850 7.000 7.150 0.2697 0.2756 0.2815
D2 2.250 4.700 5.250 0.0886 0.1850 0.2067
E 6.850 7.000 7.150 0.2697 0.2756 0.2815
E2 2.250 4.700 5.250 0.0886 0.1850 0.2067
e 0.450 0.500 0.550 0.0177 0.0197 0.0217
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
ddd 0.080 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
STM32F103x8, STM32F103xB Package characteristics
Doc ID 13587 Rev 13 81/99
Figure 44. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package
outline
1. Drawing is not to scale.
Table 53. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package
mechanical data
Symbol
millimeters inches
(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A 1.700 0.0669
A1 0.270 0.0106
A2 1.085 0.0427
A3 0.30 0.0118
A4 0.80 0.0315
b 0.45 0.50 0.55 0.0177 0.0197 0.0217
D 9.85 10.00 10.15 0.3878 0.3937 0.3996
D1 7.20 0.2835
E 9.85 10.00 10.15 0.3878 0.3937 0.3996
E1 7.20 0.2835
e 0.80 0.0315
F 1.40 0.0551
ddd 0.12 0.0047
eee 0.15 0.0059
fff 0.08 0.0031
N (number of balls) 100
Package characteristics STM32F103x8, STM32F103xB
82/99 Doc ID 13587 Rev 13
Figure 45. Recommended PCB design rules (0.80/0.75 mm pitch BGA)
Dpad
Dsm
Dpad 0.37 mm
Dsm
0.52 mm typ. (depends on solder
mask registration tolerance
Solder paste 0.37 mm aperture diameter
Non solder mask defined pads are recommended
4 to 6 mils screen print
STM32F103x8, STM32F103xB Package characteristics
Doc ID 13587 Rev 13 83/99
Figure 46. LQFP100, 14 x 14 mm 100-pin low-profile
quad flat package outline
(1)
Figure 47. Recommended footprint
(1)(2)
1. Drawing is not to scale.
2. Dimensions are in millimeters.
D
D1
D3
75 51
50 76
100 26
1 25
E3 E1 E
e
b
Pin 1
identification
SEATING PLANE
GAGE PLANE
C
A
A2
A1
C ccc
0.25 mm
0.10 inch
L
L1
k
C
1L_ME
75 51
50 76
0.5
0.3
16.7 14.3
100 26
12.3
25
1.2
16.7
1
ai14906
Table 54. LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data
Symbol
millimeters inches
(1)
Min Typ Max Min Typ Max
A 1.6 0.063
A1 0.05 0.15 0.002 0.0059
A2 1.35 1.4 1.45 0.0531 0.0551 0.0571
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
c 0.09 0.2 0.0035 0.0079
D 15.8 16 16.2 0.622 0.6299 0.6378
D1 13.8 14 14.2 0.5433 0.5512 0.5591
D3 12 0.4724
E 15.8 16 16.2 0.622 0.6299 0.6378
E1 13.8 14 14.2 0.5433 0.5512 0.5591
E3 12 0.4724
e 0.5 0.0197
L 0.45 0.6 0.75 0.0177 0.0236 0.0295
L1 1 0.0394
k 0.0 3.5 7.0 0.0 3.5 7.0
ccc 0.08 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Package characteristics STM32F103x8, STM32F103xB
84/99 Doc ID 13587 Rev 13
Figure 48. LQFP64, 10 x 10 mm, 64-pin low-profile quad
flat package outline
(1)
Figure 49. Recommended
footprint
(1)(2)
1. Drawing is not to scale.
2. Dimensions are in millimeters.
A
A2
A1
c
L1
L
E E1
D
D1
e
b
ai14398b
48
32 49
64 17
1 16
1.2
0.3
33
10.3
12.7
10.3
0.5
7.8
12.7
ai14909
Table 55. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data
Symbol
millimeters inches
(1)
Min Typ Max Min Typ Max
A 1.60 0.0630
A1 0.05 0.15 0.0020 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
c 0.09 0.20 0.0035 0.0079
D 12.00 0.4724
D1 10.00 0.3937
E 12.00 0.4724
E1 10.00 0.3937
e 0.50 0.0197
0 3.5 7 0 3.5 7
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 0.0394
N
Number of pins
64
1. Values in inches are converted from mm and rounded to 4 decimal digits.
STM32F103x8, STM32F103xB Package characteristics
Doc ID 13587 Rev 13 85/99
Figure 50. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline
1. Drawing is not to scale.
Table 56. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package
mechanical data
Symbol
millimeters inches
(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A 1.200 0.0472
A1 0.150 0.0059
A2 0.785 0.0309
A3 0.200 0.0079
A4 0.600 0.0236
b 0.250 0.300 0.350 0.0098 0.0118 0.0138
D 4.850 5.000 5.150 0.1909 0.1969 0.2028
D1 3.500 0.1378
E 4.850 5.000 5.150 0.1909 0.1969 0.2028
E1 3.500 0.1378
e 0.500 0.0197
F 0.750 0.0295
ddd 0.080 0.0031
eee 0.150 0.0059
fff 0.050 0.0020
A3
A4
A2
A1
A
Seating
plane
B
A
D
D1
e
F
F
E1 E
e
H
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8
A1 ball pad corner b (64 balls)
Bottom view
C
ME_R8
Package characteristics STM32F103x8, STM32F103xB
86/99 Doc ID 13587 Rev 13
Figure 51. Recommended PCB design rules for pads (0.5 mm pitch BGA)
1. Non solder mask defined (NSMD) pads are recommended
2. 4 to 6 mils solder paste screen printing process
Pitch 0.5 mm
D pad 0.27 mm
Dsm 0.35 mm typ (depends on
the soldermask registration
tolerance)
Solder paste 0.27 mm aperture diameter
Dpad
Dsm
ai15495
STM32F103x8, STM32F103xB Package characteristics
Doc ID 13587 Rev 13 87/99
Figure 52. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat
package outline
(1)
Figure 53. Recommended
footprint
(1)(2)
1. Drawing is not to scale.
2. Dimensions are in millimeters.
D
D1
D3
A1
L1
L
k
c
b
ccc
C
A1
A2 A
C
Seating plane
0.25 mm
Gage plane
E3 E1 E
12
13
24
25
48
1
36
37
Pin 1
identification
5B_ME
9.70 5.80
7.30
12
24
0.20
7.30
1
37
36
1.20
5.80
9.70
0.30
25
1.20
0.50
ai14911b
13 48
Table 57. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package mechanical data
Symbol
millimeters inches
(1)
Min Typ Max Min Typ Max
A 1.600 0.0630
A1 0.050 0.150 0.0020 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 0.200 0.0035 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 5.500 0.2165
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 5.500 0.2165
e 0.500 0.0197
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 1.000 0.0394
k 0 3.5 7 0 3.5 7
ccc 0.080 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Package characteristics STM32F103x8, STM32F103xB
88/99 Doc ID 13587 Rev 13
6.2 Thermal characteristics
The maximum chip junction temperature (T
J
max) must never exceed the values given in
Table 9: General operating conditions on page 36.
The maximum chip-junction temperature, T
J
max, in degrees Celsius, may be calculated
using the following equation:
T
J
max = T
A
max + (P
D
max
JA
)
Where:
T
A
max is the maximum ambient temperature in C,
JA
is the package junction-to-ambient thermal resistance, in C/W,
P
D
max is the sum of P
INT
max and P
I/O
max (P
D
max = P
INT
max + P
I/O
max),
P
INT
max is the product of I
DD
and
V
DD
, expressed in Watts. This is the maximum chip
internal power.
P
I/O
max represents the maximum power dissipation on output pins where:
P
I/O
max = (V
OL
I
OL
) + ((V
DD
V
OH
) I
OH
),
taking into account the actual V
OL
/ I
OL
and V
OH
/ I
OH
of the I/Os at low and high level in the
application.
6.2.1 Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
Table 58. Package thermal characteristics
Symbol Parameter Value Unit
JA
Thermal resistance junction-ambient
LFBGA100 - 10 10 mm / 0.8 mm pitch
44
C/W
Thermal resistance junction-ambient
LQFP100 - 14 14 mm / 0.5 mm pitch
46
Thermal resistance junction-ambient
LQFP64 - 10 10 mm / 0.5 mm pitch
45
Thermal resistance junction-ambient
TFBGA64 - 5 5 mm / 0.5 mm pitch
65
Thermal resistance junction-ambient
LQFP48 - 7 x 7 mm / 0.5 mm pitch
55
Thermal resistance junction-ambient
VFQFPN 48 -7 7 mm / 0.5 mm pitch
16
Thermal resistance junction-ambient
VFQFPN 36 - 6 6 mm / 0.5 mm pitch
18
STM32F103x8, STM32F103xB Package characteristics
Doc ID 13587 Rev 13 89/99
6.2.2 Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Table 59: Ordering information scheme.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32F103xx at maximum dissipation, it is useful
to calculate the exact power consumption and junction temperature to determine which
temperature range will be best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
Example 1: High-performance application
Assuming the following application conditions:
Maximum ambient temperature T
Amax
= 82 C (measured according to JESD51-2),
I
DDmax
= 50 mA, V
DD
= 3.5 V, maximum 20 I/Os used at the same time in output at low
level with I
OL
= 8 mA, V
OL
= 0.4 V and maximum 8 I/Os used at the same time in output
at low level with I
OL
= 20 mA, V
OL
= 1.3 V
P
INTmax
=
50 mA 3.5 V= 175 mW
P
IOmax
=
20 8 mA 0.4 V + 8 20 mA 1.3 V = 272 mW
This gives: P
INTmax
= 175 mW and P
IOmax
= 272 mW:
P
Dmax
=
175
+
272 = 447 mW
Thus: P
Dmax
= 447 mW
Using the values obtained in Table 58 T
Jmax
is calculated as follows:
For LQFP100, 46 C/W
T
Jmax
= 82 C + (46 C/W 447 mW) = 82 C + 20.6 C = 102.6 C
This is within the range of the suffix 6 version parts (40 < T
J
< 105 C).
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Table 59: Ordering information scheme).
Example 2: High-temperature application
Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature T
J
remains within the
specified range.
Assuming the following application conditions:
Maximum ambient temperature T
Amax
= 115 C (measured according to JESD51-2),
I
DDmax
= 20 mA, V
DD
= 3.5 V, maximum 20 I/Os used at the same time in output at low
level with I
OL
= 8 mA, V
OL
= 0.4 V
P
INTmax
=
20 mA 3.5 V= 70 mW
P
IOmax
=
20 8 mA 0.4 V = 64 mW
This gives: P
INTmax
= 70 mW and P
IOmax
= 64 mW:
P
Dmax
=
70
+
64 = 134 mW
Thus: P
Dmax
= 134 mW
Package characteristics STM32F103x8, STM32F103xB
90/99 Doc ID 13587 Rev 13
Using the values obtained in Table 58 T
Jmax
is calculated as follows:
For LQFP100, 46 C/W
T
Jmax
= 115 C + (46 C/W 134 mW) = 115 C + 6.2 C = 121.2 C
This is within the range of the suffix 7 version parts (40 < T
J
< 125 C).
In this case, parts must be ordered at least with the temperature range suffix 7 (see
Table 59: Ordering information scheme).
Figure 54. LQFP100 P
D
max vs. T
A
0
100
200
300
400
500
600
700
65 75 85 95 105 115 125 135
T
A
(C)
P
D
(
m
W
)
Suffix 6
Suffix 7
STM32F103x8, STM32F103xB Ordering information scheme
Doc ID 13587 Rev 13 91/99
7 Ordering information scheme
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
Table 59. Ordering information scheme
Example: STM32 F 103 C 8 T 7 xxx
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = general-purpose
Device subfamily
103 = performance line
Pin count
T = 36 pins
C = 48 pins
R = 64 pins
V = 100 pins
Flash memory size
(1)
1. Although STM32F103x6 devices are not described in this datasheet, orderable part numbers that do not
show the A internal code after temperature range code 6 or 7 should be referred to this datasheet for the
electrical characteristics. The low-density datasheet only covers STM32F103x6 devices that feature the
A code.
8 = 64 Kbytes of Flash memory
B = 128 Kbytes of Flash memory
Package
H = BGA
T = LQFP
U = VFQFPN
Temperature range
6 = Industrial temperature range, 40 to 85 C.
7 = Industrial temperature range, 40 to 105 C.
Options
xxx = programmed parts
TR = tape and real
Revision history STM32F103x8, STM32F103xB
92/99 Doc ID 13587 Rev 13
8 Revision history
Table 60. Document revision history
Date Revision Changes
01-jun-2007 1 Initial release.
20-Jul-2007 2
Flash memory size modified in Note 8, Note 5, Note 7, Note 9 and
BGA100 pins added to Table 5: Medium-density STM32F103xx pin
definitions. Figure 3: STM32F103xx performance line LFBGA100
ballout added.
T
HSE
changed to T
LSE
in Figure 22: Low-speed external clock source
AC timing diagram. V
BAT
ranged modified in Power supply schemes.
t
SU(LSE)
changed to t
SU(HSE)
in Table 22: HSE 4-16 MHz oscillator
characteristics. I
DD(HSI)
max value added to Table 24: HSI oscillator
characteristics.
Sample size modified and machine model removed in Electrostatic
discharge (ESD).
Number of parts modified and standard reference updated in Static
latch-up. 25 C and 85 C conditions removed and class name modified
in Table 33: Electrical sensitivities. R
PU
and R
PD
min and max values
added to Table 35: I/O static characteristics. R
PU
min and max values
added to Table 38: NRST pin characteristics.
Figure 31: I2C bus AC waveforms and measurement circuit and
Figure 30: Recommended NRST pin protection corrected.
Notes removed below Table 9, Table 38, Table 44.
I
DD
typical values changed in Table 11: Maximum current consumption
in Run and Sleep modes. Table 39: TIMx characteristics modified.
t
STAB
, V
REF+
value, t
lat
and f
TRIG
added to Table 46: ADC
characteristics.
In Table 29: Flash memory endurance and data retention, typical
endurance and data retention for T
A
= 85 C added, data retention for
T
A
= 25 C removed.
V
BG
changed to V
REFINT
in Table 12: Embedded internal reference
voltage. Document title changed. Controller area network (CAN)
section modified.
Figure 13: Power supply scheme modified.
Features on page 1 list optimized. Small text changes.
STM32F103x8, STM32F103xB Revision history
Doc ID 13587 Rev 13 93/99
18-Oct-2007 3
STM32F103CBT6, STM32F103T6 and STM32F103T8 root part
numbers added (see Table 2: STM32F103xx medium-density device
features and peripheral counts)
VFQFPN36 package added (see Section 6: Package characteristics).
All packages are ECOPACK compliant. Package mechanical data
inch values are calculated from mm and rounded to 4 decimal digits
(see Section 6: Package characteristics).
Table 5: Medium-density STM32F103xx pin definitions updated and
clarified.
Table 26: Low-power mode wakeup timings updated.
T
A
min corrected in Table 12: Embedded internal reference voltage.
Note 2 added below Table 22: HSE 4-16 MHz oscillator characteristics.
V
ESD(CDM)
value added to Table 32: ESD absolute maximum ratings.
Note 4 added and V
OH
parameter description modified in Table 36:
Output voltage characteristics.
Note 1 modified under Table 37: I/O AC characteristics.
Equation 1 and Table 47: RAIN max for fADC = 14 MHz added to
Section 5.3.18: 12-bit ADC characteristics.
V
AIN
, t
S
max, t
CONV
, V
REF+
min and t
lat
max modified, notes modified
and t
latr
added in Table 46: ADC characteristics.
Figure 36: ADC accuracy characteristics updated. Note 1 modified
below Figure 37: Typical connection diagram using the ADC.
Electrostatic discharge (ESD) on page 58 modified.
Number of TIM4 channels modified in Figure 1: STM32F103xx
performance line block diagram.
Maximum current consumption Table 13, Table 14 and Table 15
updated. V
hys
modified in Table 35: I/O static characteristics.
Table 49: ADC accuracy updated. t
VDD
modified in Table 10: Operating
conditions at power-up / power-down. V
FESD
value added in Table 30:
EMS characteristics.
Values corrected, note 2 modified and note 3 removed in Table 26:
Low-power mode wakeup timings.
Table 16: Typical and maximum current consumptions in Stop and
Standby modes: Typical values added for V
DD
/V
BAT
= 2.4 V, Note 2
modified, Note 2 added.
Table 21: Typical current consumption in Standby mode added. On-chip
peripheral current consumption on page 48 added.
ACC
HSI
values updated in Table 24: HSI oscillator characteristics.
V
prog
added to Table 28: Flash memory characteristics.
Upper option byte address modified in Figure 10: Memory map.
Typical f
LSI
value added in Table 25: LSI oscillator characteristics and
internal RC value corrected from 32 to 40 kHz in entire document.
T
S_temp
added to Table 50: TS characteristics. N
END
modified in
Table 29: Flash memory endurance and data retention.
T
S_vrefint
added to Table 12: Embedded internal reference voltage.
Handling of unused pins specified in General input/output
characteristics on page 60. All I/Os are CMOS and TTL compliant.
Figure 38: Power supply and reference decoupling (VREF+ not
connected to VDDA) modified.
t
JITTER
and f
VCO
removed from Table 27: PLL characteristics.
Appendix A: Important notes on page 81 added.
Added Figure 15, Figure 16, Figure 18 and Figure 20.
Table 60. Document revision history (continued)
Date Revision Changes
Revision history STM32F103x8, STM32F103xB
94/99 Doc ID 13587 Rev 13
22-Nov-2007 4
Document status promoted from preliminary data to datasheet.
The STM32F103xx is USB certified. Small text changes.
Power supply schemes on page 15 modified. Number of
communication peripherals corrected for STM32F103Tx and number of
GPIOs corrected for LQFP package in Table 2: STM32F103xx medium-
density device features and peripheral counts.
Main function and default alternate function modified for PC14 and
PC15 in, Note 6 added and Remap column added in Table 5: Medium-
density STM32F103xx pin definitions.
V
DD
V
SS
ratings and Note 1 modified in Table 6: Voltage
characteristics, Note 1
modified in Table 7: Current characteristics.
Note 1 and Note 2 added in Table 11: Embedded reset and power
control block characteristics.
I
DD
value at 72 MHz with peripherals enabled modified in Table 14:
Maximum current consumption in Run mode, code with data
processing running from RAM.
I
DD
value at 72 MHz with peripherals enabled modified in Table 15:
Maximum current consumption in Sleep mode, code running from
Flash or RAM on page 42.
I
DD_VBAT
typical value at 2.4 V modified and I
DD_VBAT
maximum values
added in Table 16: Typical and maximum current consumptions in Stop
and Standby modes. Note added in Table 17 on page 46 and Table 18
on page 47. ADC1 and ADC2 consumption and notes modified in
Table 19: Peripheral current consumption.
t
SU(HSE)
and t
SU(LSE)
conditions modified in Table 22 and Table 23,
respectively.
Maximum values removed from Table 26: Low-power mode wakeup
timings. t
RET
conditions modified in Table 29: Flash memory endurance
and data retention. Figure 13: Power supply scheme corrected.
Figure 19: Typical current consumption in Stop mode with regulator in
Low-power mode versus temperature at VDD = 3.3 V and 3.6 V added.
Note removed below Figure 32: SPI timing diagram - slave mode and
CPHA = 0. Note added below Figure 33: SPI timing diagram - slave
mode and CPHA = 1(1).
Details on unused pins removed from General input/output
characteristics on page 60.
Table 42: SPI characteristics updated. Table 43: USB startup time
added. V
AIN
, t
lat and
t
latr
modified, note added and I
lkg
removed in
Table 46: ADC characteristics. Test conditions modified and note added
in Table 49: ADC accuracy. Note added below Table 47 and Table 50.
Inch values corrected in Table 54: LQPF100, 14 x 14 mm 100-pin low-
profile quad flat package mechanical data, Table 55: LQFP64, 10 x 10
mm, 64-pin low-profile quad flat package mechanical data and
Table 57: LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package
mechanical data.
JA
value for VFQFPN36 package added in Table 58: Package thermal
characteristics.
Order codes replaced by Section 7: Ordering information scheme.
MCU s operating conditions modified in Typical current consumption
on page 45. Avg_Slope and V
25
modified in Table 50: TS
characteristics. I2C interface characteristics on page 67 modified.
Impedance size specified in A.4: Voltage glitch on ADC input 0 on
page 81.
Table 60. Document revision history (continued)
Date Revision Changes
STM32F103x8, STM32F103xB Revision history
Doc ID 13587 Rev 13 95/99
14-Mar-2008 5
Figure 2: Clock tree on page 12 added.
Maximum T
J
value given in Table 8: Thermal characteristics on
page 36.
CRC feature added (see CRC (cyclic redundancy check) calculation
unit on page 9 and Figure 10: Memory map on page 32 for address).
I
DD
modified in Table 16: Typical and maximum current consumptions in
Stop and Standby modes.
ACC
HSI
modified in Table 24: HSI oscillator characteristics on page 53,
note 2 removed.
P
D
, T
A
and T
J
added, t
prog
values modified and t
prog
description clarified
in Table 28: Flash memory characteristics on page 55.
t
RET
modified in Table 29: Flash memory endurance and data retention.
V
NF(NRST)
unit corrected in Table 38: NRST pin characteristics on
page 65.
Table 42: SPI characteristics on page 69 modified.
I
VREF
added to Table 46: ADC characteristics on page 73.
Table 48: ADC accuracy - limited test conditions added. Table 49: ADC
accuracy modified.
LQFP100 package specifications updated (see Section 6: Package
characteristics on page 78).
Recommended LQFP100, LQFP 64, LQFP48 and VFQFPN36
footprints added (see Figure 47, Figure 49, Figure 53 and Figure 41).
Section 6.2: Thermal characteristics on page 88 modified,
Section 6.2.1 and Section 6.2.2 added.
Appendix A: Important notes on page 81 removed.
21-Mar-2008 6
Small text changes. Figure 10: Memory map clarified.
In Table 29: Flash memory endurance and data retention:
N
END
tested over the whole temperature range
cycling conditions specified for t
RET
t
RET
min modified at T
A
= 55 C
V
25
, Avg_Slope and T
L
modified in Table 50: TS characteristics.
CRC feature removed.
22-May-2008 7
CRC feature added back. Small text changes. Section 1: Introduction
modified. Section 2.2: Full compatibility throughout the family added.
I
DD
at T
A
max = 105 C added to Table 16: Typical and maximum
current consumptions in Stop and Standby modes on page 43.
I
DD_VBAT
removed from Table 21: Typical current consumption in
Standby mode on page 47.
Values added to Table 41: SCL frequency (fPCLK1= 36 MHz.,VDD =
3.3 V) on page 68.
Figure 32: SPI timing diagram - slave mode and CPHA = 0 on page 70
modified. Equation 1 corrected.
t
RET
at T
A
= 105 C modified in Table 29: Flash memory endurance and
data retention on page 56.
V
USB
added to Table 44: USB DC electrical characteristics on page 72.
Figure 54: LQFP100 PD max vs. TA on page 90 modified.
Axx option added to Table 59: Ordering information scheme on
page 91.
Table 60. Document revision history (continued)
Date Revision Changes
Revision history STM32F103x8, STM32F103xB
96/99 Doc ID 13587 Rev 13
21-Jul-2008 8
Power supply supervisor updated and V
DDA
added to Table 9: General
operating conditions.
Capacitance modified in Figure 13: Power supply scheme on page 34.
Table notes revised in Section 5: Electrical characteristics.
Table 16: Typical and maximum current consumptions in Stop and
Standby modes modified.
Data added to Table 16: Typical and maximum current consumptions in
Stop and Standby modes and Table 21: Typical current consumption in
Standby mode removed.
f
HSE_ext
modified in Table 20: High-speed external user clock
characteristics on page 49. f
PLL_IN
modified in Table 27: PLL
characteristics on page 55.
Minimum SDA and SCL fall time value for Fast mode removed from
Table 40: I2C characteristics on page 67, note 1 modified.
t
h(NSS)
modified in Table 42: SPI characteristics on page 69 and
Figure 32: SPI timing diagram - slave mode and CPHA = 0 on page 70.
C
ADC
modified in Table 46: ADC characteristics on page 73 and
Figure 37: Typical connection diagram using the ADC modified.
Typical T
S_temp
value removed from Table 50: TS characteristics on
page 77.
LQFP48 package specifications updated (see Table 57 and Table 53),
Section 6: Package characteristics revised.
Axx option removed from Table 59: Ordering information scheme on
page 91.
Small text changes.
22-Sep-2008 9
STM32F103x6 part numbers removed (see Table 59: Ordering
information scheme). Small text changes.
General-purpose timers (TIMx) and Advanced-control timer (TIM1) on
page 18 updated.
Notes updated in Table 5: Medium-density STM32F103xx pin
definitions on page 27.
Note 2 modified below Table 6: Voltage characteristics on page 35,
|V
DDx
| min and |V
DDx
| min removed.
Measurement conditions specified in Section 5.3.5: Supply current
characteristics on page 39.
I
DD
in standby mode at 85 C modified in Table 16: Typical and
maximum current consumptions in Stop and Standby modes on
page 43.
General input/output characteristics on page 60 modified.
f
HCLK
conditions modified in Table 30: EMS characteristics on page 57.
JA
and pitch value modified for LFBGA100 package in Table 58:
Package thermal characteristics. Small text changes.
Table 60. Document revision history (continued)
Date Revision Changes
STM32F103x8, STM32F103xB Revision history
Doc ID 13587 Rev 13 97/99
23-Apr-2009 10
I/O information clarified on page 1.
Figure 3: STM32F103xx performance line LFBGA100 ballout modified.
Figure 10: Memory map modified. Table 4: Timer feature comparison
added.
PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default
column to Remap column in Table 5: Medium-density STM32F103xx
pin definitions.
P
D
for LFBGA100 corrected in Table 9: General operating conditions.
Note modified in Table 13: Maximum current consumption in Run
mode, code with data processing running from Flash and Table 15:
Maximum current consumption in Sleep mode, code running from
Flash or RAM.
Table 20: High-speed external user clock characteristics and Table 21:
Low-speed external user clock characteristics modified.
Figure 19 shows a typical curve (title modified). ACC
HSI
max values
modified in Table 24: HSI oscillator characteristics.
TFBGA64 package added (see Table 56 and Table 50). Small text
changes.
22-Sep-2009 11
Note 5 updated and Note 4 added in Table 5: Medium-density
STM32F103xx pin definitions.
V
RERINT
and T
Coeff
added to Table 12: Embedded internal reference
voltage. I
DD_VBAT
value added to Table 16: Typical and maximum
current consumptions in Stop and Standby modes. Figure 17: Typical
current consumption on VBAT with RTC on versus temperature at
different VBAT values added.
f
HSE_ext
min modified in Table 20: High-speed external user clock
characteristics.
C
L1
and C
L2
replaced by C in Table 22: HSE 4-16 MHz oscillator
characteristics and Table 23: LSE oscillator characteristics (fLSE =
32.768 kHz), notes modified and moved below the tables. Table 24: HSI
oscillator characteristics modified. Conditions removed from Table 26:
Low-power mode wakeup timings.
Note 1 modified below Figure 23: Typical application with an 8 MHz
crystal.
IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to
IEC 61967-2 in Section 5.3.10: EMC characteristics on page 56.
Jitter added to Table 27: PLL characteristics.
Table 42: SPI characteristics modified.
C
ADC
and R
AIN
parameters modified in Table 46: ADC characteristics.
R
AIN
max values modified in Table 47: RAIN max for fADC = 14 MHz.
Figure 44: LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array
package outline updated.
03-Jun-2010 12
Added STM32F103TB devices.
Added VFQFPN48 package.
Updated note 2 below Table 40: I2C characteristics
Updated Figure 31: I2C bus AC waveforms and measurement circuit
Updated Figure 30: Recommended NRST pin protection
Updated Section 5.3.12: I/O current injection characteristics
Table 60. Document revision history (continued)
Date Revision Changes
Revision history STM32F103x8, STM32F103xB
98/99 Doc ID 13587 Rev 13
19-Apr-2011 13
Updated footnotes below Table 6: Voltage characteristics on page 35
and Table 7: Current characteristics on page 36
Updated tw min in Table 20: High-speed external user clock
characteristics on page 49
Updated startup time in Table 23: LSE oscillator characteristics (fLSE =
32.768 kHz) on page 52
Added Section 5.3.12: I/O current injection characteristics
Updated Section 5.3.13: I/O port characteristics
Table 60. Document revision history (continued)
Date Revision Changes
STM32F103x8, STM32F103xB
Doc ID 13587 Rev 13 99/99
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