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Basic Processing Unit

This document discusses the internal components and processes of a CPU. It describes how a CPU fetches and executes instructions through three main phases: 1) fetching the instruction from memory, 2) decoding and loading operands, and 3) executing the instruction. The key components that work together are the program counter, memory, registers, and arithmetic logic unit. Buses are used to transfer data between these components. The document also explains single and multiple bus organizations and how different instructions are executed through sequences of transferring data between components.

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lingga tanu
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© Attribution Non-Commercial (BY-NC)
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Download as PPT, PDF, TXT or read online on Scribd
184 views

Basic Processing Unit

This document discusses the internal components and processes of a CPU. It describes how a CPU fetches and executes instructions through three main phases: 1) fetching the instruction from memory, 2) decoding and loading operands, and 3) executing the instruction. The key components that work together are the program counter, memory, registers, and arithmetic logic unit. Buses are used to transfer data between these components. The document also explains single and multiple bus organizations and how different instructions are executed through sequences of transferring data between components.

Uploaded by

lingga tanu
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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CHAPTER 7

Learn about : Sub chapter :


 How a processor  Some fundamental

executes instructions concepts


 The internal functional  Execution of a complete

units of a processor and instruction


how they are  Multiple bus
interconected organization
 Hardware for generating  Hardwire control
internal control signals  Microprogrammed
 The microprogramming
control
approach
 Microprogram

oraganization
 Execution of one instruction requires the following
three steps to be performed by the CPU:
2. Fetch the contents of the memory location pointed
at by the PC. The contents of this location are
intepreted as an instruction to be executed. Hence,
they are stored in the instruction register (IR).
Simbolically, this can be written as:
IR [[PC]]
4. Assuming that the memory is byte addressable,
increment the contents of the PC by 4, that is
PC  [PC] + 4
6. Carry out the actions specified by the instruction
stored in the IR
 But, in cases where an instruction occupies
more than one word, steps 1 and 2 must be
repeated as many times as necessary to
fetch the complete instruction.
 Two first steps are ussually referred to as

the fetch phase.


 Step 3 constitutes the execution phase
SINGLE BUS ORGANIZATION OF THE DATAPATH
INSIDE A PROCESSOR
 Fetch the contents of a given memory
location and load them into a CPU
register
 Store a word of data from a CPU register

into a given memory location.


 Transfer a word of data from one CPU

register to another or to ALU.


 Perform an arithmetic or logic operation,

and store the result in a CPU register.


 The input and output gates for register Ri are
controlled by the signals Ri and Riout,
in
respectively.
 Thus, when Riin is set to 1, the data available
on the common bus is loaded into Ri.
 Similarly, when Riout is set to 1, the contents
of register Ri are placed on the bus.
 While Riout is equal to 0, the bus can be used
for transferring data from other registers.
 Enable the output gate of register R1 by
setting R1out to 1. This places the
contents of R1 on the CPU bus.
 Enable the input gate of register R4 by
setting R4in to 1. This loads data from
the CPU bus into register R4.
 This data transfer can be represented
symbolically as R1out, R4in
 A SEQUENCE OF OPERATIONS TO ADD THE
CONTENTS OF REGISTER R1 TO THOSE OF
REGISTER R2 AND STORE THE RESULT IN
REGISTER R3 IS:
 R1out, Yin
 R2out, Select Y, Add, Zin
 Zout, R3in
Riin

Ri

X
Riout

Yin
Input and output X
Constant 4
gating for the Y

registers select
Mux

A B

ALU

Zin
X

Zout
Connection and
control signals
for register
MDR
 CPU transfers the address of the required information word to the memory
address register (MAR). Address of the required word is transferred to the
main memory.
 Meanwhile, the CPU uses the control lines of the memory bus to indicate that
a read operation is required.
 After issuing this request, the CPU waits until it receives an answer from the
memory, informing it that the requested function has been completed. This is
accomplished through the use of another control signal on the memory bus,
which will be referred to as Memory Function Completed (MFC).
 The memory sets this signal to 1 to indicate that the contents of the
specified location in the memory have been read and are available on the data
lines of the memory bus.
 We will assume that as soon as the MFC signal is set to 1, the information on
the data lines is loaded into MDR and is thus available for use inside the CPU.
This completes the memory fetch operation.
 MAR  [R1]
 Start Read operation on the memory bus
 Wait for the MFC response from the
memory
 Load MDR from the memory bus
 R2  [MDR]
R1out, MARin, Read
MDRinE, WMFC
MDRout, R2in
 That is similar procedure with fetching a word
from memory.
 The desired address is loaded into MAR
 Then data to be written are loaded into MDR, and
a write command is issued.
 If we assume that the data word to be stored
in the memory is in R2 and that the memory
address is in R1, the Write operation requires
the following sequence :
 MAR  [R1]
 MDR [R2]
 Write
 Wait for the MFC
R1out, MARin
R2out, MDRin. Write
MDRoutE, WMFC
 Consider the instruction :
Add (R3), R1
 Executing this instruction requires the
following actions :
1. Fetch the instruction
2. Fetch the first operand (the contents of the
memory location pointed to by R3)
3. Perform the addition
4. Load the result into R1
 PCout, MARin, Read, Select4, Add, Zin
 Zout, PCin, Yin, Wait for the MFC
 MDRout, IRin
 R3out, MARin, Read
 R1out, Yin, Wait for MFC
 MDRout, Select Y, Add, Zin
 Zout, R1in, End
 PCout, MARin, Read, Select4, Add, Zin
 Zout, PCin, Yin, Wait for the MFC (WFMC)
 MDRout, Irin
 offset_field_of_IRout, Add, Zin
 Zout, PCin, End
Three bus
organization of the
datapath
 PCout, R=B, MARin, Read, IncPC
 WFMC
 MDRoutB, R=B, IRin
 R4out, R5outB, SelectA, Add, R6in, End.

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