DSP Processor vs General

Purpose Processor

BY:
AKSHITA CHAWDHARY
(C008)
ANKIT MAHESHWARI (C022)
PARTH PANCHAL (C024)

Definitions
MicroprocessorsGeneral-Purpose Processors (GPPs)
CPUs for PCs and workstations
E.g., Intel Pentium III
32-bit GPPs for embedded applications

E.g., ARM ARM7

Digital Signal Processors (DSPs)

Microprocessors specialized for signal processing applications
Low-end DSPs and GPPs
Architectures targeting extremely cost sensitive markets, often
older architectures

High Performance DSPs and GPPs

Architectures that use advanced techniques to improve
parallelism, performance
Usually have higher clock rates

DSP Algorithms Shape DSPs

Very computationally demanding
Requires attention to numeric fidelity
High memory bandwidth requirements
Streaming dataand lots of it
Predictable data access patterns
Execution-time locality
Math-centric
Real-time constraints
Standards: algorithms, interfaces

DSP Algorithms Shape DSPs

Computational
demands

Multiple parallel execution

units, hardware acceleration of
common DSP functions

Numeric fidelity
High memory
bandwidth

With the help of accumulator,

registers
Harvard architecture, support
for parallel moves

Predictable
data access
patterns

Specialized addressing modes,

e.g., modulo, bit-reversed

DSP Algorithms Shape DSPs

Execution-time locality

Streamlined
interrupt handling

Math-centricity

Single-cycle multiplier(s) or

Streaming data

Data memory usually

SRAM, not

MAC unit(s), MAC

instruction

cache; DMA
Standards

16-bit data types; rounding

Key Processor Attributes

Program
Control

Data
Path

Memory
MemorySystem
System

Peripherals

Development
Infrastructure

Address
Generatio
n

Comparing DSPs and GPPs

Instruction Set
Low-end DSP

Low-end GPP

Specialized, complex
instructions

General-purpose
instructions

Multiple operations per

instruction

Typically only one

operation per instruction

mac x0,y0,a x:(r0)+,x0

y:(r4)+,y0

mpy r2,r3,r4
add r4,r5,r5
mov (r0),r2
mov (r1),r3
inc r0
inc r1

Comparing DSPs and GPPs

Architecture Type
Low-end DSP and GPP

High-Performance DSP and

GPP

DSP
Compound instructions
perform multiple operations,
e.g., multiply + load +
modify address register
Examples: C54x, C24x,
C28x

DSPs
Typically VLIW
Up to 8 instructions/cycle
Examples: C64x, SC140,
TigerSHARC

RISC instructions perform

single operation, e.g., add,
load, or store
Examples: ARM7, ARM9

Typically superscalar
Up to 4 instructions/cycle
Example: PowerPC 74xx

Comparing DSPs and GPPs

Trade-Offs: Superscalar vs. VLIW
Superscalar (high-performance GPPs, mostly)

Increased hardware complexity

Silicon area, power consumption
Dynamic behaviour
Complex performance model, timing variability
Decreased software complexity (programmer/compiler)
VLIW (high-performance DSPs, mostly)
Decreased hardware complexity

No dynamic behaviour
Increased software complexity

Comparing DSPs and GPPs

Program Control
Low-end DSP

Low-end GPP

Interrupts disabled during

certain operations

Interrupts rarely disabled

Simple pipelines
Often provide delay slots to
hide branch latencies

Simple pipelines
No delay slots or branch
prediction

Key Processor Attributes

Program
Control

Data
Path

Memory System

Peripherals

Development
Infrastructure

Address
Generation

Comparing DSPs and GPPs

Low-end DSP

Low-end GPP

Dedicated hardware
performs all key arithmetic
operations in 1 cycle

Multiplies often take

>1 cycle
Multi-bit shifts often take
>1 cycle

Usually 16-bit

Usually 32-bit, integer only

Hardware support for

managing numeric fidelity
Limited bit-manipulation
capabilities

Saturation, rounding
typically take extra cycles
Saturation, rounding
typically take extra cycles

SIMD

Single Instruction, Multiple Data

Performs the same operation simultaneously on multiple sets of operands

Under the control of a single instruction
Some SIMD processors support multiple data widths (for example, 32-bit, 16-bit, and 8-bit)

SIMD Challenges

Example: Viterbi Add-Compare-Select (ACS) Loop

Comparing DSPs and GPPs

Addressing
DSP

GPP

Dedicated addressgeneration units

Often, no separate addressgeneration units

Specialized addressing
modes
Autoincerement
Modulo (circular)

General-purpose addressing
modes

Key Processor Attributes

Program
Control

Data
Path

Memory System

Peripherals

Development
Infrastructure

Address
Generation

Comparing DSPs and GPPs

Memory Architecture
Low-end DSP

Low-end GPP

Harvard architecture

Von Neumann architecture

2-4 memory accesses per cycle

Typically 1 access per cycle

No caches; on-chip SRAM DMA

Typically use cache(s)

Comparing DSPs and GPPs

Memory Architecture
High-Performance DSP

High-Performance GPP

Harvard architecture

Harvard architecture

Per cycle accesses:

1-8 instructions
two or more 16- to 64-bit data
words

Per cycle accesses:

1-4 instructions
~two 32- to 64-bit or one 128- bit
data word

Sometimes caches, often

lockable, configurable as SRAM
DMA

Usually use cache

Comparing DSPs and GPPs

Caches: Challenges

Caches work by lowering average access time

They are effective at doing this in many applications

But access times vary significantly

Some applications are sensitive to maximum access time (not

average)

E.g., many hard-real-time signal processing applications

Signal processing access patterns often predictable

Thus, DMA may be preferable to a cache

Some recent caches provide pre-fetching capability

Some DSPs caches can be locked or configured as part cache,

part SRAM

Comparing DSPs and GPPs

Dynamic Features

Dynamic features are used heavily in high-end GPPs to boost

performance

Superscalar execution

Caches

Branch prediction

Data-dependent instruction execution times

These features are occasionally used in DSPs, too

These features complicate software development for real-time DSP
applications

Ensuring real-time Behaviour

Optimizing code

Comparing DSPs and GPPs

Dynamic Features
Low-end GPPs and DSPs

High-Performance GPPs and DSPs

GPPs:
Dynamic caches common

GPPs: Moderate to extensive use

of dynamic features
Dynamic caches standard
Superscalar execution, branch
prediction common

DSPs:
Rarely have dynamic features
Small loop buffer instruction
cache exception

DSPs: Generally avoid dynamic

features
Dynamic cache is most
common dynamic feature
Superscalar execution rare
Branch prediction sometimes
used

Parallelism

Key implications of differences

Cycle efficiency

DSPs have advantage on signal processing tasks

But may require special software development strategieslike assembly level

programmingto realize full advantage

Memory use efficiency

Multi-operation instructions give DSPs advantage on signal processing tasks

But GPPs often better on non-signal processing taskswhich typically

consumes most of the code space

Compiler friendliness

GPPs generally have the advantage

SIMD difficult for compilers, whether GPP or DSP

Often requires assembly programming or use of high level intrinsicsboth of which

complicate software development

Comparing DSPs and GPPs

On-Chip Integration
Low-end GPPs and DSPs

High-Performance GPPs and DSPs

Typically, wide range of on-chip

peripherals and I/O interfaces

Moderate to extensive on- chip

integration
PC CPUs offer very little on-chip
integration

Often oriented towards consumer

applications
E.g., video coprocessors, USB
ports,

Often oriented towards

communications infrastructure
E.g., Viterbi decoding
coprocessors, UTOPIA ports,

Comparing DSPs and GPPs

Compatibility and Availability

Low-end DSP

Low-end GPP

Mostly proprietary architectures

I.e., one architecture, one
vendor

Many shared architectures

I.e., one architecture, several
(to many) vendors

Limited (at best) compatibility

between successive generations

Often binary compatibility

between successive generations

Occasionally available as
licensable core

Often available as licensable

core
E.g., ARM, MIPS

Comparing DSPs and GPPs

Compatibility and Availability

High-Performance DSP

High-Performance GPP

Mostly proprietary architectures

Exceptions: StarCore, ZSP

Mostly shared architectures

PowerPC, MIPS, ARM, x86

Sometimes binary compatibility

between successive generations
E.g., C6xxx, StarCore, ZSP

Usually binary compatibility

between successive generations

between successive generations

Core
E.g., StarCore, CEVA-X, ZSP

Sometimes available as licensable

core
E.g., ARM, MIPS

Comparing DSPs and GPPs

Development Support
DSPs

GPPs

Tools

Primitive to moderately
sophisticated

Primitive to very
sophisticated

DSP-specific tool support

Good to excellent
E.g., cycle-accurate
simulators, DSP C
extensions

Poor but improving

E.g., general lack of cycleaccurate simulators

3rd-party DSP software

support

Poor to excellent

Limited but growing

Non-DSP 3rd-party
software support

Poor
Few to moderate RTOS
options

Extensive
Few to extensive RTOS
options

Links w/other high-level

tools

E.g., MATLAB

E.g., GUI builders