Presentation 1

8088 Hardware Specifications
Two modes: MN/MX

- 1: min (work with 8-bit peripherals)
- 0: max (if a coprocessor exists)
Power supply:
- +5V with tolerance of 10%
Pins are divided into three separate buses:
- Address (output)
- Data (input/output)
- Control(input/output)
Address/Data bus:
AD7-AD0 (8088) or AD15-AD0 (8086).
These lines are multiplexed address and data.

Address bus:
A15-A8 (8088).
These are address lines only.

Address/Control (status) bus:
A19/S6 A16/S3.
These lines are multiplexed address and status.

S6 is always logic 0, S5 indicates condition of the IF
flag bits, S4 and S3 indicate which segment is being
accessed during the current bus cycle.
Control bus:
RD
When asserted it indicates a read operation is happening.
READY
When READY is logic 0 the microprocessor inserts wait
states into the timing of the processor.
INTR
Used for peripherals to request a hardware interrupt.
TEST
This pin is tested by the WAIT instruction, if asserted WAIT
behaves as a NOP, otherwise the WAIT instruction waits for
TEST to become logic 0.
NMI
Similar to INTR except it cannot be masked.
Control Bus (cont)

RESET
Causes the processor to reset itself.

CLK
Clock input to the precessor.

Vcc
Power supply connection, 5.0V, 10%.

GND
Power supply connection. Note that both ground pins must be

connected for proper operation.
MN/MX
Selects minimum or maximum mode of operation.

BHE/S7
Bus high enable is used in the 8086 to enable the most significant data
bus during a read or write operation. S7 is always logic 1.
Minimum Mode:
IO/M(8088)
Indicates if the processor is accessing a memory address or
an I/O port address.
WR
When asserted it indicates a write operation is happening.
INTA
Signal a response to an interrupt request.
ALE
Indicates that the address/data bus contains address
information.
DT/R
Data transmit/receive indicates that the data bus is transmitting
or receiving information.
Minimum Mode(cont):
DEN
Data bus enable activates the external data bus buffer.

HOLD
This input receives DMA - direct memory access requests.

HLDA
When asserted this pin acknowledges that the processor entered a

hold state.
SS0
Equivalent to S0 pin in maximum mode.
Maximum Mode:
S2,S1 and S0
These status bits indicate the function of the current bus cycle.
RO/GT1 and RO/GT0
Request/grant pins used for DMA during maximum mode

operation.
Minimum VS Maximum Mode

Minimum mode is the least expensive way to
operate a 8088 system.
Control signals are generated by processor.
Good backward compatibility with earlier 8085A 8 bit
processor.
Maximum mode provides greater versatility at a

higher cost.
Control signals are generated by external controllers.
Can be used with the 8087 math coprocessor.
Can be used with multiprocessor systems.
Data Move Instructions in

Microprocessor 8088
These instructions are used to transfer
data from source to destination.
The operand can be a constant, memory

location, register or I/O port address.
Data Movement Instructions

MOV
MOV Des, Src
Src operand can be register, memory location or
immediate operand.
Des can be register or memory operand.
Both Src and Des cannot be memory location at
the same time.
Example:
MOV CX, 037AH
MOV AL, BL

PUSH and POP
Both PUSH and POP instuctions are important to
store and retrieve data from the LIFO structure
(stack).
PUSH src
In 8088, PUSH always transfer 2 bytes of data to
the stack.
Src could be any 2 byte register or memory
location or immediate value.
Example:
PUSH BX
POP Des
It pops the operand from top of stack to Des.
removes data from stack and place it into
target 16-bit register.
Example:
POP AX

Load-Effective Address - LEA
LEA Register, Src
It loads a 16-bit register with the offset
address of the data specified by the Src.
Example:
LEA BX, [DI]; loads offset address
specified by [DI]
(contents of DI) into BX
register

LDS
LDS Des,Src
It loads 32-bit pointer from memory source to
destination register and DS.
The offset is placed in the destination register and the
segment is placed in DS.
To use this instruction the word at the lower memory
address must contain the offset and the memory
address must contain the offset and the Word at the
higher address must contain the segment.
Example:
LDS BX, [DI]

LES
LES Des,Src
It loads 32-bit pointer from memory source to
destination register and ES.
The offset is placed in the destination register
and the segment is placed in ES.
To use this instruction the word at the lower
memory address must contain the offset and the
word at the higher address must contain the
segment.
This instruction is very similar to LDS except that
it initializes ES instead of DS.

LAHF, SAHF, PUSHF, POPF
LAHF:
It transfer the lower byte of flag register to AH.
SAHF:
It transfer the contents of AH to lower byte of flag
register.
PUSHF:
Pushes flag register to top of stack.
POPF:
Pops the stack top to flag register.

XCHG
XCHG Des,Src
This instruction exchanges Src with Des.
It Exchanges contents of a register with any
other register or memory location.
It can not exchange segment registers.
It can not exchange two memory locations
directly.

XLAT (Translate)
XLAT
This instruction Converts the contents of the AL
register into a number stored in a memory table.
It performs the direct table lookup technique
often used to convert one code to another.
An XLAT instruction first adds the contents of AL
to BX to form a memory address within the data
segment.
It is only instruction that adds an 8-bit to a 16-bit
number

IN and OUT
IN Accumulator, Port Address
This instruction transfers the operand from
specified port to accumulator register.
OUT Port Address, Accumulator

This instruction transfers the operand from
accumulator to specified port.
IN & OUT instructions perform I/O operations.

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8088 Hardware Specifications

Two modes: MN/MX

These lines are multiplexed address and data.

These are address lines only.

These lines are multiplexed address and status.

Control Bus (cont)

Causes the processor to reset itself.

Clock input to the precessor.

Power supply connection, 5.0V, 10%.

Power supply connection. Note that both ground pins must be

Selects minimum or maximum mode of operation.

Data bus enable activates the external data bus buffer.

This input receives DMA - direct memory access requests.

When asserted this pin acknowledges that the processor entered a

Request/grant pins used for DMA during maximum mode

Minimum VS Maximum Mode

Maximum mode provides greater versatility at a

Data Move Instructions in

The operand can be a constant, memory

Data Movement Instructions

Data Movement Instructions

Data Movement Instructions

Data Movement Instructions

Data Movement Instructions

Data Movement Instructions

Data Movement Instructions

Data Movement Instructions

Data Movement Instructions

OUT Port Address, Accumulator

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