STT-RAM is an emerging non-volatile memory technology that could replace SRAM in processor caches. It combines the capacity and cost benefits of DRAM, the fast read and write performance of SRAM, and the non-volatility of flash memory. STT-RAM uses magnetic tunnel junctions as the basic storage element and employs spin-transfer torque writing and tunneling magnetoresistance reading. It has potential to serve as a universal memory due to its characteristics of high performance, density, capacity, endurance, and scalability. However, maintaining thermal stability while reducing write current density poses challenges for its implementation as a universal memory replacement.
STT-RAM is an emerging non-volatile memory technology that could replace SRAM in processor caches. It combines the capacity and cost benefits of DRAM, the fast read and write performance of SRAM, and the non-volatility of flash memory. STT-RAM uses magnetic tunnel junctions as the basic storage element and employs spin-transfer torque writing and tunneling magnetoresistance reading. It has potential to serve as a universal memory due to its characteristics of high performance, density, capacity, endurance, and scalability. However, maintaining thermal stability while reducing write current density poses challenges for its implementation as a universal memory replacement.
Original Description:
STT-RAM is an emerging non volatile technology that is potential universal memory
STT-RAM is an emerging non-volatile memory technology that could replace SRAM in processor caches. It combines the capacity and cost benefits of DRAM, the fast read and write performance of SRAM, and the non-volatility of flash memory. STT-RAM uses magnetic tunnel junctions as the basic storage element and employs spin-transfer torque writing and tunneling magnetoresistance reading. It has potential to serve as a universal memory due to its characteristics of high performance, density, capacity, endurance, and scalability. However, maintaining thermal stability while reducing write current density poses challenges for its implementation as a universal memory replacement.
STT-RAM is an emerging non-volatile memory technology that could replace SRAM in processor caches. It combines the capacity and cost benefits of DRAM, the fast read and write performance of SRAM, and the non-volatility of flash memory. STT-RAM uses magnetic tunnel junctions as the basic storage element and employs spin-transfer torque writing and tunneling magnetoresistance reading. It has potential to serve as a universal memory due to its characteristics of high performance, density, capacity, endurance, and scalability. However, maintaining thermal stability while reducing write current density poses challenges for its implementation as a universal memory replacement.
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STT-RAM
STT-RAM is an emerging non-volatile
technology that is a potential universal
memory that could replace SRAM in processor caches. STT-RAM is an evolution in magnetic storage from hard disk drive to solid state semiconductor memory.
Need for new memory technology
Critical applications now-a-days are more data-centric
and less compute-centric.
Memory performance becoming a bottleneck due to increasing amount of data. Compute speed can still be increased but processor speed is limited by memory speed. Clock speed cannot be increased above certain limit to avoid heating. Need of an alternate memory technology which can replace existing technologies in memory hierarchy.
COMPARISION WITH OTHER RAMS
STT-RAM is an emerging non volatile memory technology that combines The capacity and cost benefits of DRAM The fast read and write performance of SRAM The non volatility of FLASH with essentially unlimited endurance
Revolution in memory Researchers proposed STT-RAM (Spin Transfer Torque Random
Access Memory). It can be used as Universal Memory. It has potential to replace all memories in existing memory hierarchy. It has characteristics of every level in memory hierarchy viz. high performance high density high capacity high endurance low power consumption non-volatility future scalability
Architecture and design of
STT-RAM cell MTJ (Magnetic Tunnel Junction) is the basic storage element of the cell. MTJ structure: Two ferromagnetic layers viz. Hard layer and Free layer Hard layer has fixed magnetic orientation. Free layer has variable magnetic orientation. Data is stored as relative magnetic orientation of these two layers.
Physics: Two physical phenomenon describe the functionality of STT-RAM. Tunneling magnetoresistance (TMR) effect for reading and the spin-transfer
torque (STT) effect for writing.
TMR enables magnetic state of the Free layer to be sensed and hence the stored information to be read. STT enables electrons/current flowing through MTJ to change the relative orientation
MTJ-building block of sttram
MTJs have no intrinsic leakage current
because the free layer needs no currentto
maintain it state. Applying a small fixed voltage to the MTJ results in a high or low current depending on whether the free layer is currently parallel or anti-parallel to the magnetic orientation of hard layer.
OVERVIEW OF STT-RAM It makesuse of the modern spintronics
technology that exploits the quantum propensity
of the electronsto spin as well as making use of their charge state . STT-RAM is a form of MRAMthat uses spin transfer torque to reorient the free layer by passing a large, directional writecurrent through the MTJ. The switching process is regulated by a thermally controlled stochastic process, which means that the free layer could change state at any time.
Working of STT-RAM cell
The relative magnetic orientation is changed by passing
spin-polarized current through MTJ.
Current transfers spin angular momentum between the magnetic layers. This results in torque on magnetization of Free layer changing its relative magnetic orientation w.r.t. that of Hard layer.
Rather than using a magnetic field to write
zeros and ones as with conentional chips ,an
STT-RAM chip records digital data by passing a current through the magnet and then over the film structure. As the current moves through the magnet,it becomes polarized Transferring the current through a pre layer create TORQUE The TORQUE changes the direction of polarized current and the orientation of pre layers.
COMPARISION WITH mRAM
Read operation A small voltage (< 0.5V) is applied across
the bit cell to sense the data stored in the
MTJ, which is compared to the average of two reference MTJ cells One of the reference cells is in the parallel (low resistance) state while the other is in the anti-parallel (high resistance) state.
Write operation
Uses spin-polarized current instead of
magnetic field to switch magnetization of
storage layer Has low power consumption and excellent scalability Writing 1 and 0
Challenges faced Two main challenges:Stochastic nature of MTJ:
1.
Transient behavior is non-deterministic due to random thermal kicks
acting on its magnetization during switching activity. Thermal stability factor (D) is the measure of its stable transient behavior. D = (Hk*Ms^2*Ar*t^2)/(kB*T) Where, Ms = Saturation magnetization, Ar = Area of MTJ, Hk = Uniaxial anisotropy, t = thickness of free layer
High write energy:
2.
Intrinsic/switching/write current density (Jc0) can give the measure of
write energy.
To maintain D with the high Ms, the switching current
increases. For reliable memory operation, low switching current with high value of D is required.
Current Trends Clinton W. Smullen, et al demonstrated a scheme to reduce write
energy of STT-RAM by relaxing its non-volatility for using it as fast
and energy-efficient cache. Reduction in planar area of MTJ caused reduction in retention time and hence non volatility. In another paper, Clinton W. Smullen, et al, proposed a scheme to reduce write energy by tuning the saturation magnetization Ms and thickness of Free layer t. In the same paper, Clinton W. Smullen, et al, proposed another approach wherein the difference between write energy for write 0 and write 1 is considered and the minimum of two is used write STTRAM cell. 7% average reduction in total write energy is achieved.
Future prospects Promising candidate for replacing SRAM, DRAM and
MRAM in cache and main memory.
Excellent scalability feature allows the researchers to evaluate its performance in multicore processing systems and parallel high performance computing systems. Compact and simple cell structure provide higher packaging density thus decreasing the cost per unit. Possible to implement multi-level cell structure using MTJ further increasing the cells per unit area. High endurance implies increased lifetime of memory.
Future prospects Standalone STT-RAM and Embedded STT-RAM
product roadmap: Mohamad T. Krounbi, S. Watts, D. Apalkov, X. Tang, K. MoonV. Nikitin , A. Ong, V. Nikitin, E. Chen, Status and Challenges for Non-Volatile Spin-Transfer Torque RAM (STT-RAM) ppt, International Symposium on Advanced Gate Stack TechnologyAlbany, NYSeptember 29 October 1 , 2010.
applications One of the first applications for stand-alone
STT-RAM will be as a mobile RAM replacement.
STT-RAM has other key initial applications as an embedded memory. STT-RAM is easily embedded in standard CMOS processes.
Smart phone with conventional
memory
Smart phone with stt-ram memory
Leading developers and researchers
of STT-RAM Grandis Inc. is the key inventor and pioneer in STT-RAM
technology. Hitachi and Tohoku University demonstrated a 32-Mbit STT-RAM in June 2009. In 2011, Qualcomm presented a 1 Mbit Embedded STTMRAM, manufactured in TSMC's 45 nm LP technology at the Symposium on VLSI Circuits.
Conclusion STT-RAM is capable of being called as Universal
Memory. maintaining a balance between its two parameters viz. thermal stability and write current density is a prime challenge before it can be used as a Universal Memory. Novel techniques have been proposed and are being invented which could help improve its performance and energy efficiency.
