COMPUTER ORGANIZATION AND D

The Hardware/Software Interface

Chapter 2
Instructions: Language
of the Computer

Instruction Set

The repertoire of instructions of a

computer
Different computers have different
instruction sets

Early computers had very simple

instruction sets

But with many aspects in common

Simplified implementation

Many modern computers also have simple

instruction sets
Chapter 2 Instructions: Language of the Computer 2

The MIPS Instruction Set

Used as the example throughout the book

Stanford MIPS commercialized by MIPS
Technologies (www.mips.com)
Large share of embedded core market

Applications in consumer electronics, network/storage

equipment, cameras, printers,

Typical of many modern ISAs

See MIPS Reference Data tear-out card, and

Appendixes B and E

Chapter 2 Instructions: Language of the Computer 3

Add and subtract, three operands

Two sources and one destination

add a, b, c # a gets b + c
All arithmetic operations have this form
Design Principle 1: Simplicity favours
regularity

2.2 Operations of the Computer Hardware

Arithmetic Operations

Regularity makes implementation simpler

Simplicity enables higher performance at
lower cost
Chapter 2 Instructions: Language of the Computer 4

Arithmetic Example

C code:
f = (g + h) - (i + j);

Compiled MIPS code:

add t0, g, h
add t1, i, j
sub f, t0, t1

# temp t0 = g + h
# temp t1 = i + j
# f = t0 - t1

Chapter 2 Instructions: Language of the Computer 5

Arithmetic instructions use register

operands
MIPS has a 32 32-bit register file

Assembler names

Use for frequently accessed data

Numbered 0 to 31
32-bit data called a word
$t0, $t1, , $t7 for temporary values
$s0, $s1, , $s7 for saved variables

2.3 Operands of the Computer Hardware

Register Operands

Design Principle 2: Smaller is faster

c.f. main memory: millions of locations

Chapter 2 Instructions: Language of the Computer 6

In MIPS assembly language

$s0 - $s7 maps onto register 16 to 23
$t0 - $t7 maps onto register 8 to 15
$s0 means register 16
$s1 means register 17
.
$t0 means register 8
$t1 means register 9
..

Chapter 2 Instructions: Language of the Computer 7

Register Operand Example

C code:
f = (g + h) - (i + j);
f, , j in $s0, , $s4

Compiled MIPS code:

add $t0, $s1, $s2
add $t1, $s3, $s4
sub $s0, $t0, $t1

Chapter 2 Instructions: Language of the Computer 8

Memory Operands

Main memory used for composite data

To apply arithmetic operations

Load values from memory into registers

Store result from register to memory

Memory is byte addressed

Arrays, structures, dynamic data

Each address identifies an 8-bit byte

Words are aligned in memory

Address must be a multiple of 4

MIPS is Big Endian

Most-significant byte at least address of a word

Big here means the largest address, the least significant byte at the
largest address. Byte address 0 1 2 3. The MSB at address 0 the LSB
at address 3

Little Endian:

least-significant byte at least address

Little here means the least address. The least significant byte at the least
address. Byte Address 0 1 2 3. MSB at address 3, the LSB at address 0

Chapter 2 Instructions: Language of the Computer 9

Memory Operand Example 1

C code:
g = h + A[8];
g in $s1, h in $s2, base address of A in $s3

Compiled MIPS code:

Index 8 requires offset of 32

4 bytes per word

lw $t0, 32($s3)
add $s1, $s2, $t0
offset

# load word

base register, i.e., rs

Chapter 2 Instructions: Language of the Computer 10

Memory Operand Example 2

C code:
A[12] = h + A[8];
h in $s2, base address of A in $s3

Compiled MIPS code:

Index 8 requires offset of 32
lw $t0, 32($s3)
# load word
add $t0, $s2, $t0
sw $t0, 48($s3)
# store word

Chapter 2 Instructions: Language of the Computer 11

Registers vs. Memory

Registers are faster to access than

memory
Operating on memory data requires loads
and stores

More instructions to be executed

Compiler must use registers for variables

as much as possible

Only spill to memory for less frequently used

variables
Register optimization is important!
Chapter 2 Instructions: Language of the Computer 12

Immediate Operands

Constant data specified in an instruction

addi $s3, $s3, 4

No subtract immediate instruction

Just use a negative constant

addi $s2, $s1, -1

Design Principle 3: Make the common

case fast

Small constants are common

Immediate operand avoids a load instruction
Chapter 2 Instructions: Language of the Computer 13

The Constant Zero

MIPS register 0 ($zero) is the constant 0

Cannot be overwritten

Useful for common operations

E.g., move between registers

add $t2, $s1, $zero

Chapter 2 Instructions: Language of the Computer 14

Given an n-bit number

x x n1 2

x n2 2

n2

x1 2 x 0 2
1

Range: 0 to +2n 1
Example

n 1

2.4 Signed and Unsigned Numbers

Unsigned Binary Integers

0000 0000 0000 0000 0000 0000 0000 10112

= 0 + + 123 + 022 +121 +120
= 0 + + 8 + 0 + 2 + 1 = 1110

Using 32 bits

0 to +4,294,967,295
Chapter 2 Instructions: Language of the Computer 15

2s-Complement Signed Integers

Given an n-bit number

x x n1 2

n2

x n2 2

x1 2 x 0 2
1

Range: 2n 1 to +2n 1 1
Example

n 1

1111 1111 1111 1111 1111 1111 1111 11002

= 1231 + 1230 + + 122 +021 +020
= 2,147,483,648 + 2,147,483,644 = 4 10

Using 32 bits

2,147,483,648 to +2,147,483,647
Chapter 2 Instructions: Language of the Computer 16

2s-Complement Signed Integers

Bit 31 is sign bit

1 for negative numbers

0 for non-negative numbers

(2n 1) cant be represented

Non-negative numbers have the same unsigned
and 2s-complement representation
Some specific numbers

0: 0000 0000 0000

1: 1111 1111 1111
Most-negative: 1000 0000 0000
Most-positive: 0111 1111 1111
Chapter 2 Instructions: Language of the Computer 17

Signed Negation

Complement and add 1

Complement means 1 0, 0 1
x x 1111...111 2 1
x 1 x

Example: negate +2

+2 = 0000 0000 00102

2 = 1111 1111 11012 + 1

= 1111 1111 11102
Chapter 2 Instructions: Language of the Computer 18

Sign Extension

Representing a number using more bits

In MIPS instruction set

addi: extend immediate value

lb, lh: extend loaded byte/halfword
beq, bne: extend the displacement

Replicate the sign bit to the left

Preserve the numeric value

c.f. unsigned values: extend with 0s

Examples: 8-bit to 16-bit

+2: 0000 0010 => 0000 0000 0000 0010

2: 1111 1110 => 1111 1111 1111 1110
Chapter 2 Instructions: Language of the Computer 19

Representing Instructions

Instructions are encoded in binary

MIPS instructions

Called machine code

Encoded as 32-bit instruction words
Small number of formats encoding operation code
(opcode), register numbers,
Regularity!

Register numbers

$t0 $t7 are regs 8 15

$t8 $t9 are regs 24 25
$s0 $s7 are regs 16 23
Chapter 2 Instructions: Language of the Computer 20

MIPS R-format Instructions

op

rs

rt

rd

shamt

funct

6 bits

5 bits

5 bits

5 bits

5 bits

6 bits

Instruction fields

op: operation code (opcode)

rs: first source register number
rt: second source register number
rd: destination register number
shamt: shift amount (00000 for now)
funct: function code (extends opcode)
Chapter 2 Instructions: Language of the Computer 21

R-format Example
op

rs

rt

rd

shamt

funct

6 bits

5 bits

5 bits

5 bits

5 bits

6 bits

add $t0, $s1, $s2

special

$s1

$s2

$t0

add

17

18

32

000000

10001

10010

01000

00000

100000

000000100011001001000000001000002 = 0232402016
Chapter 2 Instructions: Language of the Computer 22

Hexadecimal

Base 16

Compact representation of bit strings

4 bits per hex digit

0000

0100

1000

1100

0001

0101

1001

1101

0010

0110

1010

1110

0011

0111

1011

1111

Example: eca8 6420

1110 1100 1010 1000 0110 0100 0010 0000

Chapter 2 Instructions: Language of the Computer 23

MIPS I-format Instructions

rs

rt

constant or address

6 bits

5 bits

5 bits

16 bits

Immediate arithmetic and load/store instructions

op

rt: destination or source register number

Constant: 215 to +215 1
Address: offset added to base address in rs

Design Principle 4: Good design demands good

compromises

Different formats complicate decoding, but allow 32-bit

instructions uniformly
Keep formats as similar as possible
Chapter 2 Instructions: Language of the Computer 24

Stored Program Computers

The BIG Picture

Instructions represented in
binary, just like data
Instructions and data stored
in memory
Programs can operate on
programs

e.g., compilers, linkers,

Binary compatibility allows

compiled programs to work
on different computers

Standardized ISAs

Chapter 2 Instructions: Language of the Computer 25

Instructions for bitwise manipulation

Operation

Java

MIPS

Shift left

<<

<<

sll

Shift right

>>

>>>

srl

Bitwise AND

&

&

and, andi

Bitwise OR

or, ori

Bitwise NOT

nor

2.6 Logical Operations

Logical Operations

Useful for extracting and inserting

groups of bits in a word
Chapter 2 Instructions: Language of the Computer 26

Shift Operations

rs

rt

rd

shamt

funct

6 bits

5 bits

5 bits

5 bits

5 bits

6 bits

shamt: how many positions to shift

Shift left logical

op

Shift left and fill with 0 bits

sll by i bits multiplies by 2i

Shift right logical

Shift right and fill with 0 bits

srl by i bits divides by 2i (unsigned only)
Chapter 2 Instructions: Language of the Computer 27

AND Operations

Useful to mask bits in a word

Select some bits, clear others to 0

and $t0, $t1, $t2

$t2

0000 0000 0000 0000 0000 1101 1100 0000

$t1

0000 0000 0000 0000 0011 1100 0000 0000

$t0

0000 0000 0000 0000 0000 1100 0000 0000

Chapter 2 Instructions: Language of the Computer 28

OR Operations

Useful to include bits in a word

Set some bits to 1, leave others unchanged

or $t0, $t1, $t2

$t2

0000 0000 0000 0000 0000 1101 1100 0000

$t1

0000 0000 0000 0000 0011 1100 0000 0000

$t0

0000 0000 0000 0000 0011 1101 1100 0000

Chapter 2 Instructions: Language of the Computer 29

NOT Operations

Useful to invert bits in a word

Change 0 to 1, and 1 to 0

MIPS has NOR 3-operand instruction

a NOR b == NOT ( a OR b )

nor $t0, $t1, $zero

Register 0: always
read as zero

$t1

0000 0000 0000 0000 0011 1100 0000 0000

$t0

1111 1111 1111 1111 11 00 0011 1111 1111

Chapter 2 Instructions: Language of the Computer 30

Conditional Operations

Branch to a labeled instruction if a

condition is true

beq rs, rt, L1

if (rs == rt) branch to instruction labeled L1;

bne rs, rt, L1

Otherwise, continue sequentially

if (rs != rt) branch to instruction labeled L1;

j L1

unconditional jump to instruction labeled L1

Chapter 2 Instructions: Language of the Computer 31

Compiling If Statements

C code:
if (i==j) f = g+h;
else f = g-h;

f, g, in $s0, $s1,

Compiled MIPS code:

bne
add
j
Else: sub
Exit:

$s3, $s4, Else

$s0, $s1, $s2
Exit
$s0, $s1, $s2
Assembler calculates addresses
Chapter 2 Instructions: Language of the Computer 32

Compiling Loop Statements

C code:
while (save[i] == k) i += 1;

i in $s3, k in $s5, address of save in $s6

Compiled MIPS code:

Loop: sll

$t1, $s3, 2

#t1=i*4 due

$t1, $t1, $s6 #t1 = addr.

to byte addressing

add

of save[i]

lw
bne
addi
j
Exit:

$t0, 0($t1)
$t0, $s5, Exit
$s3, $s3, 1
Loop
Chapter 2 Instructions: Language of the Computer 33

Basic Blocks

A basic block is a sequence of instructions

with

No embedded branches (except at end)

No branch targets (except at beginning)

A compiler identifies basic

blocks for optimization
An advanced processor
can accelerate execution
of basic blocks

Chapter 2 Instructions: Language of the Computer 34

More Conditional Operations

Set result to 1 if a condition is true

slt rd, rs, rt

if (rs < rt) rd = 1; else rd = 0;

slti rt, rs, constant

Otherwise, set to 0

if (rs < constant) rt = 1; else rt = 0;

Use in combination with beq, bne

slt $t0, $s1, $s2
bne $t0, $zero, L

# if ($s1 < $s2)

#
branch to L

Chapter 2 Instructions: Language of the Computer 35

Branch Instruction Design

Why not blt, bge, etc?

Hardware for <, , slower than =,

Combining with branch involves more work

per instruction, requiring a slower clock
All instructions penalized!

beq and bne are the common case

This is a good design compromise

Chapter 2 Instructions: Language of the Computer 36

Signed vs. Unsigned

Signed comparison: slt, slti

Unsigned comparison: sltu, sltui
Example

$s0 = 1111 1111 1111 1111 1111 1111 1111 1111

$s1 = 0000 0000 0000 0000 0000 0000 0000 0001
slt $t0, $s0, $s1 # signed

1 < +1 $t0 = 1

sltu $t0, $s0, $s1

# unsigned

+4,294,967,295 > +1 $t0 = 0

Chapter 2 Instructions: Language of the Computer 37

Steps required
1.
2.
3.
4.
5.
6.

Place parameters in registers

Transfer control to procedure
Acquire storage for procedure
Perform procedures operations
Place result in register for caller
Return to place of call

2.8 Supporting Procedures in Computer Hardware

Procedure Calling

Chapter 2 Instructions: Language of the Computer 38

Register Usage

$a0 $a3: arguments (regs 4 7)

$v0, $v1: result values (regs 2 and 3)
$t0 $t9: temporaries

$s0 $s7: saved

Can be overwritten by callee

Must be saved/restored by callee

$gp: global pointer for static data (reg 28)

$sp: stack pointer (reg 29)
$fp: frame pointer (reg 30)
$ra: return address (reg 31)
Chapter 2 Instructions: Language of the Computer 39

Procedure Call Instructions

Procedure call: jump and link

jal ProcedureLabel
Address of following instruction put in $ra
Jumps to target address

Procedure return: jump register

jr $ra
Copies $ra to program counter
Can also be used for computed jumps

e.g., for case/switch statements

Chapter 2 Instructions: Language of the Computer 40

Leaf Procedure Example

C code:
int leaf_example (int g, h, i, j)
{ int f;
f = (g + h) - (i + j);
return f;
}
Arguments g, , j in $a0, , $a3
f in $s0 (hence, need to save $s0 on stack)
Result in $v0

Chapter 2 Instructions: Language of the Computer 41

Leaf Procedure Example

MIPS code:
leaf_example:
addi $sp, $sp, -4
sw
$s0, 0($sp)
add $t0, $a0, $a1
add $t1, $a2, $a3
sub $s0, $t0, $t1
add $v0, $s0, $zero
lw
$s0, 0($sp)
addi $sp, $sp, 4
jr
$ra

Save $s0 on stack

Procedure body
Result
Restore $s0
Return

Chapter 2 Instructions: Language of the Computer 42

Non-Leaf Procedures

Procedures that call other procedures

For nested call, caller needs to save on
the stack:

Its return address

Any arguments and temporaries needed after
the call

Restore from the stack after the call

Chapter 2 Instructions: Language of the Computer 43

Non-Leaf Procedure Example

C code:
int fact (int n)
{
if (n < 1) return f; # f=1 (0!=1)
else return n * fact(n - 1);
}
Argument n in $a0
Result in $v0

Chapter 2 Instructions: Language of the Computer 44

Non-Leaf Procedure Example

MIPS code:
fact:
addi
sw
sw
slti
beq
addi
addi
jr
L1: addi
jal
lw
lw
addi
mul
jr

$sp,
$ra,
$a0,
$t0,
$t0,
$v0,
$sp,
$ra
$a0,
fact
$a0,
$ra,
$sp,
$v0,
$ra

$sp, -8
4($sp)
0($sp)
$a0, 1
$zero, L1
$zero, 1
$sp, 8
$a0, -1
0($sp)
4($sp)
$sp, 8
$a0, $v0

#
#
#
#

adjust stack for 2 items

save return address
save argument
test for n < 1

#
#
#
#
#
#
#
#
#
#

if so, result is 1
pop 2 items from stack
and return
else decrement n
recursive call
restore original n
and return address
pop 2 items from stack
multiply to get result
and return

Chapter 2 Instructions: Language of the Computer 45

Character Data

Byte-encoded character sets

ASCII: 128 characters

Latin-1: 256 characters

95 graphic, 33 control
ASCII, +96 more graphic characters

Unicode: 32-bit character set

Used in Java, C++ wide characters,

Most of the worlds alphabets, plus symbols
UTF-8, UTF-16: variable-length encodings

Keeps ASCII as 8 bits uses 16 bits for other characters

Chapter 2 Instructions: Language of the Computer 46

Byte/Halfword Operations

Could use bitwise operations

MIPS byte/halfword load/store

String processing is a common case

lb rt, offset(rs)

Sign extend to 32 bits in rt

lbu rt, offset(rs)

lhu rt, offset(rs)

Zero extend to 32 bits in rt

sb rt, offset(rs)

lh rt, offset(rs)

sh rt, offset(rs)

Store just rightmost byte/halfword

Chapter 2 Instructions: Language of the Computer 47

Most constants are small

16-bit immediate is sufficient

For the occasional 32-bit constant

lui rt, constant

Copies 16-bit constant to left 16 bits of rt

Clears right 16 bits of rt to 0

lui $s0, 61

0000 0000 0111 1101 0000 0000 0000 0000

ori $s0, $s0, 2304 0000 0000 0111 1101 0000 1001 0000 0000

2.10 MIPS Addressing for 32-Bit Immediates and Addresses

32-bit Constants

Chapter 2 Instructions: Language of the Computer 48

Branch Addressing

Branch instructions specify

Most branch targets are near branch

Opcode, two registers, target address

Forward or backward
op

rs

rt

constant or address

6 bits

5 bits

5 bits

16 bits

PC-relative addressing

Target address = PC + offset 4

PC already incremented by 4 by this time
Chapter 2 Instructions: Language of the Computer 49

Jump Addressing

Jump (j and jal) targets could be

anywhere in text segment

Encode full address in instruction

op

address

6 bits

26 bits

(Pseudo)Direct jump addressing

Target address = PC3128 : (address 4)

Update PC with concatenation of
Top 4 bits of old PC
26-bit jump address
00
Chapter 2 Instructions: Language of the Computer 50

Target Addressing Example

Loop code from earlier example

Assume Loop at location 80000

Loop: sll

$t1, $s3, 2

80000

19

add

$t1, $t1, $s6

80004

22

32

lw

$t0, 0($t1)

80008

35

bne

$t0, $s5, Exit

80012

21

addi $s3, $s3, 1

80016

19

19

80020

Exit:

Loop

20000

80024

Chapter 2 Instructions: Language of the Computer 51

Branching Far Away

If branch target is too far to encode with

16-bit offset, assembler rewrites the code
Example
beq $s0,$s1, L1

bne $s0,$s1, L2
j L1
L2:

Chapter 2 Instructions: Language of the Computer 52

Addressing Mode Summary

Chapter 2 Instructions: Language of the Computer 53

Translation and Startup

Many compilers produce
object modules directly

Static linking

Chapter 2 Instructions: Language of the Computer 54

C Sort Example

Illustrates use of assembly instructions

for a C bubble sort function
Swap procedure (leaf)

void swap(int v[], int k)

{
int temp;
temp = v[k];
v[k] = v[k+1];
v[k+1] = temp;
}
v in $a0, k in $a1, temp in $t0
Chapter 2 Instructions: Language of the Computer 55

The Procedure Swap

swap: sll $t1, $a1, 2
# $t1 = k * 4
add $t1, $a0, $t1 # $t1 = v+(k*4)
#
(address of v[k])
lw $t0, 0($t1)
# $t0 (temp) = v[k]
lw $t2, 4($t1)
# $t2 = v[k+1]
sw $t2, 0($t1)
# v[k] = $t2 (v[k+1])
sw $t0, 4($t1)
# v[k+1] = $t0 (temp)
jr $ra
# return to calling routine

Chapter 2 Instructions: Language of the Computer 56

The Sort Procedure in C

Non-leaf (calls swap)

void sort (int v[], int n)

{
int i, j;
for (i = 0; i < n; i += 1) {
for (j = i 1;
j >= 0 && v[j] > v[j + 1];
j -= 1) {
swap(v,j);
}
}
}
v in $a0, k in $a1, i in $s0, j in $s1
Chapter 2 Instructions: Language of the Computer 57

The Procedure Body

move
move
move
for1tst: slt
beq
addi
for2tst: slti
bne
sll
add
lw
lw
slt
beq
move
move
jal
addi
j
exit2:
addi
j

$s2, $a0
$s3, $a1
$s0, $zero
$t0, $s0, $s3
$t0, $zero, exit1
$s1, $s0, 1
$t0, $s1, 0
$t0, $zero, exit2
$t1, $s1, 2
$t2, $s2, $t1
$t3, 0($t2)
$t4, 4($t2)
$t0, $t4, $t3
$t0, $zero, exit2
$a0, $s2
$a1, $s1
swap
$s1, $s1, 1
for2tst
$s0, $s0, 1
for1tst

#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#

save $a0 into $s2

save $a1 into $s3
i = 0
$t0 = 0 if $s0 $s3 (i n)
go to exit1 if $s0 $s3 (i n)
j = i 1
$t0 = 1 if $s1 < 0 (j < 0)
go to exit2 if $s1 < 0 (j < 0)
$t1 = j * 4
$t2 = v + (j * 4)
$t3 = v[j]
$t4 = v[j + 1]
$t0 = 0 if $t4 $t3
go to exit2 if $t4 $t3
1st param of swap is v (old $a0)
2nd param of swap is j
call swap procedure
j = 1
jump to test of inner loop
i += 1
jump to test of outer loop

Move
params
Outer loop

Inner loop

Pass
params
& call
Inner loop
Outer loop

Chapter 2 Instructions: Language of the Computer 58

The Full Procedure

sort:

addi $sp,$sp, 20
sw $ra, 16($sp)
sw $s3,12($sp)
sw $s2, 8($sp)
sw $s1, 4($sp)
sw $s0, 0($sp)

exit1: lw $s0, 0($sp)

lw $s1, 4($sp)
lw $s2, 8($sp)
lw $s3,12($sp)
lw $ra,16($sp)
addi $sp,$sp, 20
jr $ra

#
#
#
#
#
#
#

make room on stack for 5 registers

save $ra on stack
save $s3 on stack
save $s2 on stack
save $s1 on stack
save $s0 on stack
procedure body

#
#
#
#
#
#
#

restore $s0 from stack

restore $s1 from stack
restore $s2 from stack
restore $s3 from stack
restore $ra from stack
restore stack pointer
return to calling routine

Chapter 2 Instructions: Language of the Computer 59

Effect of Compiler Optimization

Compiled with gcc for Pentium 4 under Linux

Chapter 2 Instructions: Language of the Computer 60

Effect of Language and Algorithm

Chapter 2 Instructions: Language of the Computer 61

Lessons Learnt

Instruction count and CPI are not good

performance indicators in isolation
Compiler optimizations are sensitive to the
algorithm
Java/JIT (Java In Time) compiled code is
significantly faster than JVM interpreted

Comparable to optimized C in some cases

Nothing can fix a dumb algorithm!

Chapter 2 Instructions: Language of the Computer 62

Arrays vs. Pointers

Array indexing involves

Multiplying index by element size

Adding to array base address

Pointers correspond directly to memory

addresses

Can avoid indexing complexity

Chapter 2 Instructions: Language of the Computer 63

Example: Clearing and Array

clear1(int array[], int size) {
int i;
for (i = 0; i < size; i += 1)
array[i] = 0;
}

clear2(int *array, int size) {

int *p;
for (p = &array[0]; p < &array[size];
p = p + 1)
*p = 0;
}

move $t0,$zero
loop1: sll $t1,$t0,2
add $t2,$a0,$t1

move $t0,$a0
# p = & array[0]
sll $t1,$a1,2
# $t1 = size * 4
add $t2,$a0,$t1 # $t2 =
#
&array[size]
loop2: sw $zero,0($t0) # Memory[p] = 0
addi $t0,$t0,4 # p = p + 4
slt $t3,$t0,$t2 # $t3 =
#(p<&array[size])
bne $t3,$zero,loop2 # if ()
# goto loop2

# i = 0
# $t1 = i * 4
# $t2 =
#
&array[i]
sw $zero, 0($t2) # array[i] = 0
addi $t0,$t0,1
# i = i + 1
slt $t3,$t0,$a1 # $t3 =
#
(i < size)
bne $t3,$zero,loop1 # if ()
# goto loop1

Chapter 2 Instructions: Language of the Computer 64

Comparison of Array vs. Ptr

Multiply strength reduced to shift

Array version requires shift to be inside loop

Part of index calculation for incremented i

c.f. incrementing pointer

Compiler can achieve same effect as

manual use of pointers

Induction variable elimination

Better to make program clearer and safer

an induction variable is a variable that gets increased or decreased by a fixed amount

on every iteration of a loop

Chapter 2 Instructions: Language of the Computer 65

ARM: the most popular embedded core

Similar basic set of instructions to MIPS
ARM

MIPS

1985

1985

Instruction size

32 bits

32 bits

Address space

32-bit flat

32-bit flat

Data alignment

Aligned

Aligned

15 32-bit

31 32-bit

Memory
mapped

Memory
mapped

Date announced

Data addressing modes

Registers
Input/output

2.16 Real Stuff: ARM Instructions

ARM & MIPS Similarities

Chapter 2 Instructions: Language of the Computer 66

Compare and Branch in ARM

Uses condition codes for result of an

arithmetic/logical instruction

Negative, zero, carry, overflow

Compare instructions to set condition codes
without keeping the result

Each instruction can be conditional

Top 4 bits of instruction word: condition value

Can avoid branches over single instructions

Chapter 2 Instructions: Language of the Computer 67

Instruction Encoding

Chapter 2 Instructions: Language of the Computer 68

Evolution with backward compatibility

8080 (1974): 8-bit microprocessor

8086 (1978): 16-bit extension to 8080

Adds FP instructions and register stack

80286 (1982): 24-bit addresses, MMU

Complex instruction set (CISC)

8087 (1980): floating-point coprocessor

Accumulator, plus 3 index-register pairs

2.17 Real Stuff: x86 Instructions

The Intel x86 ISA

Segmented memory mapping and protection

80386 (1985): 32-bit extension (now IA-32)

Additional addressing modes and operations

Paged memory mapping as well as segments
Chapter 2 Instructions: Language of the Computer 69

The Intel x86 ISA

Further evolution

i486 (1989): pipelined, on-chip caches and FPU

Pentium (1993): superscalar, 64-bit datapath

New microarchitecture (see Colwell, The Pentium Chronicles)

Pentium III (1999)

Later versions added MMX (Multi-Media eXtension)

instructions
The infamous FDIV bug

Pentium Pro (1995), Pentium II (1997)

Compatible competitors: AMD, Cyrix,

Added SSE (Streaming SIMD Extensions) and associated

registers

Pentium 4 (2001)

New microarchitecture
Added SSE2 instructions
Chapter 2 Instructions: Language of the Computer 70

The Intel x86 ISA

And further

AMD64 (2003): extended architecture to 64 bits

EM64T Extended Memory 64 Technology (2004)

Intel Core (2006)

Intel declined to follow, instead

Advanced Vector Extension (announced 2008)

Added SSE4 instructions, virtual machine support

AMD64 (announced 2007): SSE5 instructions

AMD64 adopted by Intel (with refinements)

Added SSE3 instructions

Longer SSE registers, more instructions

If Intel didnt extend with compatibility, its

competitors would!

Technical elegance market success

Chapter 2 Instructions: Language of the Computer 71

Basic x86 Registers

Chapter 2 Instructions: Language of the Computer 72

Basic x86 Addressing Modes

Two operands per instruction

Source/dest operand

Second source operand

Register

Register

Register

Immediate

Register

Memory

Memory

Register

Memory

Immediate

Memory addressing modes

Address in register
Address = Rbase + displacement
Address = Rbase + 2scale Rindex (scale = 0, 1, 2, or 3)
Address = Rbase + 2scale Rindex + displacement
Chapter 2 Instructions: Language of the Computer 73

x86 Instruction Encoding

Variable length
encoding

Postfix bytes specify

addressing mode
Prefix bytes modify
operation

Operand length,
repetition, locking,

Chapter 2 Instructions: Language of the Computer 74

Implementing IA-32
(Intel Architecture 32)

Complex instruction set makes

implementation difficult

Hardware translates instructions to simpler

microoperations

Simple instructions: 11
Complex instructions: 1many

Microengine similar to RISC

Market share makes this economically viable

Comparable performance to RISC

Compilers avoid complex instructions

Chapter 2 Instructions: Language of the Computer 75

ARM v8 Instructions

In moving to 64-bit, ARM did a complete

overhaul
ARM v8 resembles MIPS

Changes from v7:

No conditional execution field

Immediate field is 12-bit constant
Dropped load/store multiple
PC is no longer a GPR
GPR set expanded to 32
Addressing modes work for all word sizes
Divide instruction
Branch if equal/branch if not equal instructions
Chapter 2 Instructions: Language of the Computer 76

Fallacies

Powerful instruction higher performance

Fewer instructions required

But complex instructions are hard to implement

May slow down all instructions, including simple ones

Compilers are good at making fast code from simple

instructions

Use assembly code for high performance

But modern compilers are better at dealing with

modern processors
More lines of code more errors and less
productivity
Chapter 2 Instructions: Language of the Computer 77

Fallacies

Backward compatibility instruction set

doesnt change

But they do create more instructions

x86 instruction set

Chapter 2 Instructions: Language of the Computer 78

Pitfalls

Sequential words are not at sequential

addresses

Increment by 4, not by 1!

Keeping a pointer to an automatic variable

after procedure returns

e.g., passing pointer back via an argument

Pointer becomes invalid when stack popped

Chapter 2 Instructions: Language of the Computer 79

Concluding Remarks

Design principles
1.
2.
3.
4.

Layers of software/hardware

Simplicity favors regularity

Smaller is faster
Make the common case fast
Good design demands good compromises

Compiler, assembler, hardware

MIPS: typical of RISC ISAs

c.f. x86

Chapter 2 Instructions: Language of the Computer 80

Concluding Remarks

Measure MIPS instruction executions in

benchmark programs

Consider making the common case fast

Consider compromises

Instruction class

MIPS examples

SPEC2006 Int

SPEC2006 FP

Arithmetic

add, sub, addi

16%

48%

Data transfer

lw, sw, lb, lbu,

lh, lhu, sb, lui

35%

36%

Logical

and, or, nor, andi,

ori, sll, srl

12%

4%

Cond. Branch

beq, bne, slt,

slti, sltiu

34%

8%

Jump

j, jr, jal

2%

0%

Chapter 2 Instructions: Language of the Computer 81