Chapter 2.

Machine
Instructions and
Programs

Objectives

Number representation and addition/subtraction in

the 2s-complement system.
Machine instructions and program execution,
including branching and subroutine call and return
operations.
Addressing methods for accessing register and
memory operands.

Number, Arithmetic
Operations, and
Characters

Signed Integer
3

major representations:
Sign and magnitude
Ones complement
Twos complement

Assumptions:

4-bit machine word

16 different values can be represented
Roughly half are positive, half are negative

Sign and Magnitude

Representation
-7
-6
-5

1111
1110

+0
+1

0000
0001

1101

0010

+2

-4

1100

0011

+3

0 100 = + 4

-3

1011

0100

+4

1 100 = - 4

-2

1010

0101

1001

-1

0110
1000

-0

0111

+5

+6

+7

High order bit is sign: 0 = positive (or zero), 1 = negative

Three low order bits is the magnitude: 0 (000) thru 7 (111)
Number range for n bits = +/-2n-1 -1
Two representations for 0

Ones Complement
Representation
-0
-1
-2

1111
1110

+0
0000
0001

1101

+1

0010

+2

-3

1100

0011

+3

0 100 = + 4

-4

1011

0100

+4

1 011 = - 4

-5

1010

0101

1001

-6

0110
1000

-7

0111

+5

+6

+7

Subtraction implemented by addition & 1's complement

Still two representations of 0! This causes some problems
Some complexities in addition

Twos Complement
Representation
-1
-2
-3
like 1's comp
except shifted
one position
clockwise

1111
1110

+0
0000
0001

1101

+1

0010

+2

-4

1100

0011

+3

0 100 = + 4

-5

1011

0100

+4

1 100 = - 4

-6

1010

0101

1001

-7

0110
1000

-8

0111

+5

+6

+7

Only one representation for 0

One more negative number than positive
number

Binary, Signed-Integer
Representations
B

Page 28

Valuesrepresented

b3 b2b1b0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1

1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1

1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1

Signand
magnitude
+7
+6
+5
+4
+3
+2
+1
+0
0
1
2
3
4
5
6
7

1' scomplement
+7
+6
+5
+4
+3
+2
+1
+0
7
6
5
4
3
2
1
0

2' scomplement
+
+
+
+
+
+
+
+

Figure2.1.Binary,signedintegerrepresentations.

7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1

Addition and Subtraction 2s

Complement
(4+3, -4+-3, 4-3, -4+3,
-4
-3)
4
0100
If carry-in to the high
order bit =
carry-out then ignore
carry
if carry-in differs from
carry-out then overflow

-4

1100

+3

0011

+ (-3)

1101

0111

-7

11001

0100

-4

1100

-3

1101

+3

0011

10001

-1

1111

Simpler addition scheme makes twos complement the most common

choice for integer number systems within digital systems

2s-Complement Add and

Subtract Operations
(a)

0010
+ 0011

( + 2)
( + 3)

0101

( + 5)

(c)

1011
+ 1110
1001

5
2
7

(e)

1101
1001

3
7

Page 31

(f)

(g)

(h)

(i)

(j)

0010
0100
0110
0011
1001
1011
1001
0001
0010
1101

( + 2)
( + 4)
( + 6)
( + 3)
7
5
7
( + 1)
( + 2)
3

(b)

0111
+ 1101
0100

( + 4)
6
2
( + 7)
3
( + 4)

1101
+ 0111
0100

( + 4)

0100
+ 1010
1110

(d)

0010
+ 1100
1110
0110
+ 1101
0011
1001
+ 0101
1110

( + 3)

1001
+ 1111
1000

0010
+ 0011
0101

( + 5)

Figure2.4.2'scomplementAddandSubtractoperations.

Overflow - Add two positive numbers to get a

negative number or two negative numbers to
get a positive number
-1
-2

0000

0010

1100

0100

1010

0101

1001

-7

0110
1000

-8

0111

+6

+7
5 + 3 = -8

+3
+4
+5

1111

0000

+1

0001

1101

-4
-5

+0

1110

-3

+2

0011

1011

-6

-2

+1

0001

1101

-4
-5

1111
1110

-3

-1

+0

0010

1100
1011
1010

-6

0110
1000

-8
-7 - 2 = +7

0011

+3

0100

+4

0101

1001

-7

+2

0111

+7

+6

+5

Overflow Conditions
5

0111
0101

-7

1000
1001

0011

-2

1100

-8

1000

10111

Overflow

Overflow
5

0000
0101

-3

1111
1101

0010

-5

1011

0111

-8

11000

No overflow

No overflow

Overflow when carry-in to the high-order bit does not equal carry out

Sign Extension

Task:
Given w-bit signed integer x
Convert it to w+k-bit integer with same value
Rule:
Make k copies of sign bit:
X = xw1 ,, xw1 , xw1 , xw2 ,, x0
X

k copies of MSB

Sign Extension Example

short int x = 15213;

int
ix = (int) x;
short int y = -15213;
int
iy = (int) y;
x
ix
y
iy

Decimal
Hex
Binary
3B6D
0011101101101101
15213
15213 0000C492 00000000000000000011101101101101
C493
1100010010010011
-15213
-15213 FFFFC493 11111111111111111100010010010011

Memory Locations,
Addresses, and
Operations

Memory Location, Addresses,

and Operation
nbits

Memory consists
of many millions of
storage cells,
each of which can
store 1 bit.
Data is usually
accessed in n-bit
groups. n is called
word length.

firstword
secondword

ithword

lastword

Figure2.5.Memorywords.

Memory Location, Addresses,

and Operation
32-bit

word length example

32bits

b 31 b 30

b1

Signbit: b 31= 0 forpositivenumbers

b 31= 1 fornegativenumbers
(a)Asignedinteger

8bits

8bits

8bits

8bits

ASCII
character

ASCII
character

ASCII
character

ASCII
character

(b)Fourcharacters

b0

Memory Location, Addresses,

and Operation

To retrieve information from memory, either for one

word or one byte (8-bit), addresses for each location
are needed.
A k-bit address memory has 2k memory locations,
namely 0 2k-1, called memory space.
24-bit memory: 224 = 16,777,216 = 16M (1M=220)
32-bit memory: 232 = 4G (1G=230)
1K(kilo)=210
1T(tera)=240

Memory Location, Addresses,

and Operation
It

is impractical to assign distinct addresses to

individual bit locations in the memory.
The most practical assignment is to have
successive addresses refer to successive
byte locations in the memory byteaddressable memory.
Byte locations have addresses 0, 1, 2, If
word length is 32 bits, the successive words
are located at addresses 0, 4, 8,

Big-Endian and Little-Endian

Assignments

Big-Endian: lower byte addresses are used for the most significant bytes of the word
Little-Endian: opposite ordering. lower byte addresses are used for the less significant
bytes of the word
Word
address

Byteaddress

Byteaddress

2 4

2 4

2 3

2 2

2 1

(a)Bigendianassignment

2 4

2 1

2 2

2 3

2 4

(b)Littleendianassignment

Figure2.7.Byteandwordaddressing.

Memory Location, Addresses,

and Operation
Address

ordering of bytes
Word alignment

Words are said to be aligned in memory if they

begin at a byte addr. that is a multiple of the num
of bytes in a word.(8 bit = 1 byte)

16-bit(2 Byte) word: word addresses: 0, 2, 4,.

32-bit(4 Byte) word: word addresses: 0, 4, 8,.
64-bit(8 Byte) word: word addresses: 0, 8,16,.

Access

strings

numbers, characters, and character

Memory Operation
Load

Copy the content. The memory content doesnt change.

Address Load
Registers can be used

Store

(or Read or Fetch)

(or Write)

Overwrite the content in memory

Address and Data Store
Registers can be used

How is byte stored in a register?

Instruction and
Instruction Sequencing

Must-Perform Operations
Data

transfers between the memory and the

processor registers
Arithmetic and logic operations on data
Program sequencing and control
I/O transfers

Register Transfer Notation

Identify

a location by a symbolic name

standing for its hardware binary address
(LOC, R0,)
Contents of a location are denoted by placing
square brackets around the name of the
location (R1[LOC], R3 [R1]+[R2])
Register Transfer Notation (RTN)

Assembly Language Notation

Represent

machine instructions and programs.

Move LOC, R1 => R1[LOC]
Add R1, R2, R3 => R3 [R1]+[R2]
C=A+B in high level language
C [A]+[B]
ADD A,B,C; 3 address instruction
ADD A,B ; 2 address
How to prevent overwriting using 2 address?

Register transfer notation

R2[LOC]
R4 [R2] + [R3]

Assemble Language

Load R2,LOC
Add R4,R2,R3

CPU Organization
Single

Accumulator

Result usually goes to the Accumulator

Accumulator has to be saved to memory quite often

General

Register

Registers hold operands thus reduce memory traffic

Register bookkeeping

Stack

Operands and result are always in the stack

Instruction Formats

Three-Address Instructions
ADD
R1, R2, R3
ADD
A,B,C
Two-Address Instructions
ADD
R1, R2
ADD
A,B
One-Address Instructions
ADD
B
Zero-Address Instructions
ADD

R1 R2 + R3

R1 R1 + R2

AC AC + M[B]
TOS TOS + (TOS 1)

Opcode Operand(s) or Address(es)

 In

one address
LOAD B
STORE B

;AC M[B]
;M[B]AC

Steps in C [A]+[B] in one address?

 Load

A
Add B
Load C

Instruction Formats
Example: Evaluate X=(A+B) (C+D)
Three-Address
1.
2.
3.

ADD
ADD
MUL

R1, A, B
R2, C, D
X, R1, R2

; R1 M[A] + M[B]
; R2 M[C] + M[D]
; M[X] R1 R2

Instruction Formats
Example: Evaluate (A+B) (C+D)
Two-Address
1.
2.
3.
4.
5.
6.

MOV
ADD
MOV
ADD
MUL
MOV

R1, A
R1, B
R2, C
R2, D
R1, R2
X, R1

; R1 M[A]
; R1 R1 + M[B]
; R2 M[C]
; R2 R2 + M[D]
; R1 R1 R2
; M[X] R1

Instruction Formats
Example: Evaluate (A+B) (C+D)
One-Address
1.
2.
3.
4.
5.
6.
7.

LOAD A
ADD B
STORE T
LOAD C
ADD D
MUL T
STORE X

; AC M[A]
; AC AC + M[B]
; M[T] AC
; AC M[C]
; AC AC + M[D]
; AC AC M[T]
; M[X] AC

Instruction Formats
Example: Evaluate (A+B) (C+D)
Zero-Address
1.
2.
3.
4.
5.
6.
7.

8.

PUSH A
PUSH B
ADD
PUSH C
PUSH D
ADD
MUL
(C+D)(A+B)
POP X

; TOS A
; TOS B
; TOS (A + B)
; TOS C
; TOS D
; TOS (C + D)
; TOS
; M[X] TOS

Using Registers
Registers

are faster
Shorter instructions

The number of registers is smaller (e.g. 32

registers need 5 bits)

Potential

speedup
Minimize the frequency with which data is
moved back and forth between the memory
and processor registers.

Using Registers contd

Instructions

where only register names are

contained , will normally fit into one word.
Add Ri,Rj;
Add Ri,Rj,Rk;
C=A+B

MOVE Rj, A
MOVE Rk,B
ADD Rj,Rk
MOVE C,Rj

Address
Beginexecutionhere

Contents

Move A,R0

i+4

Add

B,R0

3instruction
program
segment

Assumptions:
- One memory operand
per instruction
- 32-bit word length
- Memory is byte
addressable
- Full memory address
can be directly specified
in a single-word instruction

i+8
Instruction
Execution and StraightLine Sequencing
c[A]+[B]
Move R0,C

Datafor
theprogram

Two-phase procedure
-Instruction fetch
-Instruction execute
Page 43

Figure2.8.AprogramforC+

Branching

Move

NUM1,R0

i+4

Add

NUM2,R0

i+8

Add

NUM3,R0

i + 4n 4

Add

NUMn,R0

i + 4n

Move

R0,SUM

SUM

NUM1
NUM2

NUMn

Figure2.9.Astraightlineprogramforaddingnnumbers.

Branching

LOOP
Program
loop

Branch target

Move

N,R1

Clear

R0

Determineaddressof
"Next"numberandadd
"Next"numbertoR0
Decrement

R1

Branch>0

LOOP

Move

R0,SUM

Conditional branch

SUM
N

NUM1

Figure2.10.Usingalooptoaddnnumbers.

NUM2

NUMn

Condition Codes
Condition

code flags
Condition code register / status register
N (negative), 1 if result is ve else 0
Z (zero), 1 if result is 0 else 0
V (overflow), 1 if arithmetic overflow occurs
else 0
C (carry), 1 if carry out occurs else 0
Different instructions affect different flags
Ex: Branch>0 tests Z flag

Conditional Branch
Instructions
Example:

A: 1 1 1 1 0 0 0 0
B: 0 0 0 1 0 1 0 0

A:

11110000

+(B): 1 1 1 0 1 1 0 0
11011100
C=1
V=0

Z=0

Addressing Modes

Generating Memory Addresses

How

to specify the address of branch target?

Can we give the memory operand address
directly in a single Add instruction in the
loop?
Use a register to hold the address of NUM1;
then increment by 4 on each pass through
the loop.

Addressing Modes
Opcode Mode

...

Different ways in which location of an operand is

specified in an instruction
Implied
AC is implied in ADD M[AR] in One-Address instr.
TOS is implied in ADD in Zero-Address instr.
Immediate
The use of a constant in MOV R1, #5, i.e. R1 5
Register
Indicate which register holds the operand

Addressing Modes
Register

Indirect

Indicate the register that holds the number of the

register that holds the operand
R1

MOV

R1, (R2)

Autoincrement

Access & update in 1 instr.

Direct

/ Autodecrement

R2 = 3
R3 = 5

Address(or absolute address)

Use the given address to access a memory location

Addressing Modes
Indirect

Address

Indicate the memory location that holds the

address of the memory location that holds the
data
AR = 101

A=*B
Move R1,B
Move R2,(R1)

100
101
102
103
104

0 1 0 4

1 1 0 A

Relative Addressing

Relative mode the effective address is determined

by the Index mode using the program counter in
place of the general-purpose register.
X(PC) note that X is a signed number
Branch>0
LOOP
This location is computed by specifying it as an
offset from the current value of PC.
Branch target may be either before or after the
branch instruction, the offset is given as a singed
num.

Addressing Modes
Relative

Address

EA = PC + Relative Addr
PC = 2

0
1
2

AR = 100

Could be Positive
or Negative
(2s Complement)

100
101
102
103
104

1 1 0 A

Addressing Modes
Base

Register

EA = Base Register + Relative Addr

Could be Positive
or Negative
(2s Complement)

AR = 2
+

BR = 100

Usually points
to the beginning
of an array

100
101
102
103
104

0
0
0
0
0

0
0
0
1
0

0
1
0
0
5

5
2
A
7
9

Addressing Modes
Name

The different
ways in which
the location of
an operand is
specified in
an instruction
are referred to
as addressing
modes.

Assembler syntax

Addressing
function

Immediate

#Value

Operand=Value

Register

Ri

EA = Ri

Absolute(Direct)

LOC

EA = LOC

Indirect

(Ri )
(LOC)

EA = [Ri ]
EA = [LOC]

Index

X(Ri)

EA = [Ri ] + X

Basewithindex

(Ri ,Rj )

EA = [Ri ] + [Rj ]

Basewithindex
andoffset

X(Ri,Rj )

EA = [Ri ] + [Rj ] + X

Relative

X(PC)

EA = [PC] + X

(Ri )+

EA = [Ri ] ;
Incremen
t Ri

(Ri )

Decremen
t Ri ;
EA = [Ri]

Autoincremen
t
Autodecrement

Indexing and Arrays

Index mode the effective address of the operand is

generated by adding a constant value to the
contents of a register.
Index register
X(Ri): EA = X + [Ri]
The constant X may be given either as an explicit
number or as a symbolic name representing a
numerical value.
If X is shorter than a word, sign-extension is needed.

Indexing and Arrays

In

general, the Index mode facilitates access

to an operand whose location is defined
relative to a reference point within the data
structure in which the operand appears.
Several variations:
(Ri, Rj): EA = [Ri] + [Rj]
X(Ri, Rj): EA = X + [Ri] + [Rj]

Additional Modes

Autoincrement mode the effective address of the operand is the

contents of a register specified in the instruction. After accessing
the operand, the contents of this register are automatically
incremented to point to the next item in a list.
(Ri)+. The increment is 1 for byte-sized operands, 2 for 16-bit
operands, and 4 for 32-bit operands.
Autodecrement mode: -(Ri) decrement first

LOOP

Move
Move
Clear
Add
Decrement
Branch>0
Move

N,R1
#NUM1,R2
R0
(R2)+,R0
R1
LOOP
R0,SUM

Initialization

Figure2.16.TheAutoincrementaddressingmodeusedintheprogramofFigure2.12.