Ahmad Firdaus Bin Zainal Abidin

Faculty of Computer System

and Software Engineering

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Boolean algebra: basis for computer logic design
Transistors: means for implementing Boolean algebra
Switches: on/off to represent the 0’s and 1’s of binary digital circuits
Combined to form logic gates

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 Binary Binary
Digital Digital
Input Output
Signal Gate Signal
.
..

Types of Basic Logic Blocks

• Combinational Logic Block: Logic Blocks whose output logic value
depends only on the input logic values (e.g. AND, OR etc)
• Sequential Logic Block: Logic Blocks whose output logic value depends on
the input values and the state (stored information) of the blocks
 Functions of Gates can be described by:
 Truth Table
 Boolean Function
 Karnaugh Map
Here we see the logic gates that
represent the Boolean operations
previously discussed

XOR looks like OR but with the We typically represent NOR and NAND by the two on the left,
added curved line but the two on the right are also correct
 xy = x x+y=x x bar = NOT x
AND is true only if OR is true if either NOT inverts the bit
both inputs are true inputs are true We will denote x bar as ~x

NOR is NOT of OR NAND is NOT of AND XOR is true if both inputs differ
 xy = x x+y=x x bar = NOT x
AND is true only if OR is true if either NOT inverts the bit
both inputs are true inputs are true We will denote x bar as ~x

NOR is NOT of OR NAND is NOT of AND XOR is true if both inputs differ
  We form Boolean expressions out of Boolean operations on
Boolean variables or Boolean values
 So, like algebraic expressions, we can create more complex Boolean
expressions as we might need

 Consider the expression:

 F = X + ~Y*Z

 What is it’s truth table?

Take note: Notice that it is easier to derive the truth table for
the entire expression by breaking it into subexpressions
So first we determine ~Y
next, ~Y * Z
finally, X + ~Y*Z
 shows how a logic circuit's output responds to various
combinations of the inputs, using logic 1 for true and
logic 0 for false.
 All permutations of the inputs are listed on the left,
and the output of the circuit is listed on the right.
 The desired output can be achieved by a combination
of logic gates.
 A truth table for two inputs is shown, but it can be
extended to any number of inputs. The input columns
are usually constructed in the order of binary
counting with a number of bits equal to the number of
inputs.
 n input variables → 2n
AND and OR gates can have more than 2
inputs, as seen here

Notice for ~Y, we can either use a NOT gate or

simply specify that the value is ~Y

Here is the truth table for this circuit

What does this circuit

compute? (what is F?)
 As with algebra, there will be Boolean operations that
we will want to simplify
 We apply the following Boolean identities to help
 For instance, in algebra, x = y * (z + 0) + (z * 0) can be simplified to just
x=y*z

Here we have an example specifically to see

how DeMorgan’s Law works

DeMorgan’s Law states that ~(X*Y) = ~X+~Y

Boolean expressions are equal if their truth tables give the
same values
https://youtu.be/59BbncMjL8I
Example 1: use algebraic simplification rules Example 3: (x+y)(~x+y)
to reduce ~xyz+~xy~z+xz = ~x(x+y)+y(x+y)
= ~xyz + ~xy~z + xz (distributive)
= ~xx+~xy+xy+yy
= ~xy(z+~z)+xz (distributive law)
(distributive)
= ~xy(1)+xz (inverse law)
= 0+~xy+xy+yy (inverse)
= ~xy+xz (identity law) = ~xy+xy+yy (identity)
= y(~x+x+y) (distributive)
= y(1+y) (inverse)
Example 2: xy+~xz+yz = xy+~xz+yz*1 = y(1) (identity)
(identity) = y (idempotent)
= xy+~xz+yz*(x+~x) (inverse)
= xy+~xz+xyz+~xyz (distributive)
= xy(1+z)+~xz(y+1) (distributive)
= xy(1)+~xz(1) (null)
= xy*1+~xz*1 (absorption)
= xy+~xz (identity)
 NAND (and NOR) have unique properties different from the other
boolean operations
 This allows us to use one or more NAND gates (or one or more NOR gates) and
create gates that can compute AND, OR and NOT
 See the examples below
LOGIC GATES & Boolean Algebra

Early integrated circuits were several gates

on a single chip, you would connect this
chip to other chips by adding wires
between the pins

To do ~(A*B) + ~(C*D)

You would connect A and B to pins 7 and 6,

C and D to 4 and 3, and send 5 and 2 to an
AND chip
Prove? why did we
use NAND

This is a NAND chip

 x y z F
0 0 0 0
Truth 0 0 1 1
Table 0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1

Boolean F = x + ~yz
Function

x
F
Logic y
Diagram
z
Simplification from Boolean
function
Truth Boolean
 Finding an equivalent Table Function
expression that is least Unique Many different
expensive to implement expressions exist

 For a simple function, it is

possible to obtain a simple Truth
expression for low cost Table
Simplified
implementation Karnaugh
Map
Boolean
Function
 But, with complex functions, it is
Boolean
function
a very difficult task

 Karnaugh Map (K-map) is a

simple procedure for
simplifying Boolean expressions.
 Simplification of Boolean functions leads to simpler (and
usually faster) digital circuits.
 Simplifying Boolean functions using identities is time-
consuming and error-prone.
 This special section presents an easy, systematic method
for reducing Boolean expressions.

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 A Kmap is a matrix consisting of rows and columns that represent the
output values of a Boolean function.
 The output values placed in each cell are derived from the minterms of a
Boolean function.
 A minterm is a product term that contains all of the function’s variables
exactly once, either complemented or not complemented.

• For example, the minterms for a function having the

inputs x and y are:
0
1

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 Similarly, a function
having three inputs, has
the minterms that are
shown in this diagram.

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 A Kmap has a cell for each minterm.

 This means that it has a cell for each line for the truth table of a
function.
 The truth table for the function F(x,y) = xy is shown at the right along
with its corresponding Kmap.

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 As another example, we give the truth table and KMap for the function,
F(x,y) = x + y at the right.
 This function is equivalent to the OR / + (add) of all of the minterms that
have a value of 1. Thus:

F(x,y) = x + y

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The rules of Kmap simplification are:
• Groupings can contain only 1s; no 0s.
• Groups can be formed only at right angles; diagonal groups are not
allowed.
• The number of 1s in a group must be a power of 2 – even if it
contains a single 1.
• The groups must be made as large as possible.
• Groups can overlap and wrap around the sides of the Kmap.

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 A Kmap for three variables is constructed as shown in the
diagram below.
 We have placed each minterm in the cell that will hold its
value.
 Notice that the values for the yz combination at the top of
the matrix form a pattern that is not a normal binary
sequence.

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 Consider the function:

 Its Kmap is given below.

 What is the largest group of 1s that is a power of 2?

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 This grouping tells us that changes in the variables x and y
have no influence upon the value of the function: They are
irrelevant. Find only the relevant.
 This means that the function,
reduces to F(x) = z.

We could
verify this
reduction
with
identities or a
truth table.

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Question: Construct a K-map for f (A,B,C,D) = Σ(0, 7, 9, 12, 15)

Answer:

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Recapping the rules of Kmap simplification:
• Groupings can contain only 1s; no 0s.
• Groups can be formed only at right angles; diagonal groups
are not allowed.
• The number of 1s in a group must be a power of 2 – even if
it contains a single 1.
• The groups must be made as large as possible.
• Groups can overlap and wrap around the sides of the Kmap.

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 We will combine logic gates together for
calculations
 Example: ~(A*B) and ~(C*D) with an OR gate
 The resulting circuit is a combinational circuit
 Electrical current flows from one gate to the next
 By combining gates, we can compute a boolean expression
 What we want to do is:
 Derive the boolean expression for some binary calculation (e.g., addition)
 Then build the circuit using the various logic gates
 This is how we will build the digital circuits that make up the ALU (arithmetic-logic unit)
and other parts of the computer
 There are 4 possibilities when adding 2
bits together:
0+0 0+1 1+0 1+1
 In the first case, we have a sum of 0 and a carry
of 0
 In the second and third cases, we have a sum of
1 and a carry of 0
 In the last case, we have a sum of 0 and a carry The truth table for Sum and Carry
of 1 and a circuit to compute these
 These patterns are demonstrated in the truth
table above to the right
 Notice that sum computes the same as XOR
and carry computes the same as AND
 We build an Adder using just one XOR and
one AND gate
 The half adder really only does half the work
 adds 2 bits, but only 2 bits

 If we want to add 2 n-bit numbers, we need

to also include the carry in from the previous
half adder
 So, our circuit becomes more complicated

 In adding 3 bits (one bit from x, one bit from

y, and the carry in from the previous
addition), we have 8 possibilities
 The sum will either be 0 or 1 and the carry out will
either be 0 or 1
 The sum is 1 only if one of x, y and carry in are 1,
or if all three are 1, the sum is 0 otherwise
 The carry out is 1 if two or three of x, y and carry
in were 1, 0 otherwise
 The circuit to the right captures this by using 2 XOR
gates for Sum and 2 AND gates and an OR gate for
Carry Out
 We combine several full adders together to build
an Adder, as shown below:
Called a “ripple” adder because
carrys ripple upward

A 16-bit adder, comprised of 16 Full Adders connected so that each

full adder’s carry out becomes the next full adder’s carry in
 Let’s design another circuit to take a two’s complement
number and negate it (complement it)
 Change a positive number to a negative number
 Change a negative number to a positive number

 Recall to do this, you flip all of the

bits and add 1
 To flip the bits, we pass each bit
through a NOT gate
 To add one, send it to a full adder with
the other number being 000…001
 Recall from chapter 2
 two’s complement subtraction
can be performed by negating
the second number and adding it
to the first
 We revise our adder as shown to the
right
 It can now perform addition (as
normal)
 Or subtraction by sending the second
number through the complementor

The switch (SW) is a multiplexer,

covered in a few slides
 We have covered + and -, how about <, >, =
 To compare A to B, we use a simple tactic
 Compute A – B and look at the result
 if the result is -, then A < B
 if the result is 0, then A = B
 if the result is +, then A > B
 if the result is not 0, then A != B
 how do we determine if the result is -? look at the sign bit, if the sign bit is 1, then the result is
negative and A < B
 how do we determine if the result is 0? are all bits of the result 0? if so, then the result is 0 and A =
B
 we will build a zero tester which is simply going to NOR all of the bits together
 how do we determine if the result is +? if the result of A – B is not negative and not 0, it must be
positive, so we negate the results of the first two and pass them through an AND gate
 The comparator circuit is shown above (notice that the circuit outputs 3 values, only
1 of which will be a 1, the others must be 0)
 NOTE: to compute !=, we can simply negate the Zero output
 The circuit below is a multiplication circuit
 Given two values, the multiplicand and the multiplier, both stored in
temporary registers
 The addition takes place by checking the Q0 bit and deciding whether to
add the multiplicand to the register A or not, followed by right shifting the
carry bit, A and Q together

 shift/add control logic

 set counter = n
 compare Q0 to 1
 if equal, signal adder to
add
 signal the shifter to shift
 decrement counter
 repeat until counter = 0
 The Decoder is a circuit that takes a binary pattern and translates it
into a single output
 This is often used to convert a binary value into a decimal value
 For an n-bit input, there are 2n outputs
 Below is a 2 input – 4 output decoder
 if input = 01, the second line (x*~y) on the right has current
 the line 01 would be considered line 1, where we start counting at 0
Octal-to-Binary Encoder

D1
A0
D2
D3 A1
D4
D5 A2
D6
D7

2-to-4 Decoder D0

E A1 A0 D0 D1 D2 D3 A0 D1
0 0 0 0 1 1 1 D2
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0 A1 D3
1 d d 1 1 1 1 E
  Multiplexer (abbreviated as MUX) is used to select
from a group of inputs which one to pass on as output
 Here, 1 of 4 single-bit inputs is passed on using a 2-bit
selector (00 for input 0, 01 for input 1,10 for input 2, 11 for
input 3)
 While this circuit is more complex than previous ones, this is
simplified for a MUX – imagine what it would look like if we
wanted to pass on 16 bits from 1 of 4 inputs

A related circuit is the demultiplexer (DEMUX) – it receives 1 input and a select and passes the input onto one of several outputs
Putting all these ideas
together

We have a 2-bit ALU

Given 2 values, A and B,

each
of which are 2 bits (A0, A1,
B0, B1) and a selection from
the control unit (f0, f1)

This circuit computes

A+B (if f0 f1 = 00)
NOT A (if f0 f1 = 01)
A OR B (if f0 f1 = 10)
A AND B (if f0 f1 = 11)

And passes the result out as

C0 C1 along with overflow if
the addition caused an
overflow