Boolean Algebra & Logic Gates
Boolean Algebra & Logic Gates
Boolean Algebra & Logic Gates
Basic Definitions
Theorems a and b
x+x =x
x + x = (x + x) 1 by postulate 2(b)
= (x + x) (x + x’) by postulate 5(a)
= x + xx’ by postulate 4(b)
=x+0 by postulate 5(b)
=x by postulate 2(a)
Operator Precedence
Parenthesis
NOT
AND
OR
Venn Diagram
x y
xy’ xy x’y
x’y’
Boolean Function
z F
x + x’y = (x + x’)(x + y) = 1 (x + y) = x + y
x(x’ + y) = xx’ + xy = 0 + xy = xy
x’y’z + x’yz + xy’ = x’z(y’ + y) + xy’ = x’z + xy’
xy + x’z + yz = xy + x’z + yz(x + x’)
= xy + x’z + xyz + x’yz
= xy(1 + z) + x’z(1 + y)
= xy + x’z
(x + y)(x’ + z)(y + z) = (x + y)(x’ + z) by duality.
Complement of a Function
Minterms Maxterms
xyz Term Designation Term Designation
000 x’y’z’ mo x+y+z Mo
001 x’y’z m1 x+y+z’ M1
010 x’yz’ m2 x+y’+z M2
011 x’yz m3 x+y’+z’ M3
100 xy’z’ m4 x’+y+z M4
101 xy’z m5 x’+y+z’ M5
110 xyz’ m6 x’+y’+z M6
111 xyz m7 x’+y’+z’ M7
Canonical Form
x y F
0 0 0
0 1 0
1 0 0
1 1 1
OR
x y F
0 0 0
0 1 1
1 0 1
1 1 1
INVERTER
x F
0 1
1 0
BUFFER
x F
0 0
1 1
NAND
x y F
0 0 1
0 1 1
1 0 1
1 1 0
NOR
x y F
0 0 1
0 1 0
1 0 0
1 1 0
XOR
x y F
0 0 0
0 1 1
1 0 1
1 1 0
XNOR
x y F
0 0 1
0 1 0
1 0 0
1 1 1
Positive and negative logic
IC DIGITAL LOGIC FAMILIES
TTL
ECL
MOS
CMOS
I2L
Special Characteristics
Fan-out
It specifies the number of standard loads that the
output of a gate can drive without impairing its
normal operation.
Power dissipation
Propogation delay
Noise Margin
End of Chapter 2