8051 Interrupts

• Interrupt- Facility provided in microprocessor using

which attention of microprocessor may be drawn for
some specific purpose.
• Microprocessor suspends its current job- saves the
status.
• Microprocessor attends to the
device/system/event causing interrupt- ISR is
executed.
• Microprocessor goes back to suspended job and
starts executing from the point where it was
suspended.
 Interrupt Requested

µp normal Program
Execution
Normal Program
execution

Interrupt service Routine executed

• One to one correspondance between Interrupt and

ISR i.e. for each interrupt- ISR is specified and stored
in memory.
• For a microprocessor having n ISR-n XXn

interrupts.
• XX1, XX2---------XXn address of ISR-2 XX2
ISR in memory. ISR-1 XX1
• When – Interrupt ‘K’ occurs ISR-K for interrupt is
executed by loading address XXK in PC.
• XX1 - ------XXn – starting address of ISR for interrupts.
vector addresses of Interrupts.
Other issues in Interrupts
 Hardware/Software Interrupts
 Interrupt Priority
 Enabling / Disabling of Interrupts.
 Masking of Interrupts.
 Edge/Level Triggered Hardware Interrupts
• 8051 has five interrupt sources.
• Each interrupt can be programmed to two priority
levels.
INT0 – External Request from P3.2 pin
Timer 0 – Overflow from Timer 0 activates
interrupt request flag TF0.
INT1 – External Request from P3.3
Timer1- Overflow from Timer1 activates
interrupt request flag TF1
Serial Port – completion of transmission or
reception of a serial frame activates the flags TI
or RI.
• The complete interrupt system may be disabled or
enabled by storing 0 or 1 in EA bit of IE SFR
- IE.7.
SETB IE.7, - Enable Interrupts
CLR IE.7, - Disable Interrupts
• When Interrupt system is enabled i.e. IE.7=1, then
each of the five interrupts can be enabled/disabled
individually by making a specified bit in IE register as
1 or 0.
- Interrupt masking
bit = 0 – Interrupt is disabled i.e. masked
bit = 1 – Interrupt is enabled
IE Register – Interrupt Enable Register
7 6 5 4 3 2 1 0
EA X X ES ET1 EX1 ET0 EX0

EX0- Enable/Disable – External Interrupt 0

ET0- Enable/Disable – Timer 0 overflow Interrupt
EX1- Enable/Disable – External Interrupt 1
ET1- Enable/Disable – Timer 1 overflow Interrupt
ES -Enable/Disable – Serial port Interrupt
EA - Enable/Disable – All interrupts
Examples –
-Disable all interrupts
CLR IE.7
- Enable external interrupt 1 and Timer 0 overflow
interrupt
IE = 1 0 0 0 0 1 1 0 = 86H
MOV A, # 86H
or
MOV IE, A MOV IE, # 86H
Interrupt Priority –
• There are two priority levels for interrupts in 8051-
High and Low.
• Each interrupt can be programmed to a low or high
priority level, by making bits of IP(Interrupt Priority)
SFR as 0 or 1.
bit = 0 – Interrupt at Low priority level.
bit = 1 – Interrupt at High priority level.
Interrupt Priority Register
7 6 5 4 3 2 1 0
IP - X X X PS PT1 PX1 PT0 PX0

PX0 – Priority – External Interrupt 0

PT0 – Priority – Timer 0 overflow
PX1 – Priority – External Interrupt 1
PT1 – Priority – Timer 1 overflow
PS - Priority – Serial port Interrupt
Example – To place Timer 0, external interrupt 1 at high
priority and other interrupts at low priority.
IP = 0000 0110 = 06H SETB IP.1
or
MOV IP, # 06H SETB IP.2
• A low priority interrupt can’t interrupt a high priority
interrupt but a high priority interrupt can interrupt
low priority interrupt.
• In the above example –
(i) 8051 is executing ISR for serial port interrupt
i.e. it is servicing serial port interrupt.
- If interrupt request at external interrupt 01
occurs since it is at high level, the 8051 will be
interrupted.
(ii) 8051 is executing ISR for timer 0.
- An interrupt request at external interrupt 0 will
not interrupt 8051 since EX0 is at low level
- For interrupts which are programmed at same
priority level, following rule is applied.
 Source Priority Level
- External Interrupt 0 - Highest
- Timer 0 Overflow -
- External Interrupt 1 -
- Timer 1 Overflow -
- Serial Port - Lowest
• When two or more interrupt requests come at the
same time and all the interrupts at the same priority
level the 8051 will select an interrupt for servicing
based on above.
• All the interrupts are separately scanned during each
m/c cycle.
• An interrupt request will be serviced i.e.
corresponding ISR will be executed unless-
• An interrupt of equal or higher level is already
in progress.
• Current m/c cycle is not the final m/c cycle in
the execution of instruction in progress i.e. no
interrupt request will be responded to until the
instruction in progress in completed.
Edge/Level Triggered Interrupts :-
• In 8051, external interrupts i.e. INT0 and INT1 can be
programmed to be low level triggered or high to low
edge triggered.
• Level triggered – When signal at INT0 or INT1 is low-
interrupt is caused.
• Edge Triggered – When signal at INT0 or INT1
becomes low from high-interrupt is caused.
• Bits 0 to 3 of TCON register are used for
programming level or edge triggered interrupts.
TCON :-
7 6 5 4 3 2 1 0
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

• IT0 (TCON.0) and IT1 (TCON.2) are used for

Level/Edge triggered programming.
When IT0 = 0 INT0 is Low Level triggered
IT0 = 1 INT0 is High to Low edge triggered
IT1 = 0 INT1 Low level triggered
IT1 = 1 INT1 High to Low edge triggered
• When edge triggered external interrupt occurs
• Hardware will set the flag IE0 (TCON.1) for INT0 and
IE1(TCON.3) for INT1.
• In case of edge triggered interrupts, occurrence of
interrupt needs to be saved.
• The ISR location for each interrupt is predefined in
8051.
Source ISR Location
External Interrupt 0 - 0003H
Timer 0 Overflow - 000BH
Ext. Interrupt 1 - 0013H
Timer 1 Overflow - 001BH
Serial Port - 0023H
• The ISR must start at these locations and jump to
another memory location if it is bigger.
For Example:- ORG 0013H
SJMP NIMT1.
NIMT1 :-
 Programming
External Interrupts :- In a plant when there is gas
leakage, the gas detector sends a high to low
interrupt on INT0. The 8051 (12MHz clock) starts
water spray by sending control signal (5V) to P0.1
and sends alarm signal by blinking LED connected to
P2.0(Common Anode)
Main Program :-
ORG 00
SJMP 030H
ORG 030H
; Enable Interrupt INT0
IE EA X X ES ET1 EX1 ET0 EX0

= 1000 0001 = 81H

MOV IE, # 81H
; Program INT0 to edge triggered by making IT0=1 i.e.
(TCON.0=1)
SETB TCON.0[ or SETB IT0]
; Set INT0 to high priority
IP = X X X PS PT1 PX1 PT0 PX0

MOV IP, # 01H [or SETB IP.0]

SJMP $
ISR for INT0
ORG 0003H
SJMP NXINT0
NXINT0: SETB P0.1
MOV R3, # 100
REPET: CLR P2.0
ACALL DEL1S
SETB P2.0
DJNZ R3, REPET
RETI
DEL1S:- Delay of 1second
RET
Timer Interrupt:- In a Rly station when a train passes a
signal point, P0.2 line of 8051 becomes 1. 8051 waits
for 30 seconds and watches P1.2 line which may be
activated by station master. If not activated in 30
sec., 8051 sends all clear signal by lighting LED
connected to P1.7, to enable other trains to come.
Note:- Station master will activated P1.2 if any coach of
train is left out.
• 8051 is having 12MHz clock 12 oscillator m/c cycle.
• Delay calculation
12 MHz clock.
1 m/c cycle = 12/12 µsec. = 1µsec.
• Use Timer 0 as Timer for delay
• Timer 0 ISR will light LED connected to P1.7 if P1.2=0
Mode = 01 16 bit timer
count = 0000 to FFFF i.e. 216 µsec= 1 Overflow
1 Overflow = 65536 count
30 x 106 µsec = 65536 x n
n = 457.76 = 458 times overflow
= 2 x 229 times overflow
Main Program:-
ORG 0000H
SJMP 0030H
ORG 0030H
 Timer 0
TMOD = GATE C/ T M1 M0 = 01H

MOV TMOD, # 01H

MOV R3, # 229
MOV R4, #2
JNB P0.2, $
MOV TL0, # 00
MOV TH0, # 00
; Enable Interrupt –
SETB IE.7
[ MOV IE, # 82H]
SETB IE.1
; Set priority -
SETB IP.1
; Clear Interrupt flag
CLR TF0 [TCON.5]
; Initiate Timer 0
SETB TR0 [TCON.4]
SJMP $
Timer – 0 ISR
ORG 000BH
; Timer interrupt has to cause repeated interrupts – 458 i.e. 2 x
229 times.
; Check if R3= 0
DEC R3
CJNE R3, #00, KK1
DEC R4
 CJNE R4,# 00 , KK2
JNB P1.2 , KK3
; Station master has activated P1.2
SJMP KK4
KK2: MOV R3, # 229
SJMP KK1
KK3: SETB P1.7
SJMP KK4
KK1: MOV TL0, # 00
MOV TH0, # 00
CLR TF0 ; clear flag
SETB TR0 – initiate timer 0
MOV IE, # 82H; Enable Interrupt
KK4: RETI
Timer Interrupt:- Generate a pulse train of 1KHz at P1.0
using timer 0, (12 MHz clock frequency.)
Delay calculation:-
1 m/c cycle = 1 µsec.
1KHz = 103Hz =103 cycles per sec.

1 clock period = 10-3 sec = 1 msec.

UP time = 0.5 milli sec.
DN time = 0.5 milli sec.
 1 m/c cycle = 1 µsec
0.5 milli sec. = 0.5 x103 m/c cycle
= 500 m/c cycle
For mode = 01 – 16 bit counter
Preset value – 65535-500=65035 = FE0BH
Considering additional m/c cycle for roll over
Preset value = FE0CH
Main Program:-
; Program timer mode.
Gate C/T M1 M0
TMOD = 0 0 0 0 0 0 0 1 = 01H
 MOV TMOD , # 01H
; Load preset value
MOV TL0, # 0CH
MOV TH0, # FEH
; Clear Timer 0 control interrupt bit TF0
CLR TF0 [ CLR TCON.5]
; Enable Timer 0 interrupt
EA ET0 EX0
1 0 0 1 0
IE = = 82H
MOV IE, # 82H
; Set priority for Timer 0 interrupt
PTO PXO
0 0 1 0
IP = = 02H
Note : - Timer 0, Timer 1 and serial port interrupts are
generated internally. Thus level / Edge trigger
programming is not required.
; Set P1.0 to low level
CLR P1.0
; Initiate Timer 0
SETB TR0[SETB TCON.4]
SJMP $
Timer 0 ISR
ORG 000BH
SJMP TMR0
 TMR0: CPL P1.0
; Enable Timer 0 interrupt
MOV IE, #82H
; Clear TF0
CLR TF0[TCON.5]
; Reload value
MOV TL0, # 0BH
MOV TH0,# FEH
Initiate Timer 0
SETB TR0[TCON.4]
RETI
Serial Port Interrupt
Note :- Two flags TI (Transmission) and (RI) Reception are
there.
- Both cause only one interrupt
- Serial Port Interrupt
T1
- Serial Port Interrupt
R1

- Thus in ISR , You have to check the status of RI and TI

to know whether Transmit or Receive Interrupt has
occurred.
Example
Send 10 bytes of data stored at location 0030H
onwards serially in mode1 (8 bits start- stop) at
baud rate 4800.8051 has clock frequency of
11.0592MHz
Main Program
ORG 00H
SJMP 030H
ORG 030H
MOV R2, # 00H – for count
; Set mode, =01, SM0, SM1 =01
REN = 1
7 6 5 4 3 2 1 0
SCON = SM0 SM1 SM2 REN TB8 RB8 T1 RI
0 1 0 1 0 0 0 0

=50H
MOV SCON, #50H
; Enable Serial Interrupt.

7 6 5 4 3 2 1 0
IE = EA X X ES ET1 EX1 ET0 EX0
1 0 0 1 0 0 0 0

= 90H
MOV IE, # 90H
; Set Priority as High
7 6 5 4 3 2 1 0
X X X PS PT1 Px1 PT0 PX0
IP =
0 0 0 1 0 0 0 0

=10H
MOV IP, # 10H
; Set Timer 1 to mode 2 Auto read
TMOD = Timer 1 Timer 0
Gate C/T M1 M0
0 0 1 0

MOV TMOD, #20H

; Load Preset value, in TH1
; Preset value for 4800 = -6 decimal or FAH
MOV TH1, # FAH [MOV TH1 , # -6]
; Load byte to be transmitted to SBUF
Loop1: MOV A, R2
ADD A, #30H
MOV R0, A
MOV A,@ R0
MOV SBUF, A
; Clear TI and RI flags
CLR TI [CLR SCON.1]
CLR RI [CLR SCON.0]
; Initiate Timer 1
CLR TF1 [SETB TCON.7]
SETB TR1 [SETB TCON.6]
; At 4800 baud the 10 bit transmission
; will take 10/4800 sec = 1000/480 ≈ 2 msecond
; We need to give delay of 2ms . and then
; Check TI bit to find if the
; transmission is complete
[ ACALL DEL 2MS ]
JNB TI, $
CLR TI
; Load next byte.
INC R2
CJNE R2, # 11, Loop1
SJMP $
ISR Serial Interrupt
ORG 0023 H
SJMP SRINT
; Enable serial Interrupt
SRINT: MOV IE, #90H
; Initiate Timer 1
CLR TF1
SETB TR1
RETI
; Similar steps to receive 20 byte of data and store in
memory.