OPERATING SYSTEMS

CSE 4300
Instructor:Mohammad Maifi Hasan Khan

Chapter 5
Input/Output
I/O Devices

• Block Devices
– Info in fixed size
• Character Device
– Accepts stream of
character, keyboard
• Clock??
• Device Controller
– Convert streams of bits in
block of bytes
– Perform error correction
• Controller’s job –
– Convert the serial bits stream into a block of bytes
– Perform error checking and correction
– Copy to main memory
How to communicate with Device
Controllers?
• Option – I
– Each control register assigned a I/O port number (I/O port space)
– IN REG, PORT / OUT PORT, REG
• Option – II
– Map control registers to memory space
– Each register assigned a unique memory address to which no
memory is assigned
 Memory-Mapped I/O (1)
(A)
IN REG, PORT
OUT PORT, REG

IN R0, 4
MOV R0,4
Two different things!

(a) Separate I/O and memory space.

(b) Memory-mapped I/O.
(c) Memory mapped I/O data buffers and separate I/O ports
Advantage of Memory-Mapped I/O
Advantage of Memory Mapped:
- Does not require special assembly code to access
devices
- Device driver can be written entirely in C
- No special protection mechanism is needed
- Every instruction that can reference memory, can
access control register
- Makes checking device status more efficient

LOOP: TEST PORT_4

BEQ READY
BRANCH LOOP

READY:
Disadvantage of Memory-Mapped I/O
- Caching of memory words
LOOP: TEST PORT_4
BEQ READY
BRANCH LOOP

READY:
- Requires selectively disabling caching
 Memory-Mapped I/O (2)
-Having multiple bus makes it harder to inspect
every memory reference
-Option 1: Send all addresses to memory first,
if fail to respond, send to other buses
-Option 2: Snooping device
-Option 3: Filter address in PCI bridge
chip: Uses range registers to check

(a) A single-bus architecture.

(b) A dual-bus memory architecture.
 Buses

The structure of a large Pentium system

Direct Memory Access (DMA)
Direct Memory Access (DMA)

Operation of a DMA transfer.

 DMA
If DMA not used:
- Disk controller reads the block in internal buffer
- Check for error
- Causes interrupt
- OS read data from internal buffer to memory
If DMA Used
- CPU programs the DMA controller (address register, count, control
registers) and instructs disk controller to read data from disk
- DMA controller commands disk controller and initiates the transfer to
memory
- Disk controller writes to memory and notifies DMA controller
- DMA controller repeats until done
- DMA raises interrupt to CPU
• DMA controller may have multiple channels for
multiple devices
– Round-robin scheduling inside
• Operation of Bus
– Word at a time (cycle stealing)
– Burst mode
• More efficient than cycle stealing
• Can block CPU for long time
– Fly-by-mode
• Copy directly to main memory or to DMA
• Internal buffering inside disk controller
– Error checking
– Prevent overflowing due to busy bus
 Interrupts Revisited

How an interrupt happens. The connections between the devices and the interrupt
controller actually use interrupt lines on the bus rather than dedicated wires.
• I/O Device raises interrupt by asserting a signal on a bus line
• If no other interrupt pending, interrupt controller
handles the interrupt by putting a number on address line and
asserts a signal to interrupt the CPU
• Address on the bus is used as an index to interrupt vector table
• Gets the new PC from the table
• The interrupt service procedure acknowledge the interrupt by
writing a value to interrupt controller’s I/O port
 Interrupt Handlers (1)
1. Save registers not already been saved by
interrupt hardware.
2. Set up a context for the interrupt service
procedure.
3. Set up a stack for the interrupt service procedure.
4. Acknowledge the interrupt controller. If there is no
centralized interrupt controller, reenable
interrupts.
5. Copy the registers from where they were saved to
the process table.
 Interrupt Handlers (2)
6. Run the interrupt service procedure.
7. Choose which process to run next.
8. Set up the MMU context for the process to run
next.
9. Load the new process’ registers, including its
PSW.
10. Start running the new process.
Precise and Imprecise Interrupts (1)
Properties of a precise interrupt

1. PC (Program Counter) is saved in a known place.

2. All instructions before the one pointed to by the PC
have fully executed.
3. No instruction beyond the one pointed to by the
PC has been executed.
4. Execution state of the instruction pointed to by the
PC is known.
Precise and Imprecise Interrupts (2)
Intel supports precise interrupt!
Implemented in complex circuit 

(a) A precise interrupt. (b) An imprecise interrupt.

Principles of I/O Software
 Goals of the I/O Software
• Device independence: Same program can read file
from CD ROM, H/D etx.
• Uniform naming
• Error handling as close to hardware as possible
• Synchronous (blocking) vs asynchronous
• Buffering: network pkt, audio stream
Programmed I/O (1)

Steps in printing a string.

 Programmed I/O (2)

Writing a string to the printer using programmed I/O.

 Programmed I/O (2)

Tie up the CPU until the whole I/O is done 

Writing a string to the printer using programmed I/O.
 Interrupt-Driven I/O

Writing a string to the printer using interrupt-driven I/O. (a) Code executed at the time
the print system call is made. (b) Interrupt service procedure for the printer.
 Interrupt-Driven I/O

ch ar ac t e r!
t s o c cu r on every
Interru p

Writing a string to the printer using interrupt-driven I/O. (a) Code executed at the time
the print system call is made. (b) Interrupt service procedure for the printer.
 I/O Using DMA

Printing a string using DMA. (a) Code executed when the print
system call is made. (b) Interrupt service procedure.
 I/O Using DMA

e de v ic e, pe r for m ance slow

n th
If DMA is slower tha

Printing a string using DMA. (a) Code executed when the print
system call is made. (b) Interrupt service procedure.
Let us look at some real devices!

• Magnetic Disk
• Clocks
• Keyboards
• Displays
 Magnetic Disks (1)

Disk parameters for the original IBM PC 360-KB floppy disk and a
Western Digital WD 18300 hard disk.
 Magnetic Disks (2)

z s ecto r s/ track
li n d er s, y heads,
is i ns tr u c te d x cy
The softwa
re
t r o lle r r e m aps!
Con

(a) Physical geometry of a disk with two zones.

(b) A possible virtual geometry for this disk.
Disk Formatting

A disk sector.
Disk Formatting

Cylinder skew?

An illustration of cylinder skew.

 Disk Formatting
What if only “one sector” buffer in disk controller?

No interleaving is needed if controller can buffer one

whole track!
(a) No interleaving. (b) Single interleaving.
(c) Double interleaving.
Disk Arm Scheduling Algorithms

Read/write time factors

1. Seek time (the time to move the arm to the
proper cylinder).
2. Rotational delay (the time for the proper sector
to rotate under the head).
3. Actual data transfer time.
Disk Arm Scheduling Algorithms
Initial position: 11
Requests: 1, 36, 16, 34, 9, 12
FCFS: arm motion: 10,35,20,18,25,3
SSF: 12,9,16,1,34,36
Arm motion: 1,3,7,15,33,2
Problem?

Shortest Seek First (SSF) disk scheduling algorithm.

Disk Arm Scheduling Algorithms
Initial position: 11
Requests: 1, 36, 16, 34, 9, 12
rs w i ll su ffer FCFS: arm motion: 10,35,20,18,25,3
de
Edge cylin SSF: 12,9,16,1,34,36
Arm motion: 1,3,7,15,33,2
Problem?

Shortest Seek First (SSF) disk scheduling algorithm.

Disk Arm Scheduling Algorithms
Elevator Algorithm
Current Direction: UP/DOWN
Upper bound fixed: twice the number of cylinders

The elevator algorithm for scheduling disk requests.

 Bad Sector Error Handling
Two approaches:
• Deal in Controller
– Before disk is shipped, make a list of bad sector and
write on disk
– Use spare sectors as substitute
– Use internal table for mapping
• Deal in OS
– Errors may develop after shipped
– OS can build a mapping table of bad sectors
– Bad sectors can not occur in files or list of free
sectors
 Error Handling

(a) A disk track with a bad sector.

(b) Substituting a spare for the bad sector.
(c) Shifting all the sectors to bypass the bad one.
 Seek Error
• Caused by mechanical problems in the disk arm
• Recalibrating command is used to correct
misalignment
 Stable Storage (1)
ECC is not enough!
Operations for stable storage using identical
disks:
1. Stable writes
1. Write to disk 1, reread, then write to disk 2 and reread
2. Stable reads
1. Read from disk 1, and check ECC. If wrong, try disk 2
3. Crash recovery
1. Overwrite the data from disk with correct ECC
2. If both are correct but different, overwrite disk 2’s data with
disk 1’s data
 Stable Storage (2)

Analysis of the influence of crashes on stable writes.

 RAID (1): Redundant Array of
Inexpensive (Independent?) Disks
One RAID SCSI controller • Level 0: Sectors 0 – k-1 in strip 0 etc.
and a box of SCSI disks • Stripping: Distributing data over
multiple drives
• Works best with large request
• Performance excellent, implementation easy
• What if OS asks for data one sector at a time?
• Reliability compared to a single disk?

RAID levels 0 through 5.

Backup and parity drives are shown shaded.
 RAID (1): Redundant Array of
Inexpensive (Independent?) Disks
One RAID SCSI controller • Level 1: duplicate everything
and a box of SCSI disks • Read performance twice of Level 0
• Write same as Level 0
• Reliability?

RAID levels 0 through 5.

Backup and parity drives are shown shaded.
 RAID (1): Redundant Array of
Inexpensive (Independent?) Disks
One RAID SCSI controller • Level 2: split data at word/byte level
and a box of SCSI disks • Imagine 4 bits + hamming code, bits 1, 2,
4 parity bits
• Thinking machine CM-2
• 32 bits + 6 bit hamming code + 1 bit
parity
• Write 32 sectors worth of data in one
sector time
• Excellent fault tolerance
• All the drives need to be rotationally
synchronized
• Lot of overhead for parity check
• Lots of disks

RAID levels 0 through 5.

Backup and parity drives are shown shaded.
 RAID (2)
• Level 3: Simplified version of level 2
• Single parity bit per word
• 1 bit error detection for random errors
• 1 bit error correction for disk crash
• All the drives need to be rotationally
synchronized

RAID levels 0 through 5.

Backup and parity drives are shown shaded.
 RAID (2)
• Level 4: strip mechanism. Similar to Raid 0
• Parity for all strip
• Takes exclusive OR. If each strip is k bytes
long, parity strip is k bytes long
• Can recover from drive crashes
• Poor performance for update. Need to read
back all drives and re-compute parity
• Parity disk bottleneck

RAID levels 0 through 5.

Backup and parity drives are shown shaded.
 RAID (2)
• Level 5: distribute parity over multiple
drive
• Recovering from crash is complex

RAID levels 0 through 5.

Backup and parity drives are shown shaded.
 Clock Hardware
One shot mode: copy from holding register to counter and

decrement at each pulse. Once 0, causes an interrupt

Square wave mode: Keep repeating the process

A programmable clock.
 Clock Software
Typical duties of a clock driver
1. Maintaining the time of day.
2. Preventing processes from running longer than
they are allowed to.
3. Accounting for CPU usage.
4. Handling alarm system call made by user
processes.
5. Providing watchdog timers for parts of the
system itself.
Task 1 Maintaining the time of day.
Task 2 Preventing processes from running longer
than they are allowed to.

1. Scheduler initializes a counter to the value of that process's quantum

in clock ticks
2. At every clock interrupt, clock driver decrements the counter by 1
3. Once the counter becomes 0, clock driver calls the scheduler
Task 3: Accounting for CPU usage

Start a second timer whenever a process is started

and stopped when the process stops. Need to be
saved and restored when interrupts come in.
Task 4 Handling alarm system call made by user
processes.

Example scenario:
Ack not received within certain time

Simulating multiple timers with a single clock.

Task 5 Providing watchdog timers for parts of the
system itself.

Example Scenario
Floppy disk startup
Soft Timers (Aron and Druschel 1999)
Main Idea:
Two ways for I/O.
•Polling: Delay in response.
•Interrupt: Too much overhead due to context switch (pipeline, TLB, cache ).

Soft timers succeed according to rate at which kernel entries are made
because of:
1.System calls.
2.TLB misses.
3.Page faults.
4.I/O interrupts.
5.The CPU going idle.

During periods when no system calls, a second low-frequency hardware

timer can be used.
 Power Management
Hardware Issues

Power consumption of various parts of a notebook computer.

 Power Management
The Display

The use of zones for backlighting the display.

(a) When window 2 is selected it is not moved.
(b) When window 1 is selected, it moves to reduce the number of zones illuminated.
 Power Management
The CPU

(a) Running at full clock speed. (b) Cutting voltage by two cuts
clock speed by two and power consumption by four.
I/O Software Layers

Layers of the I/O software system.

User-Space I/O Software

Layers of the I/O system and the

main functions of each layer.
Rest of the Slides are for Fun
Reading!
Not included in the exam.
Device-Independent I/O Software

Functions of the device-independent I/O software.

Uniform Interfacing for Device Drivers

(a) Without a standard driver interface.

(b) With a standard driver interface.
 Buffering (1)

(a) Unbuffered input. (b) Buffering in user space.

(c) Buffering in the kernel followed by copying to user space. (d) Double buffering in the
kernel.
 Buffering (2)

Networking may involve many copies of a packet.

 CD-ROMs (1)

Recording structure of a compact disc or CD-ROM.

 CD-ROMs (2)

Logical data layout on a CD-ROM.

 CD-Recordables (1)

Cross section of a CD-R disk and laser. A silver

CD-ROM has similar structure, except without dye layer and with pitted aluminum layer
instead of gold layer.
 DVD (1)

DVD Improvements on CDs

1. Smaller pits
(0.4 microns versus 0.8 microns for CDs).
2. A tighter spiral
(0.74 microns between tracks versus 1.6
microns for CDs).
3. A red laser
(at 0.65 microns versus 0.78 microns for CDs).
 DVD (2)

DVD Formats

1. Single-sided, single-layer (4.7 GB).

2. Single-sided, dual-layer (8.5 GB).
3. Double-sided, single-layer (9.4 GB).
4. Double-sided, dual-layer (17 GB).
 DVD (3)

A double-sided, dual-layer DVD disk.