IC

Technology

Dr. Sachin D. Pabale

Matosri College of Engineering
and Research Centre,
Nasik
 The IC Market
The semiconductor industry is approaching $300B/yr in sales

Military
2%
Communications
24%

Computers
42%

Industrial
8%
Transportation 8% Consumer Electronics
Courtesy of Dr. Bill Flounders, UC Berkeley
16%
Microlab
 IC
What advantages do ICs have over discrete components?
Technology
 Size: Sub-micron vs. millimeter/centimeter.

 Speed and Power: Smaller size of IC components yields higher speed and
lower power consumption due to smaller parasitic resistances, capacitances
and inductances.

Switching between ‘0’ and ‘1’ much faster on chip than between chips.

Lower power consumption => less heat => cheaper power supplies=>
reduced system cost.

 Integrated circuit manufacturing is versatile. Simply change the mask to

change the design.

However, designing the layout (changing the masks) is usually the most
time consuming task in IC design.
 IC Technology
Invention
Early developments of the Integrated Circuit (IC) go
back to 1949.

German engineer Werner Jacobi filed a patent for an IC

like semiconductor amplifying device showing five
transistors on a common substrate in a 2-stage
amplifier arrangement.

Jacobi disclosed small cheap of hearing aids.

 Inventor Year Circuit Remark
Fleming 1904
1906
Vacuum tube diode large expensive, power-
hungry, unreliable
Vacuum triode
William Shockley 1945 Semiconductor replacing
(Bell labs) vacuum tube
Bardeen and 1947 Point Contact transfer Driving factor of growth
Brattain and resistance device “BJT” of the VLSI technology
Shockley (Bell labs)

Werner Jacobi 1949 1st IC containing No commercial use

(Siemens AG) amplifying Device 2stage reported
amplifier
Shockley 1951 Junction Transistor “Practical form of
transistor”
Jack Kilby July 1958 Integrated Circuits F/F Father of IC design
(Texas Instruments) With 2-T Germanium
slice and gold wires
 IC
Inventor Year Circuit
Technology Remark
Noyce Fairchild Semic Dec. 1958 Integrated Circuits “The Mayor of
onductor Silicon Silicon Valley”

Kahng Bell Lab 1960 First MOSFET Start of new era for
semiconductor
industry
Fairchild Semicond 1061 First Commercial
uctor And Texas IC

Frank Wanlass 1963 CMOS

(Fairchild Semiconductor)
Federico Faggin 1968 Silicon gate IC Later Joined Intel to
technology lead first CPU Intel
(Fairchild Semiconductor) 4004 in 1970
2300 T on 9mm2
Zarlink Recently M2A capsule for take photographs of
Semiconductors endoscopy digestive tract 2/sec.
 Line Transis Cell Construction Layers Die
Product Process width tors (K) Mask size
type layers Proc/bus Clock Voltage Cache (mm
(µm) Poly Metal
(bits) (MHz) (V) (Kbits) )

1971 4004 PMOS 10 2.3 --- 4 0.108 12 0 1 1 13.5

1972 8008 PMOS 10 3.5 --- 8 0.2 12 0 1 1 15.2
1974 8080 NMOS 6.0 6.0 --- 8 2 12 0 1 1 20.0
1976 8085 NMOS 3.0 6.5 --- 8 0.37 5 0 1 1 20.0
1978 8086 NMOS 3.0 29 --- 16 5-10 5 0 1 1 28.6
1979 8088 NMOS 3.0 29 --- 16/8 5-8 5 0 1 1 28.6
1982 80286 CMOS 1.5 134 --- 16 6-12 5 0 1 2 68.7
1985 80386DX CMOS 1.5 275 10 32 16-33 5 0 1 2 104.0
1989 80486DX CMOS 1.0 1,200 12 32 25-50 5 0 1 3 163.0
1992 80486DX2 CMOS 0.8 1,200 --- 32 50-66 5 0 1 3 81.0
1993 Pentium BiCMOS 0.8 3,100 18 32/64 60-66 5 0 1 3 264.0
1994 80486DX4 CMOS 0.5 1,600 32 75-100 5 0 1 3
Pentium 150-
1995 BiCMOS 0.35 5,500 20 32/64 --- 0 1 4 310.0
Pro 200
233-
1997 Pentium II CMOS 0.35 7,500 16 32/64 --- 0 1 4 209.0
300
300-
1998 Celeron CMOS 0.25 19,000 19 32/64 --- 128 1 5
333
Pentium III 500-
1999 CMOS 0.18 28,000 21 32/64 --- 256 1 6 140.0
733
1,400-
2000 Pentium 4 CMOS 0.18 42,000 21 32/64 --- 256 1 6 224
1,500
 How semiconductor industry have
achieved the complex integrated
circuits?

1. Moore’s Law.
2. Continuous technology Scaling.
 1965 - Moore's law
"Cramming more components onto integrated
circuits".

Gordon E. Moore - Chairman Emeritus of Intel Corporation

 1965 - observed trends in industry - of transistors on ICs vs.
release dates:
 Noticed number of transistors doubling with release of
each new IC generation
 release dates (separate generations) were all 18-24
months apart
 Moore’s Law:
 “The number of transistors on an integrated circuit
will double every 18 months”
 The level of integration of silicon technology as measured in terms
of number of devices per IC
 Semiconductor industry has followed this prediction with surprising
accuracy.
 Transistor
Scaling
 Until 1980’s technology was mixed, using nMOS,
pMOS, bipolar, and some CMOS.

 Supply voltage was not scaling, so power was rising.

 To reduce power, scale VDD.

 Even then power is growing, due to increased die

size, and fast frequency scaling
 Transistor Scaling

90nm 65nm
130nm

32nm 22nm
45nm
 Why do we scale MOS transistor?

1. Increase device packing density- reduces

area
2. Improve frequency response α 1/L
3. Improve drive current
4. To improve power efficiency
 Technology
Scaling
Delay, Area, Cost
and Dynamic
power

Static power
and
Variability
issues

13
 Scaling
Full Scaling (Constant Electric Field Scaling)

 In reality constant field scaling has not been observed strictly.

Since the transistor current is proportional to the gate
overdrive.

 High performance demands have dictated the use of higher

supply voltage.

 However, higher VDD implies increased power dissipation.

 Improved performance is due to the reduced capacitance.

 Full Scaling

Classical Voltage scaling ended at 130nm

 Fixed- Voltage Scaling
 Keeping voltage constant while scaling device
dimensions.
 Improved ION is due higher VDD.
 Fixed voltage scaling is comes with major power
penalty.

Hot carrier effect and oxide breakdown

phenomena compels supply voltage scaling.
 General Scaling
• General scaling model dimensions are scaled by
a factor S, while voltage are reduced by a factor U.

• When voltage is held constant, U=1, the scaling

model reduces to the fixed-voltage model.

• Offers similar performance scenario identical to the

full-and fixed scaling models.
Transistor Scaling
 Changes in Scaling

Then >130nm Now <45nm

 Scaling drives down cost

 Scaling drove down cost  Materials drive
 Scaling drove performance
performance  Power constrained
 Standby power dominates
 Performance constrained  Variability issues
 Active power dominates  SCEs
 Need to indentify alternative
to Si and/or SiO2
 Year Technology Year Projected
Semiconductor node (Approxima Technology
te) node
Manufacturing Processes
1971 10µm 2014 14nm
1975 3µm 2016 10nm
Scaling of CMOS has driven 1982 1.5µm 2018 7nm
the tremendous growth of 1985 1µm 2020 5nm
semiconductor industry for
1989 800nm
last four decades.
1994 600nm
1995 350nm
1998 250nm
1999 180nm
2000 130nm
2002 90nm
2006 65nm
2008 45nm
2010 32nm
2012 22nm
 The Nanometer Size
Scale
Transisto
Scaling
r MOSFET

22nm

Carbon nanotube

Scaling cannot go on forever because transistors cannot be smaller than atoms

 Transistor density and
performance
100 2.
0 0 1.0 V, 100 nA
IOFF 32n
m
1. 45n
m
5 65n
Gat Drive m
90n
e Current 1.0 m
Pitc 0.7x every 65n 130n
2 years m (mA/um) m
h 45nm NMO
(nm) 0. S
32n 5 PMO
112.5 nm m
S
10 0.
0 1995 2000 201 0 100 10
2005 0 Gate Pitch
0 0
(nm)
 Parameters Limiting further technology
scaling
1. Increased Static power dissipation
2. Increased variability issues
3. Short channel effects
 Variability Issues

Device Circuit
Characteristics Performance
 Process •
ION/ IOFF
• Subthreshold slope
 Voltage • Threshold voltage
• Drive Current
 Temperatur • Oxide thickness
• Speed
e • Geometry parameters
Device
Variation Performance
s
Process
Voltage and
Temperatur
e

Variability issues are even more pronounce for nano -

scale.
26
 Discrete vs Integrated Circuit Design
Activity/Item Discrete circuits Integrated Circuits
Component Accuracy Well Known Poor absolute Accuracies

Bread boarding Yes No

Fabrication Independent Very dependent

Physical Implementation PC Layout Layout, verification and

Extraction
Parasitic Not important Must be included in the
design
Simulation Model Parameters well known Model parameters vary
widely
Testing Generally complete testing is Must be considered before
possible design
CAD Schematic capture Simulation, Schematic capture
PC Board layout Simulation, layout

Components All possible Active devices, capacitor,

and resistor
 Why ICs?
 Size
 Speed
 Power
 Complexity

 Smaller size of IC components yields higher

speed and lower power consumption
 Integration reduces manufacturing cost
 Integrated Circuit Classification

 Circuit Technology
(BJT, BiCMOS, NMOS, CMOS)

 Design Style
(Standard cell, Gate array, full Custom,
FPGA)

 Circuit Size
(SSI, MSI, LSI, VLSI, ULSI, GSI)
 Circuit Technology

IC Technology

Bipolar CMOS BiCMOS SOI SiGe GaAs

Category BJT CMOS Lower

Power
Power Moderate less Dissipation
Dissipation to High
Appr.
Speed Faster Fast High
Equal rise
packing
Gm 4ms 0.4ms and fall Why
time CMOS density
Switch poor Good
implementation
?

Technology slower Faster Fully

restored
Scale down
improvement more
logic levels
easily
 ECL
 It is fastest bipolar circuit architecture available
today.
 It was the technology of choice for large mainframe
computers and supercomputers for many many years.
 Suffered from relatively high levels of power
consumption compared to CMOS technology.
 CMOS now offers speed approaching that of emitter-
coupled logic and also support much higher circuit
density and lower power consumption.
 However, high trans conductance of bipolar family
leads to develop BiCMOS.
 BiCMOS
Excellent properties for high-
frequency analog amplifiers
 Higher speed
 High gain
 Low out put resistance BJT

BICMOS
 Low power consumption
 High input resistance
Simple construction and CMOS  Fabrication challenges
scaling Challenges in optimizing
parameters of both BJT and
low-power logic gate CMOS
 Amplifiers, analog power
management ckt.
 SOI
Technology
 Silicon on insulator (SOI) technology refers to the
use of a layered silicon-insulator-silicon substrate
in place of conventional silicon substrates.

 Reduces parasitic device capacitance, thereby

improving performance.
 GaAs
 It is a III/V semiconductor, and is used in the manufacture of
devices such as microwave frequency integrated circuits.
 Some electronic properties of gallium arsenide are superior to
those of silicon. It has a higher saturated electron velocity and
higher electron mobility, allowing gallium arsenide transistors
to function at frequencies in excess of 250 GHz.
 GaAs logic circuits have much higher power consumption,
which has made them unable to compete with silicon logic
circuits.
 GaAs is not having its native oxide like SiO2 in case of Si.
 GaAs in contrast has a very high impurity density, which
makes it difficult to build ICs with small structures, suitable
up to (500nm)
 IC Technology

Ref. Fairchild semiconductor_Logic selection guide

CMOS for logic
BiCMOS for I/O and driver circuits
ECL for critical high speed parts of the
system.
 Design Style

Issues of VLSI Design

Performance Cost Area Time –to-market

Different Design Style

Full Standard
Gate FPGA
Custom Cell
Array
 Full Custom Design
 Custom design involves the entire design of the IC, down
to the smallest detail of the layout.
 No restriction on the placement of functional blocks and
their interconnections

 Highly optimized, but labor intensive.

 Designer must be an expert in VLSI design
 Design time can be very long (multiple months)
 Involves the creation of a completely new chip
 Fabrication costs are high
 Standard Cell Design
 Designer uses a library of standard cells:
an automatic place and route tool does the layout.
 Each standard cell contains a single gate of AND,
OR, NOT etc.
 Standard cells can be placed in rows and connected
with wires Routing done on “channels” between the
rows.
 All cells are the same height but vary in width.
 All cells have inputs and outputs on top or bottom of
cell.
 Design time can be much faster than full custom
because layout is automatically generated.
 Gate Array Design
 Pre-fabricated array of gates (could be NAND). (Gates
already created on a wafer; only need to add the
interconnections)
 Entire chip contains identical gates
 normally 3- or 4-input NAND or NOR gates.
 10,000 – 1,000,000 gates can be fabricated within a single
IC
depending on the technology used.
 Manufacture of interconnections requires only metal
deposition
 Fabrication costs are cheaper than standard cell or full
custom.
 The density of gate arrays is lower than that of custom IC’s
 This style is often a suitable approach for low production
 FPGA Design
 Pre-fabricated array of programmable logic and
interconnections.

 Programmable interconnects between the combinational

logic, flip-flops and chip Inputs and Outputs.

 Field Programmable devices are arrays of logic components

whose connectivity can be established with memory.

 No fabrication step required, avoid fabrication cost and time.

 Very good for prototype design because many FPGAs are re-
usable.
 Flexible Circuit Design
Complex
Interconnect • Power
No physical structure • Delay
layout design
lower NRE
Reconfigured cost
Memory • Power
Requirement

FPGA
Complex • Chip
Architecture size

Field Programmable Gate Arrays (FPGA) are also

attracted
42
by subthreshold circuits.
 FPGA
Architecture  FPGA consists of
Programmable  Array of CLBs
Routing  Programmable interconnect
Switch Short
Segment
Wire resources
Logic

Block  CLBs consists of

Long
Connection Wire  N input LUT
Block Segment  SRAM cells
 Flip flops
Programmable
Connection  Programmable interconnect
Switch resources consists of
Switch  Switch box
Block
 Metal tracks
 Connection box
 Programmable routing
multiplexer
43
 Design type
Analog, digital, or mixed signal

Digital Analog
Regular, hierarchical and Irregular
modular
Designed at system level Designed at circuit level

Available synthesis EDA tool Hard to find synthesis tool

Shorter design time Longer design time

Less power consumption
Difficult to test
 Integrated Circuits Based on transistor count
 Small scale integration(SSI) --1960
The technology was developed by integrating the number of
transistors of 1-100 on a single chip. Ex: Gates, flip-flops, op-amps.

 Medium scale integration(MSI) --1967

The technology was developed by integrating the number of transistors
of 100-1000 on a single chip. Ex: Counters, MUX, adders, 4-bit
microprocessors.

 Large scale integration(LSI) --1972

The technology was developed by integrating the number of transistors
of 1000-10000 on a single chip. Ex:8-bit microprocessors,ROM,RAM.

 Very large scale integration(VLSI) -1978

The technology was developed by integrating the number of transistors
of 10000-1Million on a single chip. Ex:16-32 bit microprocessors,
peripherals, complimentary high MOS.
 Ultra large scale integration(ULSI)
The technology was developed by integrating the
number of transistors of 1Million-10 Millions on a
single chip. Ex: special purpose processors.

 Giant scale integration(GSI)

The technology was developed by integrating the
number of transistors of above 10 Millions on a
single chip. Ex:Embedded system, system on chip.
 Fabrication technology has advanced to the point that
we can put a complete system on a single chip.

 Single chip computer can include a CPU, bus, I/O

devices and memory.

 This reduces the manufacturing cost than the

equivalent board level system with higher
performance and lower power.

What is next?- SoC

 System-on- Chip
A system on a chip or system on chip (SoC or SOC) is an
integrated circuits (IC) that integrates all components of a
computers or other electronics systems into a single chip.

It may contain digital, analog, mixed - signal, and often radio-

frequency functions—all on a single chip substrate

 More compact system

 Higher speed
 Better reliability
 Less expensive
 counters -
Timing sources External interface
timers, and USB, Firewire,
oscillator and
PLL power on reset Ethernet,
generators. USART, SPI.

ROM,RAM,
EEPROM and ADCs and
flash memory DACs.

Voltage
microcontroller,
microprocessor SoC regulator and
power
management
Power Consumption

Dr. Sachin D. Pabale

Matoshri College of Engineering
and Technology
 Outlines
Motivation to estimate power
dissipation
Sources of power dissipation
Metrics
Power optimization Techniques
Conclusion
 Moore’s
Law
• Blessing of technology Scaling:
Transistor count get double every 2 years

• Direct consequence of technology scaling:

Power density of IC increases exponentially at each
technology generation.
 Power Dissipation

CMOS technology is scaling to meet the

1. Performance
2. To reduce the cost
3. Power requirement

However, static power dissipation increases

considerably which is primarily due to the
flow of leakage currents.
Figure 2.1: Normalized dynamic and static power dissipation for (W/Lg=3)
deviĐe. Data is ďased oŶ the ITRS [ϭ6] aŶd Ŷorŵalized to the year ϮϬϬϭ’s
figure [2].
 Need to estimate power dissipation
Power dissipation affects:

Performance

Reliability Cost
Power
Dissipation

Packaging Portability
 200
High performance microprocesssor chip
Hand held products

150

Po
w
er 100
(
W
att
s) 50

0
1999 2002 2005 2008 2011 2014
Year

Figure 2.2: Power requirements of high performance

microprocessor chip and handheld products as per
ITRS [16].
 Exploring Applications
Space
GHz, W
• Servers
• Workstatio
n
• Notebooks

MHz, µW
• Embedded, ASICs
• Mobile electronics

KHz , nW
• RFIDs
• Biomedical Sensors
 Where does power goes in CMOS?

 Dynamic power consumption

 Short circuit power dissipation

 Static/ leakage power

consumption
 Power Consumption in CMOS
Ptotal   f C load V 2
 Ileak DD ft  Ipeak t sc f VDD
DD V leak

PStatic Pshort-circuit
Pdynamic

Delay

Leakage

reduces

Delay
1. Dynamic power dissipation

VDD

VOUT
Vin

CL
 Dynamic capacitive power and energy
stored in PMOS device
Case I: When input is at logic 0: VDD
Power dissipation in PMOS is,

PP  iLVSD  iL (VDD VO )

Vin VSD
The current and voltages are related VO
by, CL
iL  CLdvo / dt

Similarly, energy dissipation in the

PMOS,
Case II: when the input is high and
output is low.
During switching all the energy stored in the load VDD
capacitor is dissipated in the NMOS device is
conducting and PMOS is in cutoff mode. The
energy dissipation in the NMOS inverter can be Vin

written as, CL
VO

2
1
EN  2 CLDD
V 2 2
  C LV
2
1 L 1 L
ET  EP  EN 2 C DD
C V
DD DD
V 2 2
E
ET  Pt  P  t T  P  TfE  fC
L
DD
• Power dissipation in terms of
frequency, 2
E
ET  Pt  P  tT  P  fE T  fC LV DD

• Above equation shows that the power dissipation in

the CMOS inverter is directly proportional to
switching frequency and VDD.2 T
1
Pdynamic T  DD
 i (t)VDDdt
0
T
VDD

T 0 iDD (t)dt

VDD
 T Tf sw DD 
 DD 2 f sw
CV
CV
 Dynamic capacitive power
• Dynamic power:
2
Pdynamic  fC L V DD
Observations:
 Does not depends on device size

 Does not depends on switching delay

 Applies to general CMOS gate in which,

• Switch cap. are lumped into CL

• Output swing from GND to VDD

• Gate switches with frequency f

 Lowering Dynamic Power

Supply
Voltage:
Has been reduced with
successive generation
Pdynamic  fCLV 2
DD

Function of fan-out, Clock frequency

wire length, transistor Increasing…..
sizes
Power as function of Frequency
-5
10
VDD=0.35V
-6
10 VDD=0.4V
VDD=0.9V
VDD=1.2V
Po 10-7
w
er superthreshold Subthreshold
di -8 regime regime
ss 10
pa
tio -9
n 10
(
W -10
) 10

-11
10
0 2 4
10 10 10
Frequency (KHz)

Figure 2.13: Power dissipation as a function

of operating frequency.
 Short Circuit Power Consumption

VDD
 Finite slope of input signal causes
a
direct current path between VDD and Vin
VOUT
GND for short period of time. CL

 i.e. Short circuit current flows from

VDD to GND when both transistors
are on.
 Short Circuit Power Consumption

40 400
0 Vou short circuit 0
Vin t leakage

VDD - Vth 30 300

0 0
32nm
O NMOS
ut C
pu VDD=0.4
Vth t 20 V 200 re
ur
vo 0 0 nt
lta (p
t ge
(m
A)
I max
V)
100
100 0
I short Transitio
n
0 0
0 50 150 25 30 35 40
100 200
Input voltage 0 0 0 0
(mV)

Figure 2.4: Short circuit leakage

current of inverter at 32 nm technology
node and VDD=0.4V.
 Short Circuit Power Consumption

• Approximate short circuit current as

triangular wave.
• Energy per cycle,
I t I t tr  t f
ESC  DD max r
V DD max r
 V DD I
V 2 2 max 2
tr  t f
PSC  VDD Imax f 2
 Short Circuit Current Determines

PSC  tscVDD I peak f01

• Duration and slope of the input signal, tsc

Ipeak determined by,

The saturation current of the P and N transistors

which depends on their sizes, process technology,
temperature, etc.
Strong function of the ratio between input and output
slopes
• a function of CL
 Impact of CL on PSC

VDD
VDD

ISC≈ 0
ISC ≈ Imax
VOUT
Vin
Vin
VOUT
CL 
CL

Large Capacitive Load Small Capacitive Load

Short circuit dissipation is minimized by matching the

rise/ fall times of the input and output signals.
As capacitive load increases short circuit power
decreases
 Static Power Dissipation

• The static power is defined as the power consumption due to

constant current from VDD to ground in the absence of switching
activity.
• Shrinking transistor geometries causes different sources of
leakage current [16].

Gate
B S D
p+
p+ n+ n+ n+ n+
Sub-threshold

p-n junction
p-well p-n junction punchthroughp-n junction
punchthroughp-n junction p-
Gate leakage GIDL leakage
Substrate
well

Gate leakage GIDL leakage

 Static Power Dissipation
• Sources of static power
dissipation

 Reverse bias pn- junction current

 Subthreshold leakage current
 Gate leakage current
 Gate-Induced Drain Leakage
current
 Punchthrough Leakage current
1. Reverse bias pn- junction current is flowing
due to,
 minority carrier diffusion/drift near the edge
of the depletion region;
 electron-hole pair generation in the depletion
region of the reverse-biased junction [12].

The magnitude of the diode’s leakage current

depends on the area of the drain diffusion and
the leakage current density.
• In the presence of a high electric field (4106
V/cm) electrons will tunnel across a reverse-
biased p–n junction.
• Process technologies are generally well
designed to keep this pn-junction leakage
small relative to the subthreshold current.
 2. Subthreshold leakage Current
• Subthreshold or weak inversion conduction
current between source and drain in an
MOS transistor occurs when gate voltage is
below [15].
(VGS Vth VDS ) VDS

ID  Isub  ID0e nUT (1 e UT )

Weff  qsi Ncheff U 2   VGS Vth    VDS 

ID  Isub  T 
 1 exp  
Leff 2s  nU T 
   T 
U
exp
 Subthreshold leakage Current
2
10
VGS <Vth
1
S
10
Dr VDS<Vth
ai 0
n1
C0 D
ur
re - n+ TOX n+
nt 1 Subthreshold region
(u10 Superthreshold region Isub
A)
- p-Substrate L
2 Isu Vth=0.4
10 b 9V
IOF
- F
13
0 0 100 200 300 400 500 600 700 800 900
VGS (mV)
I-V characteristics of NMOS NMOS transistor with bias voltages.
transistor.
 3. Gate leakage current
• As technology scales down, the oxide thickness gets
thinner which causes high electric field across the
oxide.
• As TOX scales below 3 nm, gate to channel leakage
current starts to appear even at low gate voltage. That
results in direct tunneling of electrons from substrate to
gate and gate to substrate through the gate oxide.
‘

Gate leakage current

The gate leakage expressed in [32] is given by equation as
follows,
Vox 2  B(1 (1 OX /  )3/2)
)   
Igate  Weff Leff A ( V OX
Tox exp  VOX / OX 

A q3 4 2m  3/2
B ox
16  h ox
3hq

where ‘VOX’ is the potential drop across the thin oxide layer, ‘

ox is the barrier height for the tunneling particles, ‘TOX’ is the oxide
thickness, ‘A’ and ‘B’ are physical parameters.

Gate tunneling current has very strong dependence on the

voltage
 4. Gate induced drain leakage

• In the overlapping zone between gate and

drain, a high electric field exists, leading to the
generation of current from the edge of drain
and terminating at the body of the transistor.

• Thinner oxide thickness and higher potential

between gate and drain enhance the electric
field and therefore increase GIDL.
 5. Puchthrough leakage current

• In short-channel devices, the depletion regions at the

drain-substrate and source-substrate junctions extend
into the channel.
• As the channel length is reduced, if the doping is kept
constant, the separation between the depletion region
boundaries decreases.
• When the combination of channel length and reverse
bias leads to the merging of the depletion regions,
punchthrough is said to have occurred.
 Inverter Power
consumption
• Total Power
consumption

Ptot  Pdyn  Psc  Pstat tr  t

2
f VDD Imax (
Ptot  f 2 ) f VDD Ileak
CLVDD
 Power Reduction
1. Dynamic Power
 Lower the voltage
 Reduce capacitance
 Reduce frequency
2. Reducing short-circuit current
 Fats rise/ fall time on input signal
 Reduce input capacitance
 Insert small buffers to clean up slow i/p
3. Reducing leakage current
 Small transistors (leakage proportional to width)
 Lower voltage
 Power Optimization Methodology
 Multiple VDD

 Multiple VDD -Multiple Vth

 Gate sizing

 Transistor sizing

 Power gating

 Transistor stacking and sleepy stacking

 Multi-threshold architectures

 Adaptive body biasing

 Dual Power Supply
VDDL VDDH
Dual Power Supply
lowering the along non-
VDD Vin VOu
delay paths or light
critical
workloads and t

higher VDD for heavy workloads . Static

current

The main problem of designing dual

VDD in CMOS circuits is the increased
leakage current in the high voltage
gates, when a low voltage gate is
driving them.
 Gate and Transistor sizing
• For non critical path reduce device size to
minimize the power consumption.

• In Gate sizing techniques all transistors in gate

is having size.

• In transistor sizing, within a gate transistors

may have different size to maximize the
power saving.
Leakage Power Reduction Techniques
Power Gating and Sleep

Virtual VDD

Multi- Threshold PP

Voltage
In Out

 In the ACTIVE mode, the

NN

Virtual Ground

sleep transistor is ON. Sleep

 In the STANDBY mode, the

sleep transistor is turned OFF.

“Higher Vth devices are preferred for sleepy

transistors to reduce leakage current.” -
Multi-threshold architecture
Power Gating and Multi-Threshold Voltage

VDD

High-Vth sleep
Standby
transistor

VDDV

Bypass Low-Vth logic

capacitance Transisto
GND r

MTCMOS Logic
Leakage Power Reduction Techniques
1. Adaptive Body Bias

 Increase the threshold voltage

of  VD Stand
STANDBY state – D by
< Activ
transistors in the e
RBB technique. VDD
VD
D
Vth Vtho ( |2F VSB | |2F |)
Contr
Control
olLoop
 Can be applied at chip level or block Loo
p
level. Block level is most commonly
Gn Activ
preferred. d  Gn
e
<d Stand
Gnd by
 FBB technique can be used to reduce
VTh and hence delay in active mode.
 Dynamic supply voltage scaling schemes

• Uses variable supply voltage and speed tech.

• The highest supply voltage delivers the highest

performance at the fastest designed frequency of
operation.

• When performance demand is low, supply

voltage and clock frequency is lowered, just
delivering the required performance with
substantial power reduction [41].
 DVS
• system
Processor speed is controlled
by software program
automatically
• Supply voltage is controlled
by hard-wire frequency–
voltage feedback loop, using
a ring oscillator as a critical
path replica.
• All chips operate at the same
clock frequency and same
supply voltage, which are
generated from the ring
oscillator and the regulator.
 Higher oxide thickness.

• To obtain high Vth devices

• To reduce subthreshold leakage current
• To reduce gate tunneling leakage current

• However, in case of severe SCE an increase in the oxide

thickness will increase the subthreshold leakage.
• In order to suppress SCE, the high tox device needs to
have a longer channel length as compared to the low
tox device [47]
• Advanced process technology is required for fabricating
multiple tox CMOS.
 Clock gating
• Clock gating is an effective way of reducing the dynamic
power dissipation in digital circuits.
• In a typical synchronous circuit such as the general purpose
microprocessor, only a portion of the circuit is active at any
given time. Hence, by shutting down the idle portion of the
circuit, the unnecessary power consumption can be
prevented.
• This prevents unnecessary switching of the inputs to the
idle circuit block, reducing the dynamic power.
Low voltage of Operation

Subthreshold Operating
region
 Power Consumption
 Power consumption has become a significant
hurdle for recent ICs
 Higher power consumption leads to
• Shorter battery life
• Higher on-chip temperatures – reduced
operating life of the chip
There is a large and growing class of applications
where power reduction is paramount – not speed.

• Such applications are ideal candidates for sub-

threshold circuit design.
• OK, so what is sub-threshold design??
 KHz , nW
Ultra Low Power Circuit Design RFIDs tags
Biomedical Sensors
etc
Need:
 Power aware design increases considerably due to
remarkable growth of portable applications.
 Remarkable power requirement gap between high
performance microprocessor chip and portable device.
 Increased leakage power density can not be ignored in
case of portable devices.
 To enhance the battery life time

How to
• Designing
satisfy Subthreshold
ULP Circuits
demand?
 Minimum Operating
• Voltage
Swanson and Meindl (1972) examined the VTC of an
inverter:
 Minimum Voltage = 8kT/q or 200 mV at 300K (A
ring oscillator worked at 100 mV soon thereafter.)

• Ideal limit of the lowest possible supply voltage (2001) :

VDD = 2kT/q ≈ 57 mV at 300K

• R. M. Swanson and J. D. Meindl, “Ion-Implanted Complementary MOS

Transistors in Low-Voltage Circuits,” IEEE JSSC, vol. 7, no. 2, April 1972.
• A. Bryant, J. Brown, P. Cottrell, M. Ketchen, J. Ellis-Monaghan, E. Nowak, I.
Div, and E. Junction, “Low-power CMOS at Vdd= 4kT/q,” in Device Research
Conference, 2001, pp. 22–23.
 Subthreshold Regime (VDD<Vth)
2
10

VGS
1
<Vth
S 10

VDS<Vth Dr
ai 0
D n 10
C
n+ TOX n+ ur -1
re 10 Subthreshold region Superthreshold region
Isub
nt
p- L (u
Substrate A)10-2 Isub Vth=0.49V

IOFF
Fig. 2.6 NMOS transistor with bias 10
-3

0 100 200 300 400 500 600 700 800 900

voltages
VGS (mV)

Fig. 2.7 I-V characteristics of NMOS

transistor

ID  Isub  Weff  qsi Ncheff U   VGS Vth    VDS 

T
2
 1 exp  
Leff 2s  nUT  
  U T 

exp
 Sub-Threshold Regime
ID  Isub  Weff  qsi Ncheff U 2   VGS Vth    VDS 
T 
 1 exp  
Leff 2 s  nU T  
  T 
U
exp
Exponentially

Circuit Delay

Exponentially

Supply VDD< VTh

Voltag Leakage Energy Etotal
e Dissipation
t leakI  VCVDDt  CVDD
Subthreshold I leak
leak DD
on I 0eVDD /(nUt )
regime
Switching
Energy Etotal Cload VDD 2
Quadretically
 Sub-Threshold Regime

Benefits Challenges

 High transconductance gain  Re-claiming the speed penalty

 Near-ideal Voltage  Increased sensitivity to PVT
Transfer Characteristics variations due to exponential
(VTCs) I–V characteristics
 Ultra low power  Energy minimization in sub-
consumptions threshold circuits
 To develop subthreshold
device library files

These challenges leads us to design “Robust Subthreshold

Circuits with Moderate Speed”
The wire
Dr. Sachin
Pable
 Integrated Circuits

Basic Components

Active devices Interconnects

Local (short) Global (Long)

interconnect
interconnect
 VLSI Interconnects

 Used to connect components on a VLSI chip

 Used to connect chips on a multichip module

 Used to connect multichip modules on a system

board
 Wires on chip
Most of chip is wires
(interconnect)
• Most of the chip is covered by
wires, many layers of wires
• Transistors: little things under wires
• Wires as important as transistors
Affect:
 Speed
 Power
 Noise
• Alternating layers usually run
orthogonally
• In past history of integrated circuits, on-chip
interconnect wires were considered to be second class
citizens.

• only to be considered in special cases

or when performing high-precision analysis.

• With the progress semiconductor technologies, this picture is

undergoing rapid changes.
 85% 15%

Mid 1980’s
Gate delay dominates,

50% 50%

Mid 90
Gate delay and wire
delay

20% 80%

Today
Mostly wire delay
Figure 4.4: Breakdown of (a) delay and (b) energy
in simulation of FPGA at 0.4V subthreshold
voltage [7].
 Why
Al
• Low cost, easily purified
• Low resistivity
• Good adherence to Si and
SiO2
• Good patternability
• Ease of deposition
The wiring forms a complex geometry that introduces
parasitics:resistive, capacitive and inductive.
All three have multiple effects on the circuit behavior.

 An increase in propagation delay, or, equivalently, a

drop in performance.
 An impact on the energy dissipation and the power

distribution.
 An introduction of extra noise sources, which

affects the reliability of the circuit.

 Problem with
• Al Decreased
Device Dimension

Current Density Increases

Decreased reliability
(Electronics, shorting between level of Al
Solution
• Alternative Metal/ Metal Composite – Cu is preffered
in modern process- CNT will prefer in future
 Metallic Interconnections Issues

 Parasitic Capacitances and Inductances

 Reduction of Propagation Delays

 Reduction of Crosstalk Effects

 Reduction of Electromigration-Induced
Failure
CMOS inverter driving
interconnect
The delay for RC Cu interconnect
driven by a CMOS driver is given
by [129],

d  Rdriv (Cdriv  Cload )  0.4R .C

(Rdriv .CW  R W .Cload )l W l2
 W
 Interconnect scaling
trends
Ideal scaling Constant dimension
Line width/spacing S 1
Wire thickness S 1
Interlevel dielectric S 1
Wire length 1/sqrt(S) 1/sqrt(S)
Resistance/unit length 1/S2 1
Capacitance/unit length 1 1
RC delay 1/S3 1/S
Current density 1/S S
Technology scaling and wire
 w s

Wire geometry
l
• Pitch= w + s
• Aspect Ratio,
AR=t/w t

h
Modern process have
AR=2 for short
Ground
AR=3 for long H W
interconnect
t S

Ground
 Wire_Resistance

• The resistance of a wire is proportional to its length L

and inversely proportional to its cross-section A.
L
R 
AL HW
L
RR 
W

R 
H
 Wire
capacitance
1. Area component ( Also referred to as parallel
plate capacitance components)
2. Fringing field component
3.Wire- to-wire capacitance components To improve
delay
 Increase dielectric thickness
 Reduce wire width
 Reduce spacing
1. Parallel plate
capacitance
For w >> tdi (thickness of insulating material) it is
assumed that the electrical field lines are orthogonal
to the capacitance plates.

Cint   di WL
t di
 Fringing capacitance
• In modern process W/H ratio drops down
significantly.
• It causes capacitance between side walls of
wire and substrate, called fringing
capacitance.
• It can no longer be ignored.
 C fring  w. di  2
CWire  C pp
t di log( tdi /
where, w  W  H / H )
di

2
 Capacitance as function of W and tdi

W/tdi indirectly W/H

@From Schaper83
Inter wire capacitance

• Interlayer capacitance is
more dominant in multilayer
structure. This effect is more
pronounce for wires in the
higher interconnect layers.
 Propagation
Delays
Definitions Delay Time
• Time required by the output signal (current or
voltage) to reach 50% of its steady state value
Rise Time
• Time required by the output signal to rise from 10%
to 90% of its steady state value
Propagation Time
• Time required by the output signal to reach 90% of
its steady state value
 The Lumped Model
 Paracitics of wires are distributed along its length.

But, when signle paracitic components is dominant

it is oftenly useful to consider lumped model.
For small resistive components, low to medium
frequency range only capacitance component can be
considered.
 Distributed capacitance can be lumped into single
capacitor Rdriver V
ou

. Vou
t

t Vin
cwir Clumped
Driv e
er
24
 The Lumped RC-Model
The Elmore Delay
To model propagation delay time along
a path from the source s to destination i
s
considering the loading effect of the
other nodes on the path from s to k

The shared path resistance Rik

The Elmore delay

Elmore delay
 RC-Models

27
• Wires are a distributed system

– Approximate with lumped element models

N segments
R R/N R/N R/N R/N
C C/N C/N C/N C/N

R R R/2 R/2

C C/2 C/2 C

L-model -model T-model

 3-segment p-model is accurate to 3% in simulation

 L-model needs 100 segments for same accuracy!
 Driving an RC-line
Rs (rw,cw,L)
V out

V in

29
 Design Rules of Thumb
 rc delays should only be considered when tpRC >>
tpgate of the driving gate

Lcrit >>  tpgate/0.38rc

 rc delays should only be considered when the rise

(fall) time at the line input is smaller than RC,
the rise (fall) time of the line

 trise < RC

 otherwise, the change in the input signal is slower than

the propagation delay of the wire
30
 100
0 Opt.mixed CNT Total Driver Inter.dela
bundle Mixed CNT 30 delay delay y 4
90
0 bundle [94] Cu Dr 0 0
iv 25 In
C 80 er 3 ter
ap 0 an
0 co
2 nn
ac d 20
ita 70 tot ec
al
0 2 t
nc 0
e de 15 4 de
(f 60 la la
0 y
F) 0 y 1
(n 10 (n
s) 6 s)
50 0
0 L=5000u 5 8
m 0 4 7 96 12 14
40
8 2 Spacing 0 4
0 1 3
(nm)
1.5 2 2.5
Aspect Ratio
• Capacitance as function of AR Delay as function of spacing
PDP as function of interconnect
length

60 Superthreshold regime
Subthreshold regime
50
40
P
D 30
P
(f 20
J)
10
2
0 4
0
10 6
20 8 Interconnect length
1 x min. driver width 30 (mm)
40 10
 Delay as function of interconnect
width

3
10 2
10
Conv. device a nd interc onnect Conv. erconn ct and evice
int e d
2
10 1
D 10
el P
ay D
(n 1 P
s) 10 (J)
10
0

0
-1
10 10
20 20 120
15 120 15 Opt. interconnect and
Opt. device and interconnect 100
10 100 device
10 80
80 Minimum X driver
Min. X driver 5 Interconnect width (nm) size Interconnect width
60 60 (nm)
size 5
0 40 0 40
 Interconnect Techniques
 Driver Sizing Driver Interconnect Receiver

Cin Cpar.
Cload

(a)
 Tapered Driver
Tapered Driver Interconnect Tapered Receiver

Cin Cpar.
Cload

 Repeater Insertion (b)

Driver Receive
r
Interconnec Interconnec Interconnec
t t t

Cin Repeate Clo

Repeate
r r
ad

© 34
 Repeaters
 R and C are proportional to l
 RC delay is proportional to l2
 Unacceptably great for long wires
 Break long wires into N shorter segments
 Drive each one with an inverter or buffer
Wire Length: l

Driver Receiver

NSegments
Segment
l/N l/N l/N

Driver Repeater Repeater Repeater Receiver

 Repeater
Design should we use?
• How many repeaters
• How large should each one be?
• Equivalent Circuit
– Wire length l
• Wire Capacitance Cw*l, Resistance Rw*l
– Inverter width W (nMOS = W, pMOS =
2W)
• Gate Capacitance C’*W, Resistance R/W
RwlN

R/
W Cwl/2N Cwl/2N C'W
Interconnect
Slide 36
Effect of repeater insertion
 Crosstalk
• The crosstalk coupling represents the parasitic
transient voltage induced by a switching interconnect
on a neighboring interconnect.
• Crosstalk is the interference in a victim line signal
transmission caused by switching activity on
aggressor lines
• As integration density of on chip interconnect
increases at every technology node, the crosstalk
effect becomes more pronounced [132].
• Strongly depends on the value of the coupling
capacitance (Cc), transition-time skew and the
adjacent interconnect length
 Crosstalk
• In order to keep crosstalk minimum, the capacitance
between two wires should not be too large [27].

• This is feasible by breaking a long interconnect by

inserting intermediate buffers.

• Another approach of reducing the crosstalk is to use

shielding wires.
 R Lw
s w C Cloa
w
w C d
layer Aggressor
1 c
n+1
h2 Cto Rw Lw
p Cloa
t layer d
Victi C
Cbo Cadj
n m c
h1 C
Rw
t
layer w L Cloa
n-1 d
Aggressor w
2 C
w

Figure 5.19: Schematic of equivalent

circuit to model crosstalk between
adjacent wires.
 Crosstalk noise

• Crosstalk causes noise on nonswitching

wires
• If victim is floating:
– model as capacitive voltage divider
Vvictim  Cadj Vaggresso
Cgnd  adj r
Cv
Aggresso
r
Vaggressor
Cadj

Victim
V
Cgnd-v victim
 Driven
• Usually victim Victims
is driven by a gate that fights noise
– Noise depends on relative resistances
– Victim driver is in linear region, agg. in saturation
– If sizes are same, Raggressor = 2-4 x Rvictim

Vvictim  Cadj 1 Raggressor Aggresso

1  V
aggressor
C gnd v  Cadj Vaggresso
Cgnd-
r
a
k r
Cadj
Rvictim Victim

 Raggressor Cgnd a  Cadj  Cgnd-v

V
victi
m

 
k  aggressor
victim
Rvictim Cgnd v  Cadj 
Figure: Snapshot of signal transition due to
aggressor transitions for Cu interconnect.
Snapshots of voltages across victim
wire due to aggressors
transitions.
5. Effect of Crosstalk on Interconnect Performance
Table : Effect of crosstalk on interconnect performance (L=10
mm).
Aggressor Victim Rise Fall Time Delay RLC Power
Transition Transition Time (ns) (ns) PDP (fJ) (nW)
(ns)

Without Low to high 256.7 285.2 270.9 60.64 17.35

Aggressors High to low 242.2 286.14 264.2 59.16 15.9
Low to high Low to high 256.7 285.2 270.98 60.64 17.35
High to low High to low 242.2 286.14 264.2 59.16 15.9
Low to high High to low 394.9 380 387.9 110.2 25.58
High to low Low to high 257 479 368.4 104.88 22.66
Low to high Held at low Results in rise glitch on victim
High to low Held at low Results in undershoot on victim
45
Future interconnects
 Carbon Nanotubes (CNTs)

Classification of CNTs
d

Mixed CNT
Bundle SWCNT

Dmin MWCNT

Dmax

(a) (b) (c)

Figure (a) Single-wall carbon nanotubes, (b) Multi-wall carbon nanotubes

and (c) Mixed CNT bundle
47
 Single-Wall Carbon Nanotubes
(SWCNT)
(Rc+RQ)/2 R/2 R /2 (Rc+RQ)
SWCNT L/2 L/2 /2
Ground Plane
d 4C
Q
y
C
E

Fig. Equivalent RLC circuit of

SWCNT
 SWCNT: Single sheet of cylindrically rolled
graphene
: diameter in nanometer range

 Depending upon rolling (chiralities) it produces either

metallic CNT or semiconducting CNT.
48
 SWCNT_ Resistance

• The resistance of a SWCNT (RCNT) consists of

 Quantum resistance (RQ) / an intrinsic resistance

RQ  h / 4e2  6.5 k
 Contact resistance (RC). (20 to 120 kΩ [94])
For longer length, SWCNT resistance depends on its length and
applied voltage.
R CNT  h / 4e2  6.5 k lCNT  
2
lCNT  

Distributed resistance model of SWCNT: RCNT  RC  RQ(1 lCNT 49/ l0

 SWCNT_Capacitance

• Capacitance of an isolated SWCNT is contributed by

CE  2
 Electrostatic capacitance (CE) ln
With diameter ‘d’ placed at a distance ‘y’ away from a ground (y/d)
plane

 Quantum capacitance (CQ C  2e2 / hV

Q f

CQ) of individual SWCNT has a typical value of 100 aF/μm.

The effective SWCNT capacitance is given by series

combination of CE and CQ
50
 Mixed CNT Bundle

 Higher resistance associated with individual SWCNT

motivated researchers to use a bundle of CNTs.

 Theoretically, CNT bundles may contain only

SWCNTs or only MWCNTs.

 A mixed bundle consists of SWCNTs with a diameter

‘d’ and MWCNTs with various diameters (Din < di < Dout).

 Mixed CNT bundle is more realistic than SWCNT and

MWCNT bundle.
51
Thank you