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    18ec52 - DSP

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    JEETHAN
    This document discusses digital signal processors and their hardware units. It explains that DSPs can use either von Neumann or Harvard architecture for their execution cycles. The main hardware units of a DSP are the multiplier and accumulator along with address generators. It also discusses fixed-point number format and how to convert decimal numbers to their two's complement binary representations in Q-15 format. An example shows converting the decimal -0.160123 to its Q-15 representation.

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    18ec52 - DSP

    Uploaded by

    JEETHAN
    130 views14 pages
    This document discusses digital signal processors and their hardware units. It explains that DSPs can use either von Neumann or Harvard architecture for their execution cycles. The main hardware units of a DSP are the multiplier and accumulator along with address generators. It also discusses fixed-point number format and how to convert decimal numbers to their two's complement binary representations in Q-15 format. An example shows converting the decimal -0.160123 to its Q-15 representation.

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    18EC52 - DSP.pptx

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    This document discusses digital signal processors and their hardware units. It explains that DSPs can use either von Neumann or Harvard architecture for their execution cycles. The main hardware units of a DSP are the multiplier and accumulator along with address generators. It also discusses fixed-point number format and how to convert decimal numbers to their two's complement binary representations in Q-15 format. An example shows converting the decimal -0.160123 to its Q-15 representation.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    130 views14 pages

    18ec52 - DSP

    Uploaded by

    JEETHAN
    This document discusses digital signal processors and their hardware units. It explains that DSPs can use either von Neumann or Harvard architecture for their execution cycles. The main hardware units of a DSP are the multiplier and accumulator along with address generators. It also discusses fixed-point number format and how to convert decimal numbers to their two's complement binary representations in Q-15 format. An example shows converting the decimal -0.160123 to its Q-15 representation.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    of 14

    18EC52 - DSP

    Digital Signal Processors

    Von Neumann architecture


    Harvard architecture.
    Execution cycle based on the
    Von Neumann architecture
    Execution cycle based on
    Harvard architecture
    DIGITAL SIGNAL PROCESSOR
    HARDWARE UNITS
    • Multiplier and Accumulator
    Address Generators
    Fixed-Point Format
    Converting a decimal number to its 2’s
    complement form requires following steps:

    1. Convert the magnitude in the decimal to its binary


    number using the required number of bits.
    2. If the decimal number is positive, its binary number is its
    2’s complement representation; if the decimal number is
    negative, perform the 2’s complement operation, where
    we negate the binary number by changing the logic 1s to
    logic 0s and logic 0s to logic 1s and then add a logic 1 to
    the data.
    Q – format
    Q-15 means that the data are in a sign magnitude form in which
    there are 15 bits for magnitude and one bit for sign.

    Find the signed Q-15 representation for the decimal


    number 0.560123.
    Find the signed Q-15 representation for the
    decimal number -0.160123

    Converting the Q-15 format for the corresponding


    positive number with the same magnitude using
    the procedure

    0:160123 =0:001010001111110
    Then after applying 2’s complement, the Q-15
    format becomes
    -0:160123 = 1:110101110000010

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