Introduction to

CMOS VLSI
Design

Lecture 6:
Wires
David Harris

Harvey Mudd College

Spring 2004
 Outline
 Introduction
 Wire Resistance
 Wire Capacitance
 Wire RC Delay
 Crosstalk
 Wire Engineering
 Repeaters

6: Wires CMOS VLSI Design Slide 2

 Introduction
 Chips are mostly made of wires called interconnect
– In stick diagram, wires set size
– Transistors are little things under the wires
– Many layers of wires
 Wires are as important as transistors
– Speed
– Power
– Noise
 Alternating layers run orthogonally

6: Wires CMOS VLSI Design Slide 3

 Wire Geometry
 Pitch = w + s
 Aspect ratio: AR = t/w
– Old processes had AR << 1
– Modern processes have AR  2 w s
• Pack in many skinny wires
l

6: Wires CMOS VLSI Design Slide 4

 Layer Stack
 AMI 0.6 m process has 3 metal layers
 Modern processes use 6-10+ metal layers
 Example: Layer T (nm) W (nm) S (nm) AR

Intel 180 nm process 6 1720 860 860 2.0

1000
 M1: thin, narrow (< 3)
5 1600 800 800 2.0
– High density cells 1000

 M2-M4: thicker 4 1080

700
540 540 2.0

– For longer wires 3 700

700
320 320 2.2

2 700 320 320 2.2

 M5-M6: thickest 700
1 480 250 250 1.9

– For VDD, GND, clk 800

Substrate

6: Wires CMOS VLSI Design Slide 5

 Wire Resistance
  = resistivity (*m)

R

6: Wires CMOS VLSI Design Slide 6

 Wire Resistance
  = resistivity (*m)
 l
R
t w

6: Wires CMOS VLSI Design Slide 7

 Wire Resistance
  = resistivity (*m)
 l l
R  R
t w w
 R = sheet resistance (/) w w

  is a dimensionless unit(!)
l

 Count number of squares w

– R = R * (# of squares) l l

t t

1 Rectangular Block 4 Rectangular Blocks

R = R (L/W)  R = R (2L/2W) 
= R (L/W) 

6: Wires CMOS VLSI Design Slide 8

 Choice of Metals
 Until 180 nm generation, most wires were aluminum
 Modern processes often use copper
– Cu atoms diffuse into silicon and damage FETs
– Must be surrounded by a diffusion barrier
Metal Bulk resistivity (*cm)
Silver (Ag) 1.6
Copper (Cu) 1.7
Gold (Au) 2.2
Aluminum (Al) 2.8
Tungsten (W) 5.3
Molybdenum (Mo) 5.3

6: Wires CMOS VLSI Design Slide 9

 Sheet Resistance
 Typical sheet resistances in 180 nm process
Layer Sheet Resistance (/)
Diffusion (silicided) 3-10
Diffusion (no silicide) 50-200
Polysilicon (silicided) 3-10
Polysilicon (no silicide) 50-400
Metal1 0.08
Metal2 0.05
Metal3 0.05
Metal4 0.03
Metal5 0.02
Metal6 0.02

6: Wires CMOS VLSI Design Slide 10

 Contacts Resistance
 Contacts and vias also have 2-20 
 Use many contacts for lower R
– Many small contacts for current crowding around
periphery

6: Wires CMOS VLSI Design Slide 11

 Wire Capacitance
 Wire has capacitance per unit length
– To neighbors
– To layers above and below
 Ctotal = Ctop + Cbot + 2Cadj
s w

layer n+1

h2 Ctop

t layer n
Cadj
h1 Cbot
layer n-1

6: Wires CMOS VLSI Design Slide 12

 Capacitance Trends
 Parallel plate equation: C = A/d
– Wires are not parallel plates, but obey trends
– Increasing area (W, t) increases capacitance
– Increasing distance (s, h) decreases capacitance
 Dielectric constant
– = k0
 0 = 8.85 x 10-14 F/cm
 k = 3.9 for SiO2
 Processes are starting to use low-k dielectrics
– k  3 (or less) as dielectrics use air pockets
6: Wires CMOS VLSI Design Slide 13
 M2 Capacitance Data
 Typical wires have ~ 0.2 fF/m
– Compare to 2 fF/m for gate capacitance
400

350

300
M1, M3 planes
s = 320
250 s = 480
s = 640
Ctotal (aF/m)

s=

8
200
Isolated

150 s = 320
s = 480
s = 640
100
s=

8
50

0
0 500 1000 1500 2000
w (nm)

6: Wires CMOS VLSI Design Slide 14

 Diffusion & Polysilicon
 Diffusion capacitance is very high (about 2 fF/m)
– Comparable to gate capacitance
– Diffusion also has high resistance
– Avoid using diffusion runners for wires!
 Polysilicon has lower C but high R
– Use for transistor gates
– Occasionally for very short wires between gates

6: Wires CMOS VLSI Design Slide 15

Lumped Element Models
 Wires are a distributed system
– Approximate with lumped element models
N segments
R R/N R/N R/N R/N
C C/N C/N C/N C/N

R R R/2 R/2

C C/2 C/2 C

L-model -model T-model

 3-segment -model is accurate to 3% in simulation

 L-model needs 100 segments for same accuracy!
 Use single segment -model for Elmore delay
6: Wires CMOS VLSI Design Slide 16
 Example
 Metal2 wire in 180 nm process
– 5 mm long
– 0.32 m wide
 Construct a 3-segment -model
– R =
– Cpermicron =

6: Wires CMOS VLSI Design Slide 17

 Example
 Metal2 wire in 180 nm process
– 5 mm long
– 0.32 m wide
 Construct a 3-segment -model
– R = 0.05 / => R = 781 
– Cpermicron = 0.2 fF/m => C = 1 pF

260  260  260 

167 fF 167 fF 167 fF 167 fF 167 fF 167 fF

6: Wires CMOS VLSI Design Slide 18

 Wire RC Delay
 Estimate the delay of a 10x inverter driving a 2x
inverter at the end of the 5mm wire from the
previous example.
– R = 2.5 k*m for gates
– Unit inverter: 0.36 m nMOS, 0.72 m pMOS

– tpd =
6: Wires CMOS VLSI Design Slide 19
 Wire RC Delay
 Estimate the delay of a 10x inverter driving a 2x
inverter at the end of the 5mm wire from the
previous example.
– R = 2.5 k*m for gates
– Unit inverter: 0.36 m nMOS, 0.72 m pMOS
781 

690  500 fF 500 fF 4 fF

Driver Wire Load

– tpd = 1.1 ns
6: Wires CMOS VLSI Design Slide 20
 Crosstalk
 A capacitor does not like to change its voltage
instantaneously.
 A wire has high capacitance to its neighbor.
– When the neighbor switches from 1-> 0 or 0->1,
the wire tends to switch too.
– Called capacitive coupling or crosstalk.
 Crosstalk effects
– Noise on nonswitching wires
– Increased delay on switching wires

6: Wires CMOS VLSI Design Slide 21

 Crosstalk Delay
 Assume layers above and below on average are quiet
– Second terminal of capacitor can be ignored
– Model as Cgnd = Ctop + Cbot
 Effective Cadj depends on behavior of neighbors
– Miller effect A B
C
Cgnd adj Cgnd

B V Ceff(A) MCF
Constant
Switching with A
Switching opposite A

6: Wires CMOS VLSI Design Slide 22

 Crosstalk Delay
 Assume layers above and below on average are quiet
– Second terminal of capacitor can be ignored
– Model as Cgnd = Ctop + Cbot
 Effective Cadj depends on behavior of neighbors
– Miller effect A B
C
Cgnd adj Cgnd

B V Ceff(A) MCF
Constant VDD Cgnd + Cadj 1
Switching with A 0 Cgnd 0
Switching opposite A 2VDD Cgnd + 2 Cadj 2
6: Wires CMOS VLSI Design Slide 23
 Crosstalk Noise
 Crosstalk causes noise on nonswitching wires
 If victim is floating:
– model as capacitive voltage divider
Cadj
Vvictim  Vaggressor
Cgnd v  Cadj
Aggressor

Vaggressor
Cadj
Victim
Cgnd-v Vvictim

6: Wires CMOS VLSI Design Slide 24

 Driven Victims
 Usually victim is driven by a gate that fights noise
– Noise depends on relative resistances
– Victim driver is in linear region, agg. in saturation
– If sizes are same, Raggressor = 2-4 x Rvictim
Cadj 1
Vvictim  Vaggressor Raggressor
Cgnd v  Cadj 1 k
Aggressor
Cgnd-a
Vaggressor
Cadj
Rvictim Victim

 aggressor Raggressor  Cgnd a  Cadj  Cgnd-v Vvictim

k 
 victim Rvictim  C gnd v  Cadj 

6: Wires CMOS VLSI Design Slide 25

 Coupling Waveforms
 Simulated coupling for Cadj = Cvictim
Aggressor
1.8

1.5

1.2

Victim (undriven): 50%

0.9

0.6
Victim (half size driver): 16%

Victim (equal size driver): 8%

0.3 Victim (double size driver): 4%

0
0 200 400 600 800 1000 1200 1400 1800 2000

t(ps)

6: Wires CMOS VLSI Design Slide 26

 Noise Implications
 So what if we have noise?
 If the noise is less than the noise margin, nothing
happens
 Static CMOS logic will eventually settle to correct
output even if disturbed by large noise spikes
– But glitches cause extra delay
– Also cause extra power from false transitions
 Dynamic logic never recovers from glitches
 Memories and other sensitive circuits also can
produce the wrong answer

6: Wires CMOS VLSI Design Slide 27

 Wire Engineering
 Goal: achieve delay, area, power goals with
acceptable noise
 Degrees of freedom:

6: Wires CMOS VLSI Design Slide 28

 Wire Engineering
 Goal: achieve delay, area, power goals with
acceptable noise
 Degrees of freedom:
2.0 0.8

– Width 1.8 0.7

Coupling:2Cadj / (2C adj+Cgnd)

1.6
0.6
1.4 WireSpacing
– Spacing 0.5 (nm)
Delay (ns):RC/2

1.2
320
1.0 0.4 480
640
0.8 0.3
0.6
0.2
0.4
0.1
0.2
0 0
0 500 1000 1500 2000 0 500 1000 1500 2000
Pitch (nm) Pitch (nm)

6: Wires CMOS VLSI Design Slide 29

 Wire Engineering
 Goal: achieve delay, area, power goals with
acceptable noise
 Degrees of freedom:
2.0 0.8

– Width 1.8 0.7

Coupling:2Cadj / (2C adj+Cgnd)

1.6
0.6
1.4 WireSpacing
– Spacing 0.5 (nm)
Delay (ns):RC/2

1.2
320
1.0 0.4 480
640
– Layer 0.8
0.6
0.3

0.2
0.4
0.1
0.2
0 0
0 500 1000 1500 2000 0 500 1000 1500 2000
Pitch (nm) Pitch (nm)

6: Wires CMOS VLSI Design Slide 30

 Wire Engineering
 Goal: achieve delay, area, power goals with
acceptable noise
 Degrees of freedom:
2.0 0.8

– Width 1.8 0.7

Coupling:2Cadj / (2C adj+Cgnd)

1.6
0.6
1.4 WireSpacing
– Spacing 0.5 (nm)
Delay (ns):RC/2

1.2
320
1.0 0.4 480
640
– Layer 0.8
0.6
0.3

0.2
0.4
– Shielding 0.2
0
0.1

0
0 500 1000 1500 2000 0 500 1000 1500 2000
Pitch (nm) Pitch (nm)

vdd a0 a1 gnd a2 a3 vdd vdd a0 gnd a1 vdd a2 gnd a0 b0 a1 b1 a2 b2

6: Wires CMOS VLSI Design Slide 31

 Repeaters
 R and C are proportional to l
 RC delay is proportional to l2
– Unacceptably great for long wires

6: Wires CMOS VLSI Design Slide 32

 Repeaters
 R and C are proportional to l
 RC delay is proportional to l2
– Unacceptably great for long wires
 Break long wires into N shorter segments
– Drive each one with an inverter or buffer
Wire Length: l

Driver Receiver

N Segments
Segment
l/N l/N l/N

Driver Repeater Repeater Repeater Receiver

6: Wires CMOS VLSI Design Slide 33

 Repeater Design
 How many repeaters should we use?
 How large should each one be?
 Equivalent Circuit
– Wire length l/N
• Wire Capaitance Cw*l/N, Resistance Rw*l/N
– Inverter width W (nMOS = W, pMOS = 2W)
• Gate Capacitance C’*W, Resistance R/W

6: Wires CMOS VLSI Design Slide 34

 Repeater Design
 How many repeaters should we use?
 How large should each one be?
 Equivalent Circuit
– Wire length l
• Wire Capacitance Cw*l, Resistance Rw*l
– Inverter width W (nMOS = W, pMOS = 2W)
• Gate Capacitance C’*W, Resistance R/W
RwlN

R/W
Cwl/2N Cwl/2N C'W

6: Wires CMOS VLSI Design Slide 35

 Repeater Results
 Write equation for Elmore Delay
– Differentiate with respect to W and N
– Set equal to 0, solve

l 2 RC 

N RwCw
t pd
 
~60-80 ps/mm
 2 2 RC RwCw
l in 180 nm process
RCw
W
RwC 
6: Wires CMOS VLSI Design Slide 36