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    Bus Organization of 8085

    Uploaded by

    michaeledem_royal
    The 8085 microprocessor uses a multiplexed address/data bus configuration where the lower 8 address lines (AD0-AD7) are time shared with the 8-bit data bus (D0-D7). An external latch is needed to demultiplex and separate the address and data on these shared lines. The address latch enable (ALE) signal is used to latch the lower address bits during the first clock cycle when they are on the bus, then the latched address is used for the full multi-cycle memory access while the shared lines carry data in later cycles. This allows the 8085 to have a full 16-bit address bus using only 16 pins by multiplexing the lower address bits onto the bidirectional data

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    Bus Organization of 8085

    Uploaded by

    michaeledem_royal
    112 views14 pages
    The 8085 microprocessor uses a multiplexed address/data bus configuration where the lower 8 address lines (AD0-AD7) are time shared with the 8-bit data bus (D0-D7). An external latch is needed to demultiplex and separate the address and data on these shared lines. The address latch enable (ALE) signal is used to latch the lower address bits during the first clock cycle when they are on the bus, then the latched address is used for the full multi-cycle memory access while the shared lines carry data in later cycles. This allows the 8085 to have a full 16-bit address bus using only 16 pins by multiplexing the lower address bits onto the bidirectional data

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    The 8085 microprocessor uses a multiplexed address/data bus configuration where the lower 8 address lines (AD0-AD7) are time shared with the 8-bit data bus (D0-D7). An external latch is needed to demultiplex and separate the address and data on these shared lines. The address latch enable (ALE) signal is used to latch the lower address bits during the first clock cycle when they are on the bus, then the latched address is used for the full multi-cycle memory access while the shared lines carry data in later cycles. This allows the 8085 to have a full 16-bit address bus using only 16 pins by multiplexing the lower address bits onto the bidirectional data

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    112 views14 pages

    Bus Organization of 8085

    Uploaded by

    michaeledem_royal
    The 8085 microprocessor uses a multiplexed address/data bus configuration where the lower 8 address lines (AD0-AD7) are time shared with the 8-bit data bus (D0-D7). An external latch is needed to demultiplex and separate the address and data on these shared lines. The address latch enable (ALE) signal is used to latch the lower address bits during the first clock cycle when they are on the bus, then the latched address is used for the full multi-cycle memory access while the shared lines carry data in later cycles. This allows the 8085 to have a full 16-bit address bus using only 16 pins by multiplexing the lower address bits onto the bidirectional data

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    of 14

    Bus Organization of 8085

    1
    System bus
    CPU Memory Input/Output

    Control Bus

    Address Bus

    Data Bus

    System Bus
    2
    Bus Organization of 8085
    A15
    Address Bus
    A0

    Memory Input

    8085 MPU Output Real


    World

    D7
    Data Bus
    D0

    Control Bus
    Address Bus
    • Group of 16 unidirectional lines generally
    identified as A0 to A15.
    i.e. bits flow from microprocessor to
    peripheral devices.

    • 16 address lines are capable of addressing


    65536 memory locations. So, 8085 has 64K
    memory locations.

    4
    Bus Organization of 8085
    A15
    Address Bus
    A0

    Memory Input

    8085 MPU Output Real


    World

    D7
    Data Bus
    D0

    Control Bus
    Data Bus

    • Group of 8 lines identified as D0 to D7.


    • They are bidirectional i.e. data flow in both directions
    between microprocessor, memory & peripheral.

    • 8 data lines enable microprocessor to manipulate data


    ranging from 00H to FFH (28=256 numbers).

    • Largest number appear on data bus is 1111 1111 =>


    (255)10.
    • As Data bus is of 8-bit, 8085 is known as 8-bit
    Microprocessor.
    6
    Bus Organization of 8085
    A15
    Address Bus
    A0

    Memory Input

    8085 MPU Output Real


    World

    D7
    Data Bus
    D0

    Control Bus
    Control Bus
    • It comprises of various single lines that carry
    synchronization, timing & control signals.

    • These signals are used to identify a device type


    with which MPU intends to communicate.

    • Some control signals are Read, Write and


    Opcode fetch etc.

    8
    Multiplexed AD7-AD0
    • The address bus has 8 signal lines A8 - A15 which are
    unidirectional.

    •The other 8 address bits are multiplexed (time shared) with


    the 8 data bits.

    •So, the bits AD0 - AD7 are bi-directional and serve as A0 - A7


    and D0 - D7 at the same time.

    •During the execution of the instruction, these lines carry the


    address bits during the early part, then during the late parts of
    the execution, they carry the 8 data bits.
    Demultiplexing AD7-AD0
    •From the above description, it becomes obvious that the
    AD7- AD0 lines are serving a dual purpose and that they
    need to be demultiplexed to get all the information.

    •In order to separate the address from the data, we can use a
    latch to save the value before the function of the bits
    changes.

    •The high order bits of the address remain on the bus for
    three clock periods.
    .
    •However, the low order bits remain for only one clock
    period and they would be lost if they are not saved
    externally.
    Demultiplexing AD7-AD0
    •Also, notice that the low order bits of the address
    disappear when they are needed most.

    •To make sure we have the entire address for the full three
    clock cycles, we will use an external latch to save the value
    of AD7- AD0 when it is carrying the address bits.

    •The ALE
    . signal is used to enable this latch.
    Demultiplexing AD0-AD7
    A15 0 A15
    0 A14
    1 A13
    0 High-Order
    A12
    8085 Microprocessor

    0 A11 Address Bus


    0 A10
    0 A9
    A8 0 A8
    Enable G ALE=1
    ALE
    AD7 0 A7
    0 A6 Address Bus
    0 A5
    0 A4 Low-Order
    1 A3
    0 A2 Address Bus
    1 A1
    AD0 1 A0

    0 ALE= 0
    1 D7 Data Bus
    0 D6
    0 D5
    1 D4 Data Bus
    1 D3
    1 D2
    1 D1 12
    D0
    Demultiplexing AD7-AD0
    •Given that ALE operates as a pulse during T1, we will be
    able to latch the address.

    •Then when ALE goes low, the address is saved and the AD7-
    AD0 lines can be used for their purpose as the
    bi-directional data lines.

    •The high order address is placed on the address bus and


    hold for 3 clock periods
    Demultiplexing AD7-AD0
    •The low order address is lost after the first clock period,
    this address needs to be hold however so a latch needs to be
    use

    •The address AD7 - AD0 is connected as inputs to the latch


    74LS373.

    •The ALE signal is connected to the enable (G) pin of the


    latch and the Output control (OC) of the latch is grounded

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