Microprocessor and Interfacing Techniques: (Course Code: CET208A) Credits-3

Microprocessor and Interfacing Techniques
(Course Code: CET208A)

Credits-3
School of Computer Engineering and Technology
10/09/2021 Microprocessor and Interfacing Techniques (CET208A) _T5_S Y BTech_ School of Computer Engineering & Technology_ 2020-21 1
Microprocessor and Interfacing Techniques CET208A
Examination scheme:
Continuous Assessment: 50 Marks, End Semester: 50 Marks
Course Objectives:
1. To understand fundamental concepts of architecture and programming of 8086 Microprocessor.
2. To comprehend memory organization of 8086 Microprocessor and its interfacing with input-output
devices.
3. To make the students aware of peripheral ICs and their interfacing with 8086 Microprocessor.
4. To study working of NDP and Motherboard of IBM PC.
Course Outcomes:Upon completion of the course, the students will be able to:
1. Explain architecture and programming model of microprocessor 8086 and develop assembly language
programs for various applications.
2. Demonstrate memory organization of microprocessor 8086 and design interface of 8086 with memory
and peripheral devices.
3. Illustrate the concept of serial communication and interrupt handling.
4. Summarize the motherboard functional blocks along with NDP 8087.
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Syllabus
Unit 1 - 8086 Architecture: Architecture and Functional Pin description of 8086,
Programmers model (Register Set) and Segmentation of 8086, logical to physical
address translation, Addressing modes, Instruction set of 8086 in detail, 8086
Programming examples.
Assembly Language Programming, Assembler, Linker, Debugger, Directives,
Procedures (Near & Far), Macros, Loop constructs.
Unit 2 -Memory and I/O Interfacing: Memory/I/O Read/write cycle timing
diagrams, Memory and I/O space of 8086. Memory organization: even and odd banks.
Address decoding for memory/IO interfacing. Using NAND gate and Decoder.
Programmable Peripheral Interface 8255: Features, Block Diagram, Control & status
registers, Operating modes & Interfacing Concept of ADC and DAC
Microprocessor and Interfacing Techniques (CET208A) _T5_S Y BTech_ School of Computer

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Syllabus
Unit 3 - Study of Peripherals: Serial Communication- Synchronous
&Asynchronous, Universal Synchronous Asynchronous Receiver
Transmitter USART 8251: Features, Block Diagram, Control & status
registers, Operating modes, Interfacing & Programming. Programmable
Interrupt Controller 8259: Features, Block Diagram, ICWs, Operating
modes & Interfacing
Unit 4 – Math Controller & Study of Motherboard: 8087(NDP)
Features, Block Diagram, Control & status registers, typical Instruction Set
& Programming. Study of IBM PC Motherboard, functional description
of Blocks (Overview of 8237, 8254, 8279).
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Syllabus: Laboratory Exercises / Practical:
1. Accept a character string from user and display the same.
2. Write X86/64 Assembly language program (ALP) to convert 4-digit HEX number to its
equivalent BCD number.
3. Write X86/64 Assembly language program (ALP) to add array of ten (10) - 8 bit hexadecimal
numbers stored in the memory.
4. Write X86/64 ALP for the following operations on the string entered by the user a) Calculate
length of string b) Reverse the string c) Check palindrome.
5. Write 8086 ALP to interface DAC through 8255 and generate following waveforms on
oscilloscope, (i) Square wave - Variable Duty Cycle and Frequency. (ii) Ramp wave - Variable
direction (iii) Trapezoidal wave (iv) Stair case wave. (Demo)
6. Perform an experiment to establish communication between two 8251 systems A and B.
Program 8251 system A in asynchronous transmitter mode and 8251 system B in asynchronous
receiver mode. Write an ALP to transmit the data from system A and receive the data at system
B.
OR
Inline C programming (Directory creation and Delete) / PC to PC communication.


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Reference Books:
1. N. Mathivanan ,“ Microprocessors, PC Hardware and Interfacing”,
Prentice-Hall India, ISBN-81-203-2317-3.
2. A. Ray, K. Bhurchandi , ”Advanced Microprocessors and peripherals:

Arch, Programming & Interfacing”, Tata McGraw Hill, ISBN 0-07-
463841-6, 2004.
3. Introduction to 64 bit Intel Assembly Language Programming for

Linux, 2nd Edition, Ray Seyfarth, ISBN10:1478119209, ISBN-13:
9781478119203, 2012

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Unit I: 8086 Architecture
• Architecture and Functional Pin description of 8086
• Programmers model (Register Set)
• Segmentation of 8086
• logical to physical address translation
• Addressing modes
• Instruction set of 8086 in detail
• 8086 Programming examples
• Assembly Language Programming
• Assembler, Linker, Debugger, Directives
• Procedures (Near & Far)
• Macros, Loop constructs
Introduction to Microprocessor
A microprocessor is a computing device which can do
Arithmetic computations - ADD, SUBTRACT, MULTIPLY etc.

Logical computations – AND, OR, XOR, NOT, etc.
Data transfer

To successfully compute data, processor should have minimally -
• An Arithmetic and logical unit – main computation unit
• A set of registers to hold data / result

Processor’s Language
• Every Processor can execute an instruction in BINARY and
operate only on BINARY numbers.
• Thus, processor’s native language is BINARY LANGUAGE
• To define instructions and operands in BINARY is tedious
• To simplify user’s work, processor provides a simpler form of

this language called ASSEMBLY LANGUAGE
What is Assembly Language?
• Every processor defines a set of instructions and provides the syntax
to use them.
• These instructions and its syntax are unique to a processor and is
called its Assembly Language
• An instruction defines –
Operation type
Operands
• Instructions are to be written by the user in external memory at a
specific address
Example of some instructions written in memory
Address Instruction
ADD reg1, reg 2 0000H Add reg1, reg2
MOV reg1, data 0001H Mov reg1,data
SUB reg2, reg3 0002H Sub reg2, reg3

Processor also includes
A mechanism to access instruction from external memory
A unique register to hold instruction
A decoder to decode this instruction
A control unit to generate necessary signals to execute the

instruction

What is the mechanism to access instruction?
 Every processor has a unique register, an Instruction Pointer, to hold
address of the instruction in memory
 To carry this address to memory unit, it has a set of wires called address bus
 To define whether read or write operation, it has two signals READ and
WRITE
 To read instruction, it has a set of wires called data bus.
 To read instruction is loaded in Instruction Register

More about the data bus
Data bus is also used to read or write data to memory
Data can be operands or instruction
It is a bidirectional bus

Processor Architecture
A processor would minimally
have the following components – All these functional units are
connected to each other for
 data movement and are
ALU
synchronized with a common
 A set of registers reference signal CLOCK.
 Instruction register Each one with its unique
 Instruction decoder and features and this
interconnectivity defines the
 Control unit
maximum clock speed at
 Instruction Pointer which a processor can
operate.
All this put together is called as
architecture of the processor.
Performance parameters of a processor
• Clock speed – defines the maximum computing speed of the processor
can operate.
• Size of data bus – defines the maximum bandwidth of data transfer from
or to the processor.
Address bus Memory
• Size of address bus – defines the width accessed
maximum addressing capacity of
4 bit 16 bytes
the processor.
8 bit 256 bytes
16 bits 64 Kbytes
20 bit 1 MBytes

Performance parameters of a processor
The operand width –
•Defines the width/size of the register holding

Operand Maximum
data width Operand
•Defines the greatest unsigned number that the 4 bit 15
ALU can compute on 8 bit 255
•Thus defines the computing ability of the
16 bit 65,535
processor
The ALU – the design of ALU defines different

operations that a processor can perform
Stephen Morse: Father of the 8086 Processor
Intel introduced the 8086 processor in 1979 …
Stephen Morse was the lead development engineer for

the same…
This 30-year-old architecture still influences PCs today !!
Introduction of 8086 Architecture
• 8086 Microprocessor is an enhanced version of 8085 Microprocessor
that was designed by Intel in 1976.
• It is a 16-bit Microprocessor
• 20 address lines and
• 16 data lines
• 1MB storage
• It supports two modes of operation, i.e. Maximum mode and
Minimum mode.
1. Maximum mode: It is suitable for system having multiple processors.
2. Minimum mode: It is suitable for system having a single processor.
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Features of 8086
It has an instruction queue, which is capable of storing six instruction bytes
from the memory resulting in faster processing.
It was the first 16-bit processor having 16-bit ALU, 16-bit registers, internal
data bus, and 16-bit external data bus resulting in faster processing.
It is available in 3 versions based on the frequency of operation −
1. 8086-1 → 5MHz
2. 8086-2 → 8MHz
3. 8086-3 → 10 MHz
It uses two stages of pipelining, i.e. Fetch Stage and Decode Execute Stage,
which improves performance.
It has 256 vectored interrupts.
8086 –detail architecture (Block diagram)
Basic Architecture of 8086
The Bus Interface Unit (BIU)
It is processor’s connection to
outside world. It performs –
Memory
• Instruction fetching
• Reading and writing of
data operands from / to
Input BIU Output
memory Device (CPU) Device
• Inputting or outputting
data from / to devices
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BIU contd….
To perform these functions it has
• Segment registers
• Instruction Pointer
• Address generation Adder
• Bus Control logic
• Instruction Queue

What is an Instruction Queue ?
• It is a 6 byte FIFO data structure
• It permits to pre fetch 6 bytes of instruction
INS 3 (H)
INS 3 (L)
Memory INS 2 (H) Instruction register
INS 2 (L)
INS 1 (H)
INS 1 (L)
Prefetch CU
When does the BIU Prefetch ?…
Whenever the instruction
queue is not full and has room
for at least 2 more bytes
AND
at the same time the execution
unit is not asking it to read or
write data to or from memory
The BIU is free to Prefetch the

next sequential instruction
The Execution Unit
The execution Unit is responsible for
Decoding and Executing Instructions.
To perform this it has –
An ALU
Status and control flags
General purpose registers
Temporary operand registers
Accesses instruction from the output
end of the Queue
Reads data from general purpose
registers or Memory
The Execution Unit
• It decodes the instruction.
• Generates addresses for data if
necessary
• Instructs BIU to read or write
data from/to memory
• Performs specified operation
• Updates the flags
• If the Queue is empty EU has to
wait till the instruction is
fetched..

Programmers Model
The programming model for a microprocessors show the
various internal registers that area accessible to the
programmer.
To use the processor, programmer needs to know

• The registers available, their purpose and use
• The way external memory is organized
• The way I/O devices are organized
• Addressing modes available

Programmers Model
Thus each program has and needs separate
• CODE Segment
• DATA Segment
• STACK Segment
• Extra Segment: is an additional Data segment and is used when required.
This memory is made available to a program by the Operating System
8086 provides 16 bit four segment registers which point to each of the
segment:
• Code Segment Register points to base of the CODE segment
• Data Segment Register points to base of the Data Segment
• Stack Segment Register points to base of the Stack Segment
• Extra Segment Register points to base of the Extra Segment
Programmers Model
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8086 Registers
General Purpose Index
AH AL
BP
AX
SP
BH BL
BX
SI
CH CL
DI
CX
DH DL
DX Segment
CS
Status and Control SS
Flags DS
IP ES

General Purpose Registers
AX - Accumulator
BX - Base Register
CX - Count Register
DX - Data Register
Normally used for storing temporary results

Each of the registers is 16 bits wide (AX, BX, CX, DX)
Can be accessed as either 16 or 8 bits AX, AH, AL
•AX
• Accumulator Register
• Preferred register to use in Arithmetic, Logic and Data transfer
instructions because it generates the shortest Machine Language Code
• Must be used in Multiplication and Division operations
• Must also be used in I/O operations
•BX
• Base Register
• Also serves as an address register

• CX
–Count register.
–Used as a loop counter.
–Used in shift and rotate operations.
• DX
–Data register
–Used in Multiplication and Division
–Also used in I/O operations
Pointer and Index Registers
•All 16 bits wide, L/H bytes are not accessible

•Used as memory pointers
Example: MOV AH, [SI]
Move the byte stored in memory location whose address is contained in register SI to register AH
•IP is not under direct control of the programmer.
Flag Register
* Unused flags
Overflow Carry
Direction Parity
Interrupt enable Auxiliary Carry

Trap Zero
6 are status flags
8086 has 16 bit flag to indicate the
status of final arithmetic result. Sign 3 are control flag
Zero Flag
The zero flag will be set (1) whenever the result is zero.
Parity flag
The parity flag will be set whenever the number of bit “1” are even.

Carry flag
Carry flag will be set whenever there is a carry or borrow
(only with unsigned operation).

Overflow flag
Overflow flag will be set whenever the result is overflow
(with signed operation).

Sign flag
Sign flag will be set whenever the result is negative with
signed operation.

More flags
Auxiliary flag will be set when the result of BCD
operation need to be adjusted.
Direction flag is used to specify direction (increment

/decrement index register) in string operation.
Trap flag is used to interrupt CPU after each operation.

Interrupt flag is used to enable/disable hardware
interrupt.
8086 Programmer’s Model
ES Extra Segment
CS Code Segment
BIU registers SS Stack Segment
(20 bit adder)
DS Data Segment
IP Instruction Pointer
AX AH AL Accumulator
EU registers BX BH BL Base Register
CX CH CL Count Register
DX DH DL Data Register
SP Stack Pointer
BP Base Pointer
SI Source Index Register
DI Destination Index Register
FLAGS
Programmers Model
The Stack
• The stack is used for temporary storage of
information such as data or addresses.
• When a CALL is executed, the 8086

automatically PUSHes the current value
of CS and IP onto the stack.
Other registers can also be pushed
Before return from the subroutine, POP

instructions can be used to pop values back
from the stack into the corresponding
registers.

The Stack: Example
Example: Assuming that SS = 1000h and SP = 0xF820. This means that current
stack top is the physical address 0x1F820 (this is due to memory segmentation in 8086).
The next two machine instructions of the program are:
PUSH AX
PUSH BX
• These first instruction shall push the value stored in AX (16-bit register) to the stack.
This is done by subtracting a value of 2 (2 bytes) from SP.
• The new value of SP becomes 0xF81E. The CPU then copies the value of AX to the
memory word whose physical address is 0x1F81E.
• When "PUSH BX" is executed, SP is set to 0xF81C and BX is copied to 0x1F81C

The Stack: Example
To restore the values stored at the stack, the program uses instructions like:
POP BX
POP AX
POP BX copies the word at 0x1F81C (which is the old value of BX) to BX,
then increases SP by 2. SP now is 0xF81E.
POP AX copies the word at 0x1F81E to AX, then sets SP to 0xF820.

The program above pops BX first, that's because it was pushed last.
In 8086, PUSH & POP instructions can only work with 16-
bit elements.
Memory Segmentation of 8086
Concept of Segmented Memory
• It allows the memory addressing capacity to be 1 Mbytes.
• It allows instruction code, data stack and portion of program to
be more than 64KB long.
• It facilitates use of separate memory areas for Program
(Code), Data and Stack.
• It permits a program or its data to be put in different areas of
memory
• In this program can be relocated which is very useful in
multiprogramming i.e. multitasking becomes easy.
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Logical to Physical address translation
Addressing Modes: DB=16 Memory Access MOV AL,[1234H]
0
DS=2000 H+1234=21234H PA=20 DS=16 bit ,CS,SS,ES
Offset Value (16 bits)
Segment Register (16 bits) 0 0 0 0
Adder
Physical Address (20 Bits)
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Rotate CS contents by 1 digit i.e. 4 bits left
Insert 4 Zeroes there
Add 16 bit IP contents to it
CS
16-bit Segnment Base Address 0000
IP
16-bit Offset Address
20-bit Physical Address


The logical address of an instruction always consists of a CS (code segment)
and an IP (instruction pointer), shown in CS:IP format
The Memory as seen by 8086
The segment registers are 16 bit in size.
A segment register points to a block of 64Kbytes of memory.
Each segment register can track or access such 16 blocks (2 16 = 64KB)
16 X 64KB = 1MB
The address bus of 8086 is 20 bit which implies it can access 1MB of memory
The instruction pointer points to every instruction within a 64KB block of CODE
Memory
The Index Registers point to data variables / bytes within a block of 64KB of DATA
memory
The Stack pointer tracks the stack variables within a 64KBblock of STACK Memory
CS : IP Physical Address
0000 : 0000 00000 The maximum memory which 8086 can access using
0000 : FFFF 0FFFF
1000 : 0000 10000
20bit address bus
1000 : FFFF 1FFFF = 1 MB
2000 : 0000 20000
2000 : FFFF 2FFFF
3000 : 0000 30000 Total number of blocks of 64KB each
3000 : FFFF 3FFFF = Total Memory / Block size
= 1MB / 64 KB = 16
A000 : 0000 A0000
A000 : FFFF AFFFF
B000 : 0000 B0000 Only 4 blocks or segment are active at a time in
B000 : FFFF BFFFF memory :
C000 : 0000
C000 : FFFF
C0000
CFFFF CODE segment
D000 : 0000 D0000 DATA segment
D000 : FFFF DFFFF
STACKsegment and the
E000 : 0000 E0000
E000 : FFFF EFFFF EXTRA segment
F000 : 0000 F0000
F000 : FFFF FFFFF
Active memory = 4 x 64 KB = 256KB
Memory Segmentation & Re-locatability
• Memory is a group of ‘n’ 64K blocks as seen by 8086 processor
• wherein n= 16 (16 X 64K = 1MB : the max. addressable memory by 8086)
• Each memory location has two addresses – Base and Offset
• Base address is the address of the first line / byte of a 64K block or segment
• Offset address is the line / byte number from base of a block
• Base address is defined by OS at run time
• Offset address defined by Compiler at compilation time
• This two dimensional addressing makes a program “Relocatable” i.e. a
program may get loaded in any block available and still be executed
successfully.
• Base address defined in Segment Register
• Offsets in IP or Index registers
Memory The Physical or Actual Address
Addr. Data/Instr CS : IP
0000 : 0005H
IP 0005H 0005H I6H
IP 0004H 0004H I5H 0000 : 0004H
IP 0003H 0003H I4H
0000 : 0003H
IP 0002H 0002H I3H
IP 0001H 0001H I2H 0000 : 0002H
0000H I1H 0000 : 0001H
IP 0000H
Instruction Pointer 0000 : 0000H

0000H
Code Segment Register

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Addressing Modes
Operands can be in registers as well as in memory
Method of specifying an operand is called as addressing mode
8086 supports following addressing modes
1. Immediate
2. Register
3. Direct
4. Register indirect or indirect memory
5. Base Addressed (BX or BP)
6. Indexed (SI or DI)
7. Base indexed (BX /BP + SI/DI)
8. Base Indexed with displacement / Relative based indexed
addressing mode (BX + SI +displacement)
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Immediate Addressing
Immediate addressing eg. : MOV al, 20H
To load data in a register – say AX
Assume AX = 00H
0000H
After Executing
MOV AX, 1234H
MOV AH, 12H
MOV AL, 34H

REGISTER ADDRESSING
To transfer data from one register to the other
Assume AX = 1234H and BX = 0000H
MOV BX, AX
MOV BH, AH
MOV BH, AL
MOV BH, AX
ERROR
MOV BX, AH
DIRECT ADDRESSING
The addressing mode in which the effective address of the

memory location is written directly in the instruction
Data M.L.
MOV AX,[5000H] 22 5000
33 22 33 5001
AH AL 5002

For accessing data in memory
1.Direct addressing eg. : MOV AL,[3000h]
2.Register indirect eg. : MOV [DI], BX
Example: MOV al, [si]
Assume DS = 1000H, SI = 0010H
EA = SI = 0010H
Physical Address = (DS * 10h) + EA
= 10000H + 0010H
= 10010H
3. Base plus index addressing eg. : MOV AL, [BX+SI]
Assume DS = 1000H, SI = 0010H, BX = 0100H
MOV AL, [BX+SI] ; DS:BX+SI

EA = BX + SI
= 0100 + 0010H
= 0110H
Physical Address = (DS * 10h) + EA
= 10000H + 0110H
= 10110H
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4.Register relative addressing eg.: MOV CX, [Bx+0004H]
5.Base relative-plus index addressing eg.: MOV AL,[BX+SI+10H]
6.String addressing modes eg. MOVSB, CMPSB
Addressing mode for accessing I/O ports

OUT 05H, AL
IN AX, 80H
IN AL, DX
Assembly Language Program Development Tools
There are several tools available to support the programmer
of assembly language for better experience of programming.
They are as follows:
•
Editor
•
Assembler
•
Linker
•
Debuggers
The flow chart of ALP Tools
Edit
prog.asm
Assemble
library.lib prog.obj prog.lst
Link
prog.exe prog.map
Debug Run
The flow chart of ALP Tools
ALP Tools :Editor
Editor
• Write new (.asm) programs
• Make changes to existing ones
Example: gedit, a GNU editor
ALP Tools : Assembler
An assembler basically does the following –

1. Assign offset address to all memory references (data variables,
instructions, labels)
2. Convert the assembly language code to machine language
3. Check the syntax of the code and report errors if any
4. Create an object file and .lst file
Example :NASM - The Netwide Assembler
ALP Tools : Linker
Linking Multiple Files
Example: Ld – GNU Linker

• Linker can read, combine and
write object files in many
different formats .
• Different formats may be

linked together to produce any
available kind of object file.
ALP Tools : Loader
The loader is a part of the operating system that will load
the program from secondary storage into primary storage
(i.e., main memory).
The loader is implicitly invoked by typing the executable

program name.
ALP Tools : Debugger
•Traces program execution
Either step-by-step, or
Using breakpoints
•It shows:
Source (.asm) code
Registers
Memory contents with address
Instruction set of 8086
Instructions in 8086 are mainly divided into following categories:

Data Transfer Instructions

Arithmetic Instruction

Bit manipulation Instruction

String Instruction

Program execution transfer Instruction

Processor control Instruction
Instruction to transfer a word
MOV − copy the byte or word from the source to the destination.
PUSH − put a word at the top of the stack.
POP − get a word from the top of the stack to the provided location.
PUSHA − put all the registers into the stack.
POPA − get words from the stack to all registers.
XCHG − exchange the data from two locations.
XLAT − translate a byte in AL using a table in the memory.
Instructions for input and output port transfer

IN − read a byte or word from port to the accumulator.
OUT − send out a byte or word from the accumulator to the port.
Instructions to transfer the address
LEA − load the address of operand into the provided register.
LDS − load DS register and other provided register from the memory
LES − load ES register and other provided register from the memory.
Instructions to transfer flag registers
LAHF − load AH with the low byte of the flag register.
SAHF − store AH register to low byte of the flag register.
PUSHF − copy the flag register at the top of the stack.
POPF − copy a word at the top of the stack to the flag register.
Data Transfer Instructions :MOV
MOV Des, Src:
It is used to copy the content of Source(Src) to Destination(Des)
Src operand can be register, memory location or immediate operand.
Des can be register or memory operand.
Both Src and Des cannot be memory location at the same time.
E.g.:
MOV CX, 037A H
MOV AL, BL
MOV BX, [0301 H]
Data Transfer Instructions :MOV
PUSH Operand:
It pushes the operand into top of stack.
E.g.: PUSH BX
POP Des:
It pops the operand from top of stack to Destination.
Des can be a general purpose register, segment register (except CS) or memory
location.
E.g.: POP AX
PUSHF - Copies Flag register on Top of stack

POPF - Copies Top of stack in Flag Register
Data Transfer Instructions using Stack
LIFO stack
TOS SP  0008 H 0008H
PUSH AX :
TOS SP  0006 H AL AH
PUSH AX :
0008H
0006 H AL AH
TOS SP  0004 H BL BH
Data Transfer Instructions :
XCHG Des, Src:
This instruction exchanges Src with Des.
It cannot exchange two memory locations directly.
E.g.: XCHG DX, AX
IN Accumulator, Port Address:
It transfers the operand from specified port to accumulator register.
E.g.: IN AX, 0028 H
OUT Port Address, Accumulator:
It transfers the operand from accumulator to specified port.
E.g.: OUT 0028 H, AX
XLAT/XLATB
load in AL reg [BX+AL]
section .data
arr db 30h, 31h, 32h, 33h, 34h, 35h, 36h, 37h, 38h, 39h,, 41h, 42h, 43h, 44h,45h,46h
Section .text
Global _start
_start:
----
MOV BX, arr
MOV AL, 05 +5 BX
XLATB
30h 31h 32h 33h 34h 35h 36h 37h ------ 46h
---
End
AL = [BX+05] = 35h
LEA Register, Src:
It loads a 16-bit register with the offset address of the data specified by the Src.
E.g.: LEA BX, [DI]

This instruction loads the contents of DI (offset) into the BX register.
LDS Des, Src:
It loads 32-bit pointer from memory source to destination register and DS.
The word is placed in the destination register and the segment is placed in DS.
This instruction Copies the word at the lower memory address to the Des reg and
the word at the higher address to the segment reg i.e. DS.
LDS dest,src (Load pointer using DS)
• Load two 16 bit registers from a 4 byte block of memory.

• First 2 bytes are copied into dest register.
• Second 2 bytes are copied into DS register.
Address Memory
Ex: DS=0100,SI=0020 01020 30
Command: LDS DI,[SI] 01021 F0
01022 80
Physical addr=01020 01023 90
Result:DI = F0 30 01024
DS= 90 80
LAHF:
It copies the lower byte of flag register to AH.
SAHF:
It copies the contents of AH to lower byte of flag register.
PUSHF:
Pushes flag register to top of stack.
POPF:
Pops the stack top to flag register.
Arithmetic instructions
Instructions to perform addition
ADD − add the provided byte to byte/word to word.
ADC − add with carry.
INC − increment the provided byte/word by 1.
AAA − adjust ASCII after addition.
DAA − adjust the decimal after the addition/subtraction operation.
Instructions to perform subtraction
SUB − subtract the byte from byte/word from word.
SBB − subtraction with borrow.
DEC − decrement the provided byte/word by 1.
NEG − negate each bit of the provided byte/word and add 1/2’s complement.
CMP − compare 2 provided byte/word.
AAS − adjust ASCII codes after subtraction.
DAS − adjust decimal after subtraction.

Instruction to perform multiplication
MUL − multiply unsigned byte by byte/word by word.
IMUL - multiply signed byte by byte/word by word.
AAM − adjust ASCII codes after multiplication.
Instructions to perform division

DIV − divide the unsigned word by byte or unsigned double word by word.
IDIV − divide the signed word by byte or signed double word by word.
AAD − adjust ASCII codes after division.
CBW − fill the upper byte of the word with the copies of sign bit of the lower byte.
CWD − fill the upper word of the double word with the sign bit of the lower word.
ADD Des, Src: ADC Des, Src:
It adds a byte to byte or a word It adds the two operands with
to word. CF.
It effects AF, CF, OF, PF, SF, ZF It effects AF, CF, OF, PF, SF,
flags. ZF flags.
E.g.: E.g.:
ADD AL, 74H ADC AL, 74H
ADD DX, AX ADC DX, AX
ADD AX, [BX] ADC AX, [BX]
Microprocessor and Interfacing Techniques (CET208A) _T5_S Y BTech_ School of Computer Engineering & Technology_
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SUB Des, Src: SBB Des, Src:
It subtracts a byte from byte or a It subtracts the two operands and
word from word. also the borrow from the result.
It effects AF, CF, OF, PF, SF, ZF It effects AF, CF, OF, PF, SF, ZF
flags. flags.
For subtraction, CF acts as borrow E.g.:
flag. SBB AL, 74H
E.g.:
SBB DX, AX
SUB AL, 74H
SBB AX, [BX]
SUB DX, AX
SUB AX, [BX]
10/09/2021 2020-21 90
DAA (Decimal Adjust after
Example: If AL = 35H, BL = 47H
Addition) ADD AL,BL
It is used to make sure that the DAA
result of adding two BCD
numbers is adjusted to be a AL = 7CH
correct BCD number. Thus with DAA
It only works on AL register. 7+0 and C+6 => 82

For Subtraction : DAS
Implied Addressing Mode
(Decimal Adjust after
Subtraction)
AAA (ASCII Adjust after Addition):
Implied Addressing Mode
Converts number in AL register from
ASCII to Hex
i.e. If lower nibble of AL > 9 then Other ASCII Instructions:
1. AL=AL+6 AAS (ASCII Adjust after
Subtraction)
2. AH=AH+1
AAM (ASCII Adjust after
3. AL=AL AND 0FH Multiplication)
This instruction does not have any AAD (ASCII Adjust Before
operand. Division)
Example: AL = 34H & BL = 33H
ADD AL, BL
AAA
Will result in AL= 07H
MUL Src:
It is an unsigned multiplication instruction.
It multiplies two bytes to produce a word or two words to produce a double word.
AX = AL * Src
DX : AX = AX * Src
This instruction assumes one of the operand in AL or AX.
Src can be a register or memory location. And Flags-OF, CF
Unused bits of destination register is always filled with sign bit
IMUL Src:
It is a signed multiplication instruction.
10/09/2021 2020-21 93
MUL instruction
8 bit multiplication • 16 bit multiplication
• AL is multiplicand • AX is multiplicand
• AX keep the result • DX:AX keep the result
• MUL Byte[op1] • MUL Word[op1]

• AX = AL * op1 • DX : AX = AX * op1
• MOV AX,0100h ; AX = 0100h

• MOV AL,10h ; AL = 10h
• MOV BX,1234h ; BX = 1234h
• MOV CL,13h ; CL = 13h
• MUL BX ; DX = 0012h
• MUL CL ; AX = 0130h
; AX = 3400h
10/09/2021 2020-21 94
DIV Src:
It is an unsigned division instruction.
It divides word by byte or double word by word.
The operand is stored in AX, divisor is Src and the result is stored as:
AH = remainder, AL = quotient (for word/byte)
DX=remainder, AX=quotient (for D-word/word)
IDIV Src:
It is a signed division instruction.
10/09/2021 2020-21 95
DIV instruction
8 bit division • 16 bit Division

• DIV BYTE[op1] • DIV WORD[op2]
• AX / op1 , AL = Quotient and • DX:AX / op1, AX = Quotient and
AH = Remainder DX = Remainder
• MOV AX, 0017h • MOV AX,4022h

• MOV BX, 0010h • MOV DX,0000h
• DIV BL • MOV CX,1000h
• DIV CX
AX = 0701 ;AX = 0004
;DX = 0022
10/09/2021 2020-21 96
CBW (Convert Byte to Word):
This instruction converts byte in AL to word in AX.
The conversion is done by extending the sign bit of AL throughout AH.
CWD (Convert Word to Double Word):

This instruction converts word in AX to double word in DX : AX.
The conversion is done by extending the sign bit of AX throughout DX.
10/09/2021 2020-21 97
INC Src: DEC Src:
It increments the byte or word by one. It decrements the byte or word by
The operand can be a register or one.
memory location. The operand can be a register or
E.g.: INC AX memory location.
E.g.: DEC AX
INC [SI]
 DEC [SI]
CMP Des, Src:
It compares two specified bytes or words.
The Src and Des can be a constant, register or memory location.
Both operands cannot be a memory location at the same time.
The comparison is done simply by internally subtracting the source from
destination.
The value of source and destination does not change, but the flags CF, ZF, SF are
modified to indicate the result.
NEG Src:
It creates 2’s complement of a given number.
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CMP instruction
CMP reg, imm Example:

CMP reg, mem
CMP reg, reg MOV CX, 10h
CMP mem, reg CMP CX, 20h ;Z=0,S=1,C=1,O=0
MOV BX, 40h
CMP BX, 40h ;Z=1,S=0,C=0,O=0
MOV AX, 30h
There is no “CMP mem, imm” CMP AX, 20h ;Z=0,S=0,C=0,O=0
10/09/2021 2020-21 100
Bit Manipulation instructions
Instructions to perform logical operation
NOT − invert each bit of a byte or word.
AND − adding each bit in a byte/word with the corresponding bit in another byte/word.
OR − multiply each bit in a byte/word with the corresponding bit in another byte/word.
XOR − perform Exclusive-OR operation over each bit in a byte/word with the corresponding bit in another
byte/word.
TEST − add operands to update flags, without affecting operands.
Instructions to perform shift operations

SHL/SAL − shift bits of a byte/word towards left and put zero(S) in LSBs.
SHR − shift bits of a byte/word towards the right and put zero(S) in MSBs.
SAR − shift bits of a byte/word towards the right and copy the old MSB into the new MSB.
Instructions to perform rotate operations
ROL − rotate bits of byte/word towards the left, i.e. MSB to LSB and to Carry Flag [CF].
ROR − rotate bits of byte/word towards the right, i.e. LSB to MSB and to Carry Flag [CF].
RCR − rotate bits of byte/word towards the right, i.e. LSB to CF and CF to MSB.
RCL − rotate bits of byte/word towards the left, i.e. MSB to CF and CF to LSB.
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Instructions to perform logical operation:
NOT − Used to invert each bit of a byte or word.
EX: NOT BX ; Complement contents of BX register.

NOT BYTE[BX] ;Complement memory byte at offset [BX] in data segment
No flags affected
AND − Used for adding each bit in a byte/word with the corresponding bit in another byte/word.
EX: AND CX,[SI]

AND BH,CL
AND BX,00FFH
CF,OF=0
PF,SF,ZF flags affected. AF-Undefinded.
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OR − Used to multiply each bit in a byte/word with the corresponding bit in another byte/word.
EX: OR AH,CL
OR BL,80H
OR CX, TABLE[BX][SI]
CF,OF=0
PF,SF,ZF flags affected. AF-Undefind.
XOR − Used to perform Exclusive-OR operation over each bit in a byte/word with the
corresponding bit in another byte/word.
EX: XOR CL,BH

XOR BYTE[BX],00FFH
CF,OF=0. PF,SF,ZF are updated.AF-Undefined.

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TEST − Used to AND operands to update flags, without affecting operands.
EX: TEST AL,BH ;AND BH with AL, no result stored. Update PF, SF, ZF.
TEST CX,0001H ; AND CX with immediate number 0001H, no result stored.

;Update PF, SF, ZF.
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SHL/SAL Des, Count:

It shift bits of byte or word left, by count.
It puts zero(s) in LSBs.
MSB is shifted into carry flag.
If the number of bits desired to be shifted is 1, then the immediate
number 1 can be written in Count.
However, if the number of bits to be shifted is more than 1, then the
count is put in CL register. And recent bit to the CF (Carry flag)
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SHL src, 1 or SAL src, 1
CF
1 0 0 0 0 0 0 1 0
After shift  reg/mem = 02H, CF = 1
src- reg/mem
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SHR/SAR Des, Count:

It shift bits of byte or word right, by count.
It puts zero(s)(for SHL) and Sign bit (for SAL) in MSBs.
LSB is shifted into carry flag.
If the number of bits desired to be shifted is 1, then the immediate number 1
can be written in Count.
However, if the number of bits to be shifted is more than 1, then the count is
put in CL register. And recent bit to the CF (Carry flag)
SHR src, 1
CF
1 0 0 0 0 0 0 1
0
After Shift  Reg/mem = 01000000, CF = 1
SAR src, 1
CF
1 0 0 0 0 0 0 1
After Rotation  Reg/mem = 11000000, CF = 1
ROL Des, Count:

It rotates bits of byte or word left, by count.
LSB is transferred to MSB and also to CF.
If the number of bits desired to be shifted is 1, then the immediate number
1 can be written in Count.
However, if the number of bits to be shifted is more than 1, then the count
is put in CL register. And recent bit to the CF (Carry flag)
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ROR Des, Count:

It rotates bits of byte or word right, by count.
MSB is transferred to LSB and also to CF.
10/09/2021 2020-21 112
ROL src, 1
CF
1 0 0 0 0 0 0 1
After Rotation - Reg = 00000011, CF = 1
ROR src, 1
After Rotation - Reg =11000000, CF = 1
CF
1 0 0 0 0 0 0 1
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RCL Des, Count:
It rotates bits of byte or word right, by count.
LSB to MSB then MSB is transferred to CF and CF to LSB.
If the number of bits desired to be shifted is 1, then the
immediate number 1 can be written in Count.
However, if the number of bits to be shifted is more than 1,
then the count is put in CL register. And recent bit to the CF
(Carry flag)
10/09/2021 2020-21 114
RCL src, 1
CF
0 1 0 0 0 0 0 0 1
After Rotation - Reg = 00000010, CF = 1
RCR src, 1 After Rotation - Reg =01000000, CF = 1
CF
1 0 0 0 0 0 0 1 0
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RCR Des, Count:
It rotates bits of byte or word left, by count.
MSB to LSB then LSB is transferred to CF and CF to MSB.
String instructions
 String : Sequence of bytes or words
 8086 instruction set includes instruction for string movement, comparison, scan, load and store.
 REP instruction prefix : used to repeat execution of string instructions
 String instructions end with S or SB or SW.

S represents string, SB string byte and SW string word.
 Offset or effective address of the source operand is stored in SI register and that of the
destination operand is stored in DI register.
 Depending on the status of DF, SI and DI registers are automatically updated.
 DF = 0  SI and DI are incremented by 1 for byte and 2 for word.
 DF = 1  SI and DI are decremented by 1 for byte and 2 for word.

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String instructions
REP − repeat the given instruction till CX ≠ 0.
REPE/REPZ − repeat the given instruction until CX = 0 or zero flag ZF = 1.
REPNE/REPNZ − repeat the given instruction until CX = 0 or zero flag ZF = 1.
MOVS/MOVSB/MOVSW − move the byte/word from one string to another.
COMS/COMPSB/COMPSW − compare two string bytes/words.
INS/INSB/INSW − Used as an input string/byte/word from the I/O port to the provided memory location.
OUTS/OUTSB/OUTSW − Used as an output string/byte/word from the provided memory location to the
I/O port.
SCAS/SCASB/SCASW − scan a string and compare its byte with a byte in AL or string word with a word
in AX.
LODS/LODSB/LODSW − store the string byte into AL or string word into AX.
10/09/2021 2020-21 118
String instructions
 LODS / LODSB / LODSW:
MOVS / MOVSB / MOVSW:
 It causes TRANSFER of byte or word from one
It causes moving of byte or word string to another.
from one string to another.  In this instruction, the source string is in Data
Segment referred by DS:SI transferred to
In this instruction, Accumulator.
 Ex:.
 the source string is in Data MOV SI,STRING1
CLD
Segment referred by DS:SI
LODS
destination string is in Extra
Loads one byte from STRING1 into AL
Segment referred by ES:DI.
• Lodsb
Ex: MOVSB str1,str2  Lodsw
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String instructions
section .data
string1 DB 'HELLO‘
section .bss
String2 resb 5
Section .text
global _start
_start:
mov si,string1
mov di,string2
CLD ; DF = 0
MOVSB ; mov 1st byte
MOVSB ; mov 2nd byte
String instructions
STOS / STOSB / STOSW: CMPS Des, Src:
It causes TRANSFER of byte or It compares the string bytes

word from one string to another. or words.
In this instruction, the string is in
Extra Segment referred by ES:DI SCAS String:
transferred to Accumulator.
Ex: MOV DI,STRING1 It scans a string.
CLD
MOV AL, 05h It compares the String with
STOSB ; byte in AL or with word in
store 05h in memory location pointed by AX
ES:DI
Microprocessor and Interfacing Techniques (CET208A) _T5_S Y BTech_ School of Computer Engineering & Technology_ 2020-21 121
10/09/2021
Compare String
• Example: • Increments (or decrements)
. . section .data
each string pointer and
STRING1 DB ‘ABC‘
STRING2 DB ‘ABD’
successively compares bytes
until there is a mismatch
section .text between the bytes being
global _start
_start:
compared, or until CX = 0.
MOV SI, STRING1 ; source • CMPSB can be used to
MOV DI, STRING2 ; destination
CLD ; DF = 0
determine whether two strings
match, or whether one string is
MOV CX, 3 ; string length a substring of another string.
REPE CMPSB ; repeat while strings match
String instructions
REP
REPZ/ REPE While CX  0 and ZF = 1, repeat execution of
string instruction and
(Repeat CMPS or SCAS (CX)  (CX) – 1
until ZF = 0)
REPNZ/ REPNE
While CX  0 and ZF = 0, repeat execution of
(Repeat CMPS or SCAS string instruction and
until ZF = 1) (CX)  (CX) - 1
10/09/2021 2020-21 123
REP/REPZ/REPNZ
. section .data . section .data
section .bss
section .bss String2 resb 5
String2 resb 5
section .text
section .text global _start
global _start _start:
_start:
MOV SI, STRING1 ; source
MOV SI, STRING1 ; source MOV DI, STRING2 ; destination
MOV DI, STRING2 ; destination CLD ; DF = 0
CLD ; DF = 0
MOV CX, 5
MOVSB ; mov 1st byte
REP MOVSB ; copies 5 chars
MOVSB ; mov 2nd byte
String Instructions
Branch/Program Execution Transfer Instructions
These instructions cause change in the sequence of the execution of instruction.
This change can be a conditional or sometimes unconditional.
The conditions are represented by flags.
CALL Des:
This instruction is used to call a subroutine or function or procedure.
The address of next instruction after CALL is saved onto stack.
RET:
It returns the control from procedure to calling program.
Every CALL instruction should have a RET.
10/09/2021 2020-21 126
JMP Des:
This instruction is used for unconditional jump from one
place to another.
Jxx Des (Conditional Jump):
All the conditional jumps follow some conditional
statements or any instruction that affects the flag.
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Mnemonic Meaning Jump Condition
JA Jump if Above CF = 0 and ZF = 0
JAE Jump if Above or Equal CF = 0
JB Jump if Below CF = 1
JBE Jump if Below or Equal CF = 1 or ZF = 1
JC Jump if Carry CF = 1
JE Jump if Equal ZF = 1
JNC Jump if Not Carry CF = 0
JNE Jump if Not Equal ZF = 0
JNZ Jump if Not Zero ZF = 0
JPE Jump if Parity Even PF = 1
JPO Jump if Parity Odd PF = 0
JZ Jump if Zero ZF = 1
10/09/2021
128
Loop Des:
This is a looping instruction.
The number of times looping is required is placed in the CX register.
With each iteration, the contents of CX are decremented.
ZF is checked whether to loop again or not.
INTO (Interrupt on overflow):
This instruction generates type 4 interrupt (i.e. interrupt for overflow)
It causes the 8086 to do an indirect far call a procedure which is written by the user to
handle the overflow condition.
IRET: To return the execution to the interrupted program
Machine Control Instructions
HLT (Halt) :- It causes the processor to enter in to the halt state. It can be stop by
INTR,NMI or RESET pin
NOP (No Operation) :- It causes the processor to enter in to the wait state for 3 Clock
cycles.
WAIT :- It causes the processor to enter in to the ideal state. Can be stop by TEST,
INTR OR NMI pin
LOCK :- This instruction prevents other processors to take the control of shared
resources. For e.g LOCK IN AL,80H
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Processor Control/Flag Manipulation Instructions
STC: STD:
It sets the carry flag to 1. It sets the direction flag to 1.
CLC: If it is set, string bytes are accessed
It clears the carry flag to 0. from higher memory address to lower
memory address.
CMC:
It complements the carry flag.
CLD:
STI: It clears the direction flag to 0.
It sets the Interrupt flag to 1. If it is reset, the string bytes are
CLI: accessed from lower memory address
to higher memory address.
It clears the Interrupt flag to 0.
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Interrupt Instructions
These instructions are used to call the interrupt during program

execution.
INT − Used to interrupt the program during execution and calling

service specified.
INTO − Used to interrupt the program during execution if OF = 1
IRET − Used to return from interrupt service to the main program
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Comparison of Macro and Procedure
Macro Procedure
•Used for a small number of instructions • Used for a unique task required repeatedly in
used repeatedly in the program the program
•Called by its name • Called using CALL instruction and name
•Memory space required is same • Memory space required is less
•Transfer of control does not take place. • Transfer of control is between main program
and procedure.
•MACRO call is replaced by
instructions by assembler. • call to a procedure is executed during run
time by the processor.
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Pin Diagram: 8086
10/09/2021 2020-21 134
INTEL 8086 - Pin Details
Power Supply
5V  10%
Ground
Reset
Registers, seg
regs, flags
CS: FFFFH, IP:
0000H
If high for
minimum 4
Clock clks
Duty cycle: 33%
10/09/2021 135
Address/Data Bus:
Contains address Address Latch Enable:
bits A15-A0 when ALE
is 1 & data bits D15 – When high,
multiplexed
D0 when ALE is 0.
address/data bus
contains address
information.
10/09/2021 136
INTR
When 1 and IF=1, microprocessor
INTERRUPT prepares to service interrupt. INTA
becomes active after current instruction
completes.
INTA
Interrupt Acknowledge generated by
the microprocessor in response to
INTR. Causes the interrupt vector to be
Non - maskable put onto the data bus.
interrupt NMI
Non-maskable interrupt. Similar to
INTR except IF flag bit is not consulted
.
Interrupt
acknowledge
Interrupt
request
10/09/2021 137
• HOLD Direct
Requests Memory
a direct memory access (DMA).
When 1, microprocessor stops and places
address, data and control bus in high-
Access
impedance state.
• HLDA (Hold Acknowledge)
Indicates that the microprocessor has
Hold entered the hold state.
Hold
acknowledge
10/09/2021 Details
Address/Status Bus
Address bits A19 –
A16 & Status bits S6 –
S3
10/09/2021 Details
139
BHE#, A0: Bus High Enable/S7

0,0: Whole word Enables most
(16-bits) significant data bits
0,1: High byte
D15 – D8 during read
to/from odd address or write operation.
1,0: Low byte S7: Always 1.
to/from even address
1,1: No selection
10/09/2021 140
Min/Max mode
Minimum Mode: +5V
Maximum Mode: 0V
Minimum Mode Pins
Maximum Mode
Pins
10/09/2021 141
WR
Microprocessor is driving data bus
to memory or an I/O device. When
Read Signal 0, data bus contains valid data
M/IO
Indicates if address is a Memory or
IO address
RD
Write Signal When 0, data bus is driven by
memory or an I/O device
DT/R (Data Transmit/Receive)
Data bus is transmitting/receiving
Memory or I/0 data
DEN (Data bus Enable) Activates
Data external data bus buffers.
Transmit/Recei
ve
Data Bus Enable

10/09/2021 142
S2 S1 S0
000: INTA
001: read I/O port
010: write I/O port
011: halt
100: code access Status Signal
101: read memory
110: write memory Inputs to Bus controller
111: none -passive (8288) to generate
eliminated signals due
to max mode.
10/09/2021 143
Maximum Mode - Pin Details
Lock Output
Used to lock peripherals
off the system
DMA Controller
Activated by using the
LOCK: prefix on any (Request/Grant)
instruction
Lock Output
10/09/2021 144
Maximum Mode - Pin Details
QS1 QS0
00: Queue is idle
01: First byte of opcode
10: Queue is empty
11: Subsequent byte of
opcode
Queue Status
Used by numeric
coprocessor (8087)
10/09/2021 145
Use of BHE# / BLE#
Use of BHE# / BLE#

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Microprocessor and Interfacing Techniques

(Course Code: CET208A)

School of Computer Engineering and Technology

Microprocessor and Interfacing Techniques (CET208A) _T5_S Y BTech_ School of Computer

Microprocessor and Interfacing Techniques (CET208A) _T5_S Y BTech_ School of

2. A. Ray, K. Bhurchandi , ”Advanced Microprocessors and peripherals:

3. Introduction to 64 bit Intel Assembly Language Programming for

Microprocessor and Interfacing Techniques (CET208A) _T5_S Y BTech_ School of

Arithmetic computations - ADD, SUBTRACT, MULTIPLY etc.

Microprocessor and Interfacing Techniques (CET208A) _T5_S Y BTech_ School of

Microprocessor and Interfacing Techniques (CET208A) _T5_S Y BTech_ School of

• Thus, processor’s native language is BINARY LANGUAGE

• To define instructions and operands in BINARY is tedious

• To simplify user’s work, processor provides a simpler form of

MOV reg1, data 0001H Mov reg1,data

SUB reg2, reg3 0002H Sub reg2, reg3

Microprocessor and Interfacing Techniques (CET208A) _T5_S Y BTech_ School of

A unique register to hold instruction

A decoder to decode this instruction

A control unit to generate necessary signals to execute the

Microprocessor and Interfacing Techniques (CET208A) _T5_S Y BTech_ School of

Microprocessor and Interfacing Techniques (CET208A) _T5_S Y BTech_ School of

Microprocessor and Interfacing Techniques (CET208A) _T5_S Y BTech_ School of

Microprocessor and Interfacing Techniques (CET208A) _T5_S Y BTech_ School of

•Defines the width/size of the register holding

The ALU – the design of ALU defines different

Intel introduced the 8086 processor in 1979 …

Stephen Morse was the lead development engineer for

Microprocessor and Interfacing Techniques (CET208A) _T5_S Y BTech_ School of

The BIU is free to Prefetch the

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To use the processor, programmer needs to know

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Status and Control SS

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Normally used for storing temporary results

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•All 16 bits wide, L/H bytes are not accessible

Interrupt enable Auxiliary Carry

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Microprocessor and Interfacing Techniques (CET208A) _T5_S Y BTech_ School of

Microprocessor and Interfacing Techniques (CET208A) _T5_S Y BTech_ School of

Microprocessor and Interfacing Techniques (CET208A) _T5_S Y BTech_ School of

Direction flag is used to specify direction (increment

Trap flag is used to interrupt CPU after each operation.

• When a CALL is executed, the 8086

Other registers can also be pushed

Before return from the subroutine, POP

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• When "PUSH BX" is executed, SP is set to 0xF81C and BX is copied to 0x1F81C

POP AX copies the word at 0x1F81E to AX, then sets SP to 0xF820.

Segment Register (16 bits) 0 0 0 0

Physical Address (20 Bits)

Microprocessor and Interfacing Techniques (CET208A)

16-bit Segnment Base Address 0000

16-bit Offset Address

20-bit Physical Address

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