Binary Counters

binary counter
• A counter that follows the binary number sequence is called a
binary counter.
• An n-bit binary counter is a register of n flip-flops and associated
gates that follows a sequence of states according to the binary
count of n bits, from 0 to 2" - 1.
• Going through a sequence of binary numbers such as 0000, 0001,
0010, 001 1, and so on.
• The lower-order bit is complemented after every count and every
other bit is complemented from one count to the next if and only
if all its lower-order bits are equal to 1 .
4-bit synchronous binary counter.
 Binary Counter with Parallel Load

• The increment operation adds one to the content of a register.

• By enabling the count input during one clock period, the content of the register can be
incremented by one .

The operation of the circuit is summarized

• With the clear, load, and increment inputs all at 0, the outputs do not change. If the clear and
load inputs are maintained at logic 0, the increment input controls the operation of the counter
and

• the outputs change to the next binary count for each positive transition of the

• clock.

• The input data are loaded into the flip-flops when the load control input is equal to I provided
that the clear is disabled, but the increment input can be 0 or I.

• The register is cleared to 0 with the clear control regardless of the values in the load and
increment inputs.
 THE BASIC COMPUTER

• The Basic Computer has two components, a processor and memory

• The memory has 4096 words in it
– 4096 = 212, so it takes 12 bits to select a word in memory
• Each word is 16 bits long

CPU RAM
0

15 0

4095
 Instruction codes
• Program
– A sequence of (machine) instructions

• Instruction code

– A group of bits that tell the computer to perform a specific operation (a

sequence of micro-operation)
Operation Code

 The operation code of the instruction is a group of bitst that define such
operations as add ,subtract,multiply,shift and complement.

• The instructions of a program, along with any needed data are stored in memory
• The CPU reads the next instruction from memory
• It is placed in an Instruction Register (IR)
 Instruction codes

INSTRUCTION FORMAT

• A computer instruction is often divided into two parts

– An opcode (Operation Code) that specifies the operation for that instruction
– An address that specifies the registers and/or locations in memory to use for that
operation
• In the Basic Computer, since the memory contains 4096 (= 2 12) words, we needs 12 bit
to specify which memory address this instruction will use
• In the Basic Computer, bit 15 of the instruction specifies the addressing mode (0: direct
addressing, 1: indirect addressing)
• Since the memory words, and hence the instructions, are 16 bits long, that leaves 3
bits for the instruction’s opcode

Instruction Format

15 14 12 11 0
I Opcode Address
Addressing
mode
 Instruction codes

ADDRESSING MODES
• The address field of an instruction can represent either
– Direct address: the address in memory of the data to use (the address of the operand), or
– Indirect address: the address in memory of the address in memory of the data to use

Direct addressing Indirect addressing

22 0 ADD 457 35 1 ADD 300
300 1350
457 Operand
1350 Operand

+ +
AC AC
 Instruction codes

PROCESSOR REGISTERS

• A processor has many registers to hold instructions, addresses, data, etc

• The processor has a register, the Program Counter (PC) that holds the
memory address of the next instruction to get
– Since the memory in the Basic Computer only has 4096 locations, the PC only needs 12
bits
• In a direct or indirect addressing, the processor needs to keep track of
what locations in memory it is addressing: The Address Register (AR) is
used for this
– The AR is a 12 bit register in the Basic Computer
• When an operand is found, using either direct or indirect addressing, it is
placed in the Data Register (DR). The processor then uses this value as
data for its operation
• The Basic Computer has a single general purpose register – the
Accumulator (AC)
 Instruction codes

PROCESSOR REGISTERS

• The significance of a general purpose register is that it can be referred to in

instructions
– e.g. load AC with the contents of a specific memory location; store the contents of AC into
a specified memory location
• Often a processor will need a scratch register to store intermediate results
or other temporary data; in the Basic Computer this is the Temporary
Register (TR)
• The Basic Computer uses a very simple model of input/output (I/O)
operations
– Input devices are considered to send 8 bits of character data to the processor
– The processor can send 8 bits of character data to output devices
• The Input Register (INPR) holds an 8 bit character gotten from an input
device
• The Output Register (OUTR) holds an 8 bit character to be send to an output
device
 Registers

BASIC COMPUTER REGISTERS

Registers in the Basic Computer

11 0
PC
Memory
11 0 4096 x 16
AR

15 0
IR CPU
15 0 15 0
TR DR

7 0 7 0 15 0
OUTR INPR AC

List of BC Registers
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds output character
 Registers

COMMON BUS SYSTEM

• The registers in the Basic Computer are connected using a bus

• This gives a savings in circuitry over complete connections between
registers
 Registers

COMMON BUS SYSTEM

S2
S1 Bus
S0
Memory unit 7
4096 x 16
Address
Write Read
AR 1
LD INR CLR
PC 2
LD INR CLR
DR 3
LD INR CLR
E
ALU AC 4
LD INR CLR
INPR
IR 5
LD
TR 6
LD INR CLR
OUTR
Cloc
LD
16-bit common bus k
 Registers

COMMON BUS SYSTEM

Read INPR
Memory Write
4096 x 16 E ALU
Address

AC

L I C
L I C L
DR IR
L I C L I C
PC TR

AR OUTR LD
L I C
7 1 2 3 4 5 6
16-bit Common Bus
S 0 S1 S 2
 Registers

COMMON BUS SYSTEM

• Three control lines, S2, S1, and S0 control which register the bus
selects as its input
S2 S1 S 0 Register
0 0 0 x
0 0 1 AR
0 1 0 PC
0 1 1 DR
1 0 0 AC
1 0 1 IR
1 1 0 TR
1 1 1 Memory

• Either one of the registers will have its load signal activated, or the
memory will have its read signal activated
– Will determine where the data from the bus gets loaded
• The 12-bit registers, AR and PC, have 0’s loaded onto the bus in the
high order 4 bit positions
• When the 8-bit register OUTR is loaded from the bus, the data
comes from the low order 8 bits on the bus
 Instructions

BASIC COMPUTER INSTRUCTIONS

• Basic Computer Instruction Format

Memory-Reference Instructions (OP-code = 000 ~ 110)

15 14 12 11 0
I Opcode Address

Register-Reference Instructions (OP-code = 111, I = 0)

15 12 11 0
0 1 1 1 Register operation

Input-Output Instructions (OP-code =111, I = 1)

15 12 11 0
1 1 1 1 I/O operation
 Instructions

BASIC COMPUTER INSTRUCTIONS

Hex Code
Symbol I = 0 I=1 Description
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load AC from memory
STA 3xxx Bxxx Store content of AC into memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero

CLA 7800 Clear AC

CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer

INP F800 Input character to AC

OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off
 Instructions

INSTRUCTION SET COMPLETENESS

A computer should have a set of instructions so that the user can
construct machine language programs to evaluate any function that is known
to be computable.
• Instruction Types
Functional Instructions
- Arithmetic, logic, and shift instructions
- ADD, CMA, INC, CIR, CIL, AND, CLA
Transfer Instructions
- Data transfers between the main memory
and the processor registers
- LDA, STA
Control Instructions
- Program sequencing and control
- BUN, BSA, ISZ
Input/Output Instructions
- Input and output
- INP, OUT
 Instruction codes

CONTROL UNIT

• Control unit (CU) of a processor translates from machine instructions

to the control signals for the microoperations that implement them

• Control units are implemented in one of two ways

• Hardwired Control
– CU is made up of sequential and combinational circuits to generate the control
signals
• Microprogrammed Control
– A control memory on the processor contains microprograms that activate the
necessary control signals

• We will consider a hardwired implementation of the control unit for

the Basic Computer
 Timing and control

TIMING AND CONTROL

Control unit of Basic Computer

Instruction register (IR)

15 14 13 12 11 - 0 Other inputs

3x8
decoder
7 6543 210
D0
I Combinational Control
D7
Control signals
T15 logic
T0
15 14 . . . . 2 1 0
4 x 16
decoder

4-bit Increment (INR)

sequence Clear (CLR)
counter
(SC) Clock
 Timing and control

TIMING SIGNALS
- Generated by 4-bit sequence counter and 416 decoder
- The SC can be incremented or cleared.

- Example: T0, T1, T2, T3, T4, T0, T1, . . .

Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.
D3T4: SC  0
T0 T1 T2 T3 T4 T0
Clock

T0

T1

T2

T3

T4

D3

CLR
SC
 INSTRUCTION CYCLE

• In Basic Computer, a machine instruction is executed in the following

cycle:
1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the instruction has an indirect address
4. Execute the instruction

• After an instruction is executed, the cycle starts again at step 1, for the
next instruction

• Note: Every different processor has its own (different)

instruction cycle
 Instruction Cycle

FETCH and DECODE

• Fetch and Decode T0: AR PC (S0S1S2=010, T0=1)

T1: IR  M [AR], PC  PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)

T1 S2
T0 S1 Bus

S0
Memory
unit 7
Address
Read
AR 1
LD
PC 2
INR
IR 5
LD Clock
Common bus
 Instrction Cycle

DETERMINE THE TYPE OF INSTRUCTION

Start
SC  0

AR  PC T0
T1
IR M[AR],PCPC + 1
T2
Decode Opcode in IR(12-14),
ARIR(0-11), IIR(15)

(Register or I/O) = 1 = 0 (Memory-reference)

D7
(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)
I I
T3 T3 T3 T3
Execute Execute ARM[AR] Nothing
input-output register-reference
instruction instruction
SC  0 SC  0 Execute T4
memory-reference
instruction
SC  0

D'7IT3: AR M[AR]
D'7I'T3: Nothing
D7I'T3: Execute a register-reference instr.
D7IT3: Execute an input-output instr.
 Instruction Cycle

REGISTER REFERENCE INSTRUCTIONS

Register Reference Instructions are identified when
- D7 = 1, I = 0
- Register Ref. Instr. is specified in b0 ~ b11 of IR
- Execution starts with timing signal T3
r = D7 IT3 => Register Reference Instruction
Bi = IR(i) , i=0,1,2,...,11
r: SC  0
CLA rB11: AC  0
CLE rB10: E0
CMArB9: AC  AC’
CME rB8: E  E’
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15)
INC rB5: AC  AC + 1
SPA rB4: if (AC(15) = 0) then (PC  PC+1)
SNA rB3: if (AC(15) = 1) then (PC  PC+1)
SZA rB2: if (AC = 0) then (PC  PC+1)
SZE rB1: if (E = 0) then (PC  PC+1)
 MR Instructions

MEMORY REFERENCE INSTRUCTIONS

Symbol Operation Symbolic Description

Decoder
AND D0 AC  AC  M[AR]
ADD D1 AC  AC + M[AR], E  Cout
LDA D2 AC  M[AR]
STA D3 M[AR]  AC
BUN D4 PC  AR
BSA D5 M[AR]  PC, PC  AR + 1
ISZ D6 M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC  PC+1
- The effective address of the instruction is in AR and was placed there during
timing signal T2 when I = 0, or during timing signal T3 when I = 1
- Memory cycle is assumed to be short enough to complete in a CPU cycle
- The execution of MR instruction starts with T4
AND to AC
D0T4:DR  M[AR] Read operand
D0T5:AC  AC  DR, SC  0 AND with AC
ADD to AC
D1T4:DR  M[AR] Read operand
D1T5:AC  AC + DR, E  Cout, SC  0 Add to AC and store carry in E
 MEMORY REFERENCE INSTRUCTIONS
LDA: Load to AC
D2T4:DR  M[AR]
D2T5:AC  DR, SC  0
STA: Store AC
D3T4:M[AR]  AC, SC  0
BUN: Branch Unconditionally
D4T4:PC  AR, SC  0
BSA: Branch and Save Return Address
M[AR]  PC, PC  AR + 1
Memory, PC, AR at time T4 Memory, PC after execution
20 0 BSA 135 20 0 BSA 135
PC = 21Next instruction 21 Next instruction

AR = 135 135 21
136 Subroutine PC = 136 Subroutine

1 BUN 135 1 BUN 135

Memory Memory
 MR Instructions

MEMORY REFERENCE INSTRUCTIONS

BSA:
D5T4:M[AR]  PC, AR  AR + 1
D5T5:PC  AR, SC  0

ISZ: Increment and Skip-if-Zero

D6T4:DR  M[AR]
D6T5:DR  DR + 1
D6T4:M[AR]  DR, if (DR = 0) then (PC  PC + 1), SC  0
 MR Instructions

FLOWCHART FOR MEMORY REFERENCE INSTRUCTIONS

Memory-reference instruction

AND ADD LDA STA

D0 T4 D1 T4 D2 T4 D3T4
DR  M[AR] DR  M[AR] DR  M[AR] M[AR]  AC
SC  0
D0T5 D1T5 D2T5
AC  AC DR AC  AC + DR AC  DR
SC  0 E  Cout SC  0
SC  0
BUN BSA ISZ
D4T4 D5T4 D6T4
PC  AR M[AR]  PC DR  M[AR]
SC  0 AR  AR + 1
D5T5 D6T5
PC  AR DR  DR + 1
SC  0
D6T6
M[AR]  DR
If (DR = 0)
then (PC  PC + 1)
SC  0
 I/O and Interrupt

INPUT-OUTPUT AND INTERRUPT

A Terminal with a keyboard and a Printer
• Input-Output Configuration
Input-output Serial Computer
terminal communication
interface registers and
Printer Receiver flip-flops
OUTR FGO
interface

AC

Keyboard Transmitter INPR FGI

INPR Input register - 8 bits interface
OUTR Output register - 8 bits Serial Communications Path
FGI Input flag - 1 bit Parallel Communications Path
FGO Output flag - 1 bit
IEN Interrupt enable - 1 bit

- The terminal sends and receives serial information

- The serial info. from the keyboard is shifted into INPR
- The serial info. for the printer is stored in the OUTR
- INPR and OUTR communicate with the terminal
serially and with the AC in parallel.
- The flags are needed to synchronize the timing
difference between I/O device and the computer
 I/O and Interrupt

PROGRAM CONTROLLED DATA TRANSFER

-- CPU -- -- I/O Device --
/* Input */ /* Initially FGI = 0 */ loop: If FGI = 1 goto loop
loop: If FGI = 0 goto loop INPR  new data, FGI  1
AC  INPR, FGI  0
loop: If FGO = 1 goto loop
/* Output */ /* Initially FGO = 1 */
consume OUTR, FGO  1
loop: If FGO = 0 goto loop
OUTR  AC, FGO  0
FGI=0 FGO=1
Start Input Start Output

FGI  0
AC  Data
yes yes
FGI=0
FGO=0
no
no
AC  INPR
OUTR  AC

yes More FGO  0

Character
yes More
no Character
END no
END
 INPUT-OUTPUT INSTRUCTIONS

D7IT3 = p
IR(i) = Bi, i = 6, …, 11

p: SC  0 Clear SC
INP pB11:AC(0-7)  INPR, FGI  0 Input char. to AC
OUT pB10:OUTR  AC(0-7), FGO  0 Output char. from AC
SKI pB9: if(FGI = 1) then (PC  PC + 1) Skip on input flag
SKO pB8: if(FGO = 1) then (PC  PC + 1) Skip on output flag
ION pB7: IEN  1 Interrupt enable on
IOF pB6: IEN  0 Interrupt enable off
 I/O and Interrupt

PROGRAM-CONTROLLED INPUT/OUTPUT
• Program-controlled I/O
- Continuous CPU involvement
I/O takes valuable CPU time
- CPU slowed down to I/O speed
- Simple
- Least hardware

Input

LOOP, SKI DEV

BUN LOOP
INP DEV

Output
LOOP, LDA DATA
LOP, SKO DEV
BUN LOP
OUT DEV
 INTERRUPT INITIATED INPUT/OUTPUT
- Open communication only when some data has to be passed --> interrupt.

- The I/O interface, instead of the CPU, monitors the I/O device.

- When the interface founds that the I/O device is ready for data transfer,
it generates an interrupt request to the CPU

- Upon detecting an interrupt, the CPU stops momentarily the task

it is doing, branches to the service routine to process the data
transfer, and then returns to the task it was performing.

* IEN (Interrupt-enable flip-flop)

- can be set and cleared by instructions

- when cleared, the computer cannot be interrupted
 I/O and Interrupt

FLOWCHART FOR INTERRUPT CYCLE

R = Interrupt f/f
Instruction cycle =0 =1 Interrupt cycle
R

Fetch and decode Store return address

instructions in location 0
M[0]  PC
Execute =0
IEN
instructions
=1 Branch to location 1
=1
FGI
PC 1
=0
=1
FGO IEN0
=0 R0
R 1

- The interrupt cycle is a HW implementation of a branch

and save return address operation.
- At the beginning of the next instruction cycle, the
instruction that is read from memory is in address 1.
- At memory address 1, the programmer must store a branch instruction
that sends the control to an interrupt service routine
- The instruction that returns the control to the original
program is "indirect BUN 0"
 I/O and Interrupt

REGISTER TRANSFER OPERATIONS IN INTERRUPT CYCLE

Memory
Before interrupt After interrupt cycle
0 0 256
1 0 BUN 1120 PC = 1 0 BUN 1120
Main Main
255 Program 255 Program
PC = 256 256
1120 1120
I/O I/O
Program Program
1 BUN 0 1 BUN 0
Register Transfer Statements for Interrupt Cycle
- R F/F  1 if IEN (FGI + FGO)T0T1T2
 T0T1T2 (IEN)(FGI + FGO): R  1

- The fetch and decode phases of the instruction cycle

must be modified Replace T0, T1, T2 with R'T0, R'T1, R'T2
- The interrupt cycle :
RT0: AR  0, TR  PC
RT1: M[AR]  TR, PC  0
RT2: PC  PC + 1, IEN  0, R  0, SC  0
 I/O and Interrupt

FURTHER QUESTIONS ON INTERRUPT

How can the CPU recognize the device

requesting an interrupt ?

Since different devices are likely to require

different interrupt service routines, how can
the CPU obtain the starting address of the
appropriate routine in each case ?

Should any device be allowed to interrupt the

CPU while another interrupt is being serviced ?

How can the situation be handled when two or

more interrupt requests occur simultaneously ?
 Description
COMPLETE COMPUTER DESCRIPTION
Flowchart of Operations
start
SC  0, IEN  0, R  0
=0(Instruction =1(Interrupt
R
Cycle) Cycle)
R’T0 RT0
AR  PC R’T AR  0, TR  PC RT1
1

IR  M[AR], PC  PC + 1 M[AR]  TR, PC  0

R’T2 RT2
AR  IR(0~11), I  IR(15) PC  PC + 1, IEN  0
D0...D7  Decode IR(12 ~ 14) R  0, SC  0

=1(Register or I/O) D7 =0(Memory Ref)

=1 (I/O) =0 (Register) =1(Indir) =0(Dir)

I I

D7IT3 D7I’T3 D7’IT3 D7’I’T3

Execute Execute AR <- M[AR] Idle
I/O RR
Instruction Instruction
Execute MR D7’T4
Instruction
 Description

COMPLETE COMPUTER DESCRIPTION Microoperations

Fetch RT0: AR  PC
RT1: IR  M[AR], PC  PC + 1
Decode RT2:
D0, ..., D7  Decode IR(12 ~ 14),
Indirect D7IT3: AR  IR(0 ~ 11), I  IR(15)
Interrupt
T T T (IEN)(FGI + FGO): AR  M[AR]
0 1 2

RT0: R1
RT1: AR  0, TR  PC
Memory-Reference RT2: M[AR]  TR, PC  0
AND
PC  PC + 1, IEN  0, R  0, SC  0
D0T4:
ADD D0T5:
D1T4: DR  M[AR]
LDA D1T5: AC  AC  DR, SC  0
D2T4: DR  M[AR]
STA
BUN D2T5: AC  AC + DR, E  Cout, SC  0
BSA D3T4: DR  M[AR]
D4T4:
AC  DR, SC  0
ISZ D5T4:
M[AR]  AC, SC  0
D5T5:
D6T4: PC  AR, SC  0
D6T5: M[AR]  PC, AR  AR + 1
D6T6: PC  AR, SC  0
 Description

COMPLETE COMPUTER DESCRIPTION Microoperations

Register-Reference
D7IT3 = r (Common to all register-reference instr)
IR(i) = Bi (i = 0,1,2, ..., 11)
r: SC  0
CLA rB11: AC  0
CLE rB10:
CMA E0
rB9:
CME AC  AC
CIR rB8:
E  E
CIL rB7:
INC rB6: AC  shr AC, AC(15)  E, E  AC(0)
SPA rB5: AC  shl AC, AC(0)  E, E  AC(15)
SNA rB4: AC  AC + 1
SZA rB3: If(AC(15) =0) then (PC  PC + 1)
SZE
rB2: If(AC(15) =1) then (PC  PC + 1)
HLT
rB1:
If(AC = 0) then (PC  PC + 1)
Input-Output rB0:
If(E=0) then (PC  PC + 1)
D7IT3 = p S0
INP IR(i) = Bi
OUT (Common to all input-output instructions)
p:
SKI (i = 6,7,8,9,10,11)
pB11:
SKO pB10: SC  0
ION AC(0-7)  INPR, FGI  0
pB9:
IOF
pB8: OUTR  AC(0-7), FGO  0
 Design of Basic Computer

DESIGN OF BASIC COMPUTER(BC)

Hardware Components of BC
A memory unit: 4096 x 16.
Registers:
AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC
Flip-Flops(Status):
I, S, E, R, IEN, FGI, and FGO
Decoders: a 3x8 Opcode decoder
a 4x16 timing decoder
Common bus: 16 bits
Control logic gates:
Adder and Logic circuit: Connected to AC
Control Logic Gates
- Input Controls of the nine registers
- Read and Write Controls of memory
- Set, Clear, or Complement Controls of the flip-flops
- S2, S1, S0 Controls to select a register for the bus
- AC, and Adder and Logic circuit
 Design of Basic Computer

CONTROL OF REGISTERS AND MEMORY

Address Register; AR
Scan all of the register transfer statements that change the content of AR:
R’T0: AR  PC LD(AR)
R’T2: AR  IR(0-11) LD(AR)
D’7IT3: AR  M[AR] LD(AR)
RT0: AR  0 CLR(AR)
D5T4: AR  AR + 1 INR(AR)
LD(AR) = R'T0 + R'T2 + D'7IT3
CLR(AR) = RT0
INR(AR) = D5T4

From bus 12 AR
12
To bus
D'7
I Clock
T3 LD
T2 INR
CLR
R
T0
D
T4
 Design of Basic Computer

CONTROL OF FLAGS
IEN: Interrupt Enable Flag
pB7: IEN  1 (I/O Instruction)
pB6: IEN  0 (I/O Instruction)
RT2: IEN  0 (Interrupt)

p = D7IT3 (Input/Output Instruction)

D7
I p
B7 J Q IEN
T3

B6
K
R
T2
 Design of Basic Computer

CONTROL OF COMMON BUS

x1
x2 S2
x3 Multiplexer
x4 Encoder S 1 bus select
x5 inputs
x6 S0
x7

x1 x2 x3 x4 x5 x6 x7 selected
S2 S1 S0
0 0 0 0 0 0 0 0 0 0 register
none
1 0 0 0 0 0 0 0 0 1 AR
0 1 0 0 0 0 0 0 1 0 PC
0 0 1 0 0 0 0 0 1 1 DR
0 0 0 1 0 0 0 1 0 0 AC
0 0 0 0 1 0 0 1 0 1 IR
0 0 0 0 0 1 0 1 1 0 TR
0 AR
For 0 0 0 0 0 1 1 1 1 Memory
D4T4: PC  AR
D5T5: PC  AR

x1 = D4T4 + D5T5
 Design of AC Logic

DESIGN OF ACCUMULATOR LOGIC

Circuits associated with AC
16
16 Adder and 16 16
From DR logic AC
circuit To bus
From INPR 8
LD INR CLR Clock

Control
gates

All the statements that change the content of AC

D0T5: AC  AC  DR AND with DR
D1T5: AC  AC + DR Add with DR
D2T5: AC  DR Transfer from DR
pB11: AC(0-7)  INPR Transfer from INPR
rB9: AC  AC Complement
rB7 : AC  shr AC, AC(15)  E Shift right
rB6 : AC  shl AC, AC(0)  E Shift left
rB11 : AC  0 Clear
rB5 : AC  AC + 1 Increment
 Design of AC Logic

CONTROL OF AC REGISTER

Gate structures for controlling

the LD, INR, and CLR of AC

From Adder 16 16 To bus

and Logic AC
D0 AND LD Clock
T5 INR
D1 ADD CLR
D2 DR
T5
p INPR
B 11
r COM
B9
SHR
B7
SHL
B6
INC
B5
CLR
B 11
 Design of AC Logic

ALU (ADDER AND LOGIC CIRCUIT)

One stage of Adder and Logic circuit

DR(i) AC(i)
AND

C i ADD LD
FA Ii J Q
AC(i)
C i+1 DR
K
From INPR
INPR
bit(i) COM

SHR
AC(i+1)
SHL
AC(i-1)