Address Decoding Technique

Address Decoding Techniques
1. Absolute decoding
2. Linear decoding
3. Block decoding
1.Absolute Decoding:
 In the absolute decoding technique the memory chip is selected only
for the specified logic level on the address lines: no other logic levels
can select the chip.
 Below figure the memory interface with absolute decoding. Two 32K
EPROMs are used to provide even and odd memory banks.
 Control signals BHE and A0 are use to enable output of odd and even
memory banks respectively. As each memory chip has 32 K memory
locations, sixteen address lines are required to address each locations,
independently .
.
Linear Decoding:
In small system hardware for the decoding logic can be eliminated by using
only required number of addressing lines (not all). Other lines are simple
ignored. This technique is referred as linear decoding or partial decoding.
Control signals BHE and Ao are used to enable odd and even memory banks,
respectively. Figure shows the addressing of 16K RAM (6264) with linear
decoding.
MICROPROCESSORS AND MICROCONTROLLERS Page 2

The address line A19 is used to select the RAM chips. When A19
is low, chip is selected, otherwise it is disabled. The status of A14
to A18 does not affect the chip selection logic. This gives you
multiple addresses (shadow addresses). This technique reduces
the cost of decoding circuit, but it gas drawback of multiple
addresses.
Block Decoding:
In a microcomputer system the memory array is often consists of
several blocks of memory chips. Each block of memory requires
decoding circuit. To avoid separate decoding for each memory
block special decoder IC is used to generate chip select signal for
each block.
Figure shows the Block decoding technique using 74138, 3:8 decoder

UNIT-2 8086 ASSEMBLY LANGUAGE PROGRAMMING ECE DEPARTMENT
Memory Map Table
Addre A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0
ss 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
FFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
H
EPROM 8K X 8
FE000 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
H
FDFFF 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
H
RAM 8K X 8
FC000 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
H
Total 8K bytes of EPROM need 13 address lines A0-A12 (since z13 = 8K).
Address lines A13 - A19 are used for decoding to generate the chip select.
The 𝐵𝐻𝐸 signal goes low when a transfer is at odd address or higher byte
of data is to be accessed.
Let us assume that the latched address, 𝐵𝐻𝐸 and demultiplexed data lines are readily available for interfacing.
The memory system in this problem contains in total four 4K x 8 memory chips.
The two 4K x 8 chips of RAM and ROM are arranged in parallel to obtain 16-bit data bus width. If A0 is 0, i.e., the
address is even and is in RAM, then the lower RAM chip is selected indicating 8-bit transfer at an even address. If A0 is
i.e., the address is odd and is in RAM, the 𝐵𝐻𝐸 goes low, the upper RAM chip is selected, further indicating that the 8-
bit transfer is at an odd address. If the selected addresses are in ROM, the respective ROM chips are selected. If at a
time A0 and 𝐵𝐻𝐸 both are 0, both the RAM or ROM chips are selected, i.e., the data transfer is of 16 bits. The selection
of chips here takes place as shown in table below.

Memory Chip Selection Table:
Decoder I/P --> A2 A1 A0 Selection/
Address/𝐵𝐻𝐸 --> A13 A0 𝐵𝐻𝐸 Comment
Word transfer on D0 - D15 0 0 0 Even and odd address in RAM
Byte transfer on D7 - D0 0 0 1 Only even address in RAM
Byte transfer on D8 - D15 0 1 0 Only odd address in RAM
Word transfer on D0 - D15 1 0 0 Even and odd address in RAM
Byte transfer on D7 - D0 1 0 1 Only even address in RAM
Byte transfer on D8 - D15 1 1 0 Only odd address in ROM
Problem2: Design an interface between 8086 CPU and two chips of 16K×8 EPROM and two chips of 32K×8 RAM.
Select the starting address of EPROM suitably. The RAM address must start at 00000 H.
Solution: The last address in the map of 8086 is FFFFF H. after resetting, the processor starts from FFFF0 H. hence this
address must lie in the address range of EPROM.

It is better not to use a decoder to implement the above map because it is not continuous, i.e. there is some unused
address space between the last RAM address (0FFFF H) and the first EPROM address (F8000 H). Hence the logic is
implemented using logic gates.
Problem3: It is required to interface two chips of 32K×8 ROM and four chips of 32K×8 RAM with 8086, according to
following map.
ROM 1 and ROM 2 F0000H - FFFFFH, RAM 1 and RAM 2 D0000H - DFFFFH, RAM 3 and RAM 4 E0000H - EFFFFH.
Show
the implementation of this memory system.
Solution:

Methods of Interfacing I/O Devices
Memory Mapping IO mapping

1. 20-bit addresses are provided for IO 1. 8-bit or 16-bit address are provided for IO
devices. devices
2. The IO ports or peripherals can be treated 2. Only IN and OUT instructions can be used for
like memory locations and so all data transfer between IO device and the
instructions related to memory can be processor.
used for data transfer.
3. In memory mapped ports, the data can be 3. In IO mapped ports, the data transfer can
moved from any register to port and vice take only between the accumulator and the
versa ports
4. When memory mapping is used for IO 4. When IO mapping is used for IO devices,
devices, the full memory address space then the full address space can be used for
cannot be used for addressing memory. addressing memory.

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Address Decoding Techniques

MICROPROCESSORS AND MICROCONTROLLERS Page 2

MICROPROCESSORS AND MICROCONTROLLERS Page 4

Memory Map Table

MICROPROCESSORS AND MICROCONTROLLERS Page 5

Memory Chip Selection Table:

Decoder I/P --> A2 A1 A0 Selection/

Address/𝐵𝐻𝐸 --> A13 A0 𝐵𝐻𝐸 Comment

Word transfer on D0 - D15 0 0 0 Even and odd address in RAM

Byte transfer on D7 - D0 0 0 1 Only even address in RAM

Byte transfer on D8 - D15 0 1 0 Only odd address in RAM

Word transfer on D0 - D15 1 0 0 Even and odd address in RAM

Byte transfer on D7 - D0 1 0 1 Only even address in RAM

Byte transfer on D8 - D15 1 1 0 Only odd address in ROM

MICROPROCESSORS AND MICROCONTROLLERS Page 6

MICROPROCESSORS AND MICROCONTROLLERS Page 7

Methods of Interfacing I/O Devices

Memory Mapping IO mapping

MICROPROCESSORS AND MICROCONTROLLERS Page 8

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