Power and Energy Basics

Progettazione Low Power A.A. 2020-2021

 Outline

 Metrics
 Dynamic power
 Static power
 Energy-delay trade-off’s

Progettazione Low Power A.A. 2020-2021 3

 Where is Power Dissipated in CMOS?

 Active (Dynamic) power

– (Dis)charging capacitors
– Short-circuit power
 Both pull-up and pull-down on during transition
 Static (leakage) power
– Transistors are imperfect switches
 Static currents
– Biasing currents

Progettazione Low Power A.A. 2020-2021 3

 Active (or Dynamic) Power

Key property of active power:

Pdyn  f
with f the switching frequency

Sources:
 Charging and discharging capacitors
 Temporary glitches (dynamic hazards)
 Short-circuit currents

Progettazione Low Power A.A. 2020-2021 3

 Charging Capacitors
Applying a voltage step
1
E R  CV 2
2
E01  CV 2 R
1
EC  CV 2
2
V C

Value of R does not impact energy!

Progettazione Low Power A.A. 2020-2021 3
 Applied to Complementary CMOS Gate

Vdd 2
E 01  CLVDD

1 2
PMOS iL ER  CLVDD
2
A1 NETWORK
Vout
AN 1 2
CL EC  CLVDD
NMOS 2
NETWORK

 One half of the power from the supply is consumed in the

pull-up network and one half is stored on CL
 Charge from CL is dumped during the 10 transition
 Independent of resistance of charging/discharging network

Progettazione Low Power A.A. 2020-2021 3

 Circuits with Reduced Swing

0→V

0→V - VTH
More in general…
V C
C
V2 V1
-


dV
E01   VC C dt  CV
V VT
V2
0
dt  dVC  CV (V  VTH )
0

E = C*V2*(V2-V1)
Energy consumed is
proportional to output swing (V2>V1)
Progettazione Low Power A.A. 2020-2021 3
 Dynamic Power Consumption

Power = Energy/transition • Transition rate

= CLVDD2•f01

= CLVDD2•f• P01

= CswitchedVDD2•f

 Power dissipation is data dependent – depends

on the switching probability
 Switched capacitance Cswitched= P01CL= aCL
(a is called the switching activity)
Progettazione Low Power A.A. 2020-2021 3
 Impact of Logic Function

Example: Static 2-input NOR gate

Assume signal probabilities

A B Out pA=1 = 1/2
0 0 1 pB=1 = 1/2
0 1 0
Then transition probability
1 0 0 p01 = pOut=0 x pOut=1
1 1 0
= 3/4 x 1/4 = 3/16
If inputs switch every cycle
aNOR= 3/16

NAND gate yields similar result

Progettazione Low Power A.A. 2020-2021 3
 Impact of Logic Function

Example: Static 2-input XOR Gate

Assume signal probabilities

A B Out pA=1 = 1/2
0 0 0 pB=1 = 1/2
0 1 1
Then transition probability
1 0 1 p01 = pOut=0 x pOut=1
1 1 0
= 1/2 x 1/2 = 1/4
If inputs switch in every cycle
P01 = 1/4

Progettazione Low Power A.A. 2020-2021 3.

 Transition Probabilities for Basic Gates

As a function of the input probabilities

p01
AND (1 - pApB)pApB
OR (1 - pA)(1 - pB)(1 - (1 - pA)(1 - pB))
XOR (1 - (pA +pB – 2pApB))(pA + pB – 2pApB)

Activity for static CMOS gates

a = p0p1

Progettazione Low Power A.A. 2020-2021 3

 Activity as a Function of Topology
XOR versus NAND/NOR

XOR

NAND/NOR

aNOR,NAND = (2N-1)/22N aXOR = 1/4

Progettazione Low Power A.A. 2020-2021 3.

 Exercise 1

Progettazione Low Power A.A. 2020-2021 3.

 Exercise 1

Progettazione Low Power A.A. 2020-2021 3.

 Exercise 1

Progettazione Low Power A.A. 2020-2021 3.

 Exercise 2

Progettazione Low Power A.A. 2020-2021 3.

 Excercise 3

Progettazione Low Power A.A. 2020-2021 3.

 Algebraic Transformations
Idea: Modify network to reduce capacitance
F= a·b + a·c = a·(b+c)
p1=0.051
a p3=0.076 a
b f
f
a b
c c
p4=0.375

pa = 0.1; pb = 0.5; pc = 0.5

Progettazione Low Power A.A. 2020-2021 3.

 Algebraic Transformations
Idea: Modify network to reduce capacitance
F= a·b + a·c = a·(b+c)
p1=0.051
If you calculate af with
a a this procedure, you’ll
b f get two different
f
a b values…
p0=0.95 c p0=0.25 How is it possible???
c
p1=0.05 p1=0.75
p0-1=0.0475 p0-1=0.1875
pa = 0.1; pb = 0.5; pc = 0.5

Caveat: This may increase activity!

Progettazione Low Power A.A. 2020-2021 3.

 Reconvergent Fanout (Spatial Correlation)

Inputs to gate can be interdependent (correlated)

A X
Z A X
reconvergence
Z

no reconvergence reconvergent
PZ = 1-(1-PA)PB PZ = 1-(1-PA)PA ?
NO!
PZ: probability that Z=1 PZ = 1
Must use conditional probabilities
PZ = 1- PA . P(X|A) = 1
probability that X=1 given that A=1
Becomes complex and intractable real fast

Progettazione Low Power A.A. 2020-2021 3.

 Glitching in Static CMOS
Analysis so far did not include timing effects
A
X
B Z
C

ABC 101 000

Z
Glitch

Gate Delay

Also known as dynamic hazards:

The result is correct, “A single input change causing
but extra power is dissipated multiple changes in the output”

Progettazione Low Power A.A. 2020-2021 3.

 What Causes Glitches?
A
A
X B
B X
Z
Y Y
C
C
Z
D D

A,B A,B

C,D C,D

X X

Y Y

Z Z

Uneven arrival times of input signals of gate due to

unbalanced delay paths
Solution: balancing delay paths!
Progettazione Low Power A.A. 2020-2021 3.
 Short-Circuit Currents

(also called crowbar currents)

VDD
VDD -VT

vin
VT
Vin I sc Vout
I peak t
CL ishort

PMOS and NMOS simultaneously on during transition

Progettazione Low Power A.A. 2020-2021 3.

 Transistors Leak

 Drain leakage
– Diffusion currents
– Drain-induced barrier lowering (DIBL)
 Junction leakages
– Gate-induced drain leakage (GIDL)
 Gate leakage
– Tunneling currents through thin oxide

Progettazione Low Power A.A. 2020-2021 3.

 Sub-Threshold Leakage

Leakage current increases with drain voltage

(mostly due to DIBL)
VTH  d VDS
W S
I leak  I0 10 (for VDS> 3 kT/q)
W0
Hence
VTH d VDD
W
Pleak  (I 0 10 S )(VDD 10 S )
W0

Leakage Power strong function of supply voltage

Progettazione Low Power A.A. 2020-2021 3.

 Stack Effect

Assume that body effect in short

channel transistor is small
NAND gate: VM VTH  d (VDD VM )
I leak, M 1  I 0 10 S
VDD
Neglecting
VTH  d VM the Body

I leak, M 2  I 0 10 S
Biasing…

d
VM  VDD
1 2d
d VDD 1 d
I stack 
S
( )
1 2 d (instead of the
 10 expected factor of 2)
I inv

Progettazione Low Power A.A. 2020-2021 3.

 Summary of Power Dissipation Sources

P ~   C L  CCS Vswing VDD  f  I DC  I Leak VDD

 a– switching activity
 CL – load capacitance  IDC – static current
 CCS – short-circuit  Ileak – leakage current
capacitance
 Vswing – voltage swing
 f – frequency

energy
P  rate  static power
operation
Progettazione Low Power A.A. 2020-2021 3.
 The Traditional Design Philosophy

 Maximum performance is primary goal

– Minimum delay at circuit level
 Architecture implements the required function
with target throughput, latency
 Performance achieved through optimum sizing,
logic mapping, architectural transformations.
 Supplies, thresholds set to achieve maximum
performance, subject to reliability constraints

Progettazione Low Power A.A. 2020-2021 3.

 The New Design Philosophy

 Maximum performance (in terms of

propagation delay) is too power-hungry,
and/or not even practically achievable
 Many (if not most) applications either can
tolerate larger latency, or can live with lower
than maximum clock-speeds
 Excess performance (as offered by
technology) to be used for energy/power
reduction
Trading off speed for power
Progettazione Low Power A.A. 2020-2021 3.
 Exploring the Energy-Delay Space
Energy Unoptimized
design

Emax Pareto-optimal
designs

Emin
Dmin Dmax Delay

In energy-constrained world, design is trade-off process

♦ Minimize energy for a given performance requirement
♦ Maximize performance for given energy budget

Progettazione Low Power A.A. 2020-2021 [Ref: D. Markovic, JSSC’04] 3.

 Summary

 Power and energy are now primary design

constraints
 Active power still dominating for most
applications
– Supply voltage, activity and capacitance the key
parameters
 Leakage becomes major factor in sub-100nm
technology nodes
– Mostly impacted by supply and threshold voltages
 Design has become energy-delay trade-off
exercise!

Progettazione Low Power A.A. 2020-2021 3.