Module 6 Dldca

Data Representation and
Arithmetic Algorithms
Module 6
Arithmetic & Logic Unit
 Does the calculations
 Everything else in the computer is there to service this
unit
 Handles integers
 May handle floating point (real) numbers
 May be separate FPU (maths co-processor)
 May be on chip separate FPU
ALU Inputs and Outputs
Integer Representation
 Only have 0 & 1 to represent everything
 Positive numbers stored in binary
 e.g. 41=00101001
 No minus sign
 No period
 Sign-Magnitude
 Two’s complement
Sign-Magnitude
 Left most bit is sign bit
 0 means positive
 1 means negative
 +18 = 00010010
 -18 = 10010010
 Problems
 Need to consider both sign and magnitude in arithmetic
 Two representations of zero (+0 and -0)
Two’s Complement
 +3 = 00000011
 +2 = 00000010
 +1 = 00000001
 +0 = 00000000
 -1 = 11111111
 -2 = 11111110
 -3 = 11111101
Benefits
 One representation of zero
 Arithmetic works easily
 Negating is fairly easy
 3 = 00000011
 Boolean complement gives 11111100
 Add 1 to LSB 11111101
Negation Special Case 1
 0= 00000000
 Bitwise not 11111111
 Add 1 to LSB +1
 Result 1 00000000
 Overflow is ignored, so:
 -0=0
Negation Special Case 2
 -128 = 10000000
 bitwise not 01111111
 Add 1 to LSB +1
 Result 10000000
 So:
 -(-128) = -128 X
 Monitor MSB (sign bit)
 It should change during negation
Range of Numbers
 8 bit 2s complement
 +127 = 01111111 = 27 -1
 -128 = 10000000 = -27
 16 bit 2s complement
 +32767 = 011111111 11111111 = 215 - 1
 -32768 = 100000000 00000000 = -215
Addition and Subtraction
 Normal binary addition
 Monitor sign bit for overflow
 Take twos complement of subtrahend and add to minuend

 i.e. a - b = a + (-b)
 So we only need addition and complement circuits

Hardware for Addition and Subtraction
Multiplication
 Complex
 Work out partial product for each digit
 Take care with place value (column)
 Add partial products
Multiplication Example
 1011 Multiplicand (11 dec)
 x 1101 Multiplier (13 dec)
 1011 Partial products
 0000 Note: if multiplier bit is 1 copy
 1011 multiplicand (place value)
 1011 otherwise zero
 10001111 Product (143 dec)
 Note: need double length result
Unsigned Binary Multiplication (Hardware
implementation)
Flowchart for Unsigned Binary Multiplication
Execution of Example
Multiplying Negative Numbers
 This does not work!
 Solution 1
 Convert to positive if required
 Multiply as above
 If signs were different, negate answer
 Solution 2
 Booth’s algorithm
Booth’s Algorithm
Signed Multiplication (Hardware
Implementation)
Example of Booth’s Algorithm
Division
 More complex than multiplication
 Negative numbers are really bad!
 Based on long division
Division of Unsigned Binary Integers
00001101 Quotient
Divisor 1011 10010011 Dividend

1011
001110
Partial
1011
Remainders
001111
1011
Remainder
100
Hardware Implementation of Division
Flowchart for Unsigned Binary Division
(Restoring algorithm)
Example- Restoring algorithm
Divide 7 by 3
Non-restoring algorithm
Example-Non-restoring algorithm
Divide 10 by 3
Floating Point
 +/- .significand x 2exponent

 Misnomer
 Point is actually fixed between sign bit and body of mantissa
 Exponent indicates place value (point position)
Floating Point Examples
Signs for Floating Point
 Mantissa is stored in 2s compliment
 Exponent is in excess or biased notation
 e.g. Excess (bias) 128 means
 8 bit exponent field
 Pure value range 0-255
 Subtract 128 to get correct value
 Range -128 to +127
Normalization
 FP numbers are usually normalized
 i.e. exponent is adjusted so that leading bit (MSB) of
mantissa is 1
 Since it is always 1 there is no need to store it
 (c.f. Scientific notation where numbers are normalized to
give a single digit before the decimal point
 e.g. 3.123 x 103)
FP Ranges
 For a 32 bit number
 8 bit exponent
 +/- 2256  1.5 x 1077
 Accuracy
 The effect of changing lsb of mantissa
 23 bit mantissa 2-23  1.2 x 10-7
 About 6 decimal places
Expressible Numbers
Density of Floating Point Numbers
IEEE 754
 Standard for floating point storage
 32 and 64 bit standards
 8 and 11 bit exponent respectively
 Extended formats (both mantissa and exponent) for
intermediate results
IEEE 754 Formats
Special Values in IEEE 754 standard
Note: Similar for Double precision (just replacing 255 by 2049)

FP Arithmetic +/-
 Check for zeros
 Align significands (adjusting exponents)
 Add or subtract significands
 Normalize result
FP Addition & Subtraction Flowchart
FP Arithmetic x/
 Check for zero
 Add/subtract exponents
 Multiply/divide significands (watch sign)
 Normalize
 Round
 All intermediate results should be in double length storage
Floating Point Multiplication
Floating Point Division

Module 6 Dldca

Uploaded by

Copyright:

Available Formats

Module 6 Dldca

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Module 6 Dldca

Uploaded by

Copyright:

Available Formats

Data Representation and

 Take twos complement of subtrahend and add to minuend

 So we only need addition and complement circuits

Divisor 1011 10010011 Dividend

 +/- .significand x 2exponent

Note: Similar for Double precision (just replacing 255 by 2049)

You might also like