Introduction to Computer

Architecture and Organization

| MODULE 01
Reference

• Chapter 1.1, 1.2, 1.3

• Chapter 3.1, 3.2, 3.3
Overview

• Computer Architecture
• Logical Layout
• Attributes of a system visible to a programmer (or)
• Attributes that have a direct impact on the logical execution of
a program
• Instruction Set Architecture (ISA)
• Defines instruction formats, opcodes, data, memory,…
Overview

• Computer Organization
• Operational units and their interconnections
• Organization is done based on architecture
• Physical Components
Structure & Functional Components

Function – The
Structure – How the
operation of each
components are
component as part of
interrelated.
the structure.
 Functional
Components

• Four major types

• Data Processing

• Data Storage
• Volatile / Permanent

• Data Movement (I/O)

• Peripherals, Data
Communication

• Control Unit
How does a program get
executed?
How does a program get executed?
Levels of Programming Languages
Structural Design – Single Core

• CPU – Processor
• Main Memory – Stores the data
• I/O – Data movement
• System Bus – Provides communication
between CPU, Memory, I/O

• We have had more processors in

recent times
Structural Design

• Registers – processor’s own

memory
• ALU – Arithmetic and Logic Unit –
performs data processing
• Internal bus – data movement
b/w Registers, ALU, CU
Structural Design

• Control Unit – controls the

operation of the CPU and
computer
Structural Design – Multi Core

• Multiple processors residing on a single chip

• Each processor is know as a CORE (equal to a CPU)
• Optimized vector and matrix operations
Structural Design – Multi Core
Structural Design – Multi Core

• Instruction Logic – Fetch,

Decode, and finding the
location of the data
• ALU – performs specified
operation
• Load / Store – manages data
transfer to and from main
Structural Design – Multi Core

• Cache Memory – part of main memory

• Smaller, faster, expensive
• L1 < L2 < L3 (size & distance)
• L1 is smaller in size, closer to the cores
Memory

• Physical device to store programs and data

• Two types of memory

• Main Memory

• Volatile –loses information when power is turned off

• Secondary Memory

• Non-volatile
Main Memory
• Closely connected to the processor

• Stored data are quickly and easily changed

• Holds the programs and data that the processor is actively

working with

• Interacts with the processor millions of time per second

• Needs constant electric power to keep its information

• Fast, expensive, low capacity

• Works directly with the processor

Secondary Memory
• Connected to main memory through the bus and a controller

• Stored data are easily changed, but changes are slow compared to main
memory

• Used for long-term storage of programs and data

• Before data and programs can be used, they must be copied

from secondary memory to main memory

• Does not need electric power to keep its information

• Slow, cheap, large capacity

Access Time

Storage
Memory Unit – Classification
Memory

Secondary
Primary Memory
Memory
Hard disk
drive
Solid state
RAM ROM drive
Flash drive
PROM CD, DVD
Static
EPROM Magnetic
RAM
Dynamic EEPROM tapes
RAM Flash
memory
21
RAM vs ROM
SRAM vs DRAM
 Levels of Memory Hierarchy
Capacity
Access Time Upper Level
Cost
CPU Registers faster
100s Bytes
1s ns Registers
Cache Instr. Operands
K Bytes
4 ns Cache
1-0.1 cents/bit
Main Memory Blocks
M Bytes
100ns- 300ns Memory
$.0001-.00001 cents /bit
Pages
Disk
Files
Larger
Tape Lower Level
Registers and
Register files
Registers

• Register is a high-speed computer memory that stores

data/instruction in execution.
• A Register consists of flip-flops and gates that affect their
transition.
• Constructed with four D-type flip-flops and a common clock pulse
output.
• Set of registers stored in a sequential memory space – Register
files
Registers

• Registers have 3 specific roles:

1. User-visible registers

2. Condition code registers

3. Control and status registers

Instructions, Operands,
Opcodes and Addressing
• Instructions are operations performed by the CPU.
• Operands are entities operated upon by the instruction.
• An opcode is short for 'Operation Code'.
• Addresses are the locations in memory of specified data.
• In assembly language mnemonic form an opcode is a command such as
MOV or ADD or JMP.

MOV AL, 34h

In this eg., the operands are the register named AL and the value 34 hex.
User Visible Registers
• True general purpose registers – register can contain the operand for any opcode

• Restricted (special purpose registers) – use for specific operations – floating point and
stack operations

• Data registers – used to hold data and cannot be employed in calculation of an

operand address. – Accumulator (AC)

• Address registers
• Segment registers – hold the base address of the segment

• Index register – used for indexed addressing and may be auto-incremented

• Stack pointer – points to the top of the stack (if there is a user-visible stack addressing, stacks in the
memory)
Condition Code Registers - Flags
• Condition codes are bits set by the CPU hardware as the result of
operations
• Machine instructions allow these bits to be read by implicit reference
• Programmer cannot alter them
• In some machines, sub –routine call will result in the automatic saving of all
user-visible registers, to be restored on return.
• Set of individual bits – flags
• Result of last operation is zero

• Can be read by programs

• Jump if zero – simplifies branch taking
Commonly used Registers

• Accumulator: This is the most common register, used to store

data taken out from the memory.
• General Purpose Registers: This is used to store data
intermediate results during program execution. It can be
accessed via assembly programming.
• Data Register : These registers only holds the data. The
restriction of these registers is, these can not be used for
operand address calculation
Control / Status - Special
Purpose Registers:
• Users do not access these registers. These registers are for
Computer system,
• MAR: Memory Address Register are those registers that holds the address
for memory unit.
• MBR: Memory Buffer Register stores instruction and data received from the
memory and sent from the memory.
• PC: Program Counter holds the address of the next instruction to be read
from memory after the current instruction is executed.
• IR: Instruction Register holds the instruction to be executed.
Control / Status registers (PSW)
• Parity Flag (PF) − It indicates the total number of 1-bits in the
result obtained from an arithmetic operation.
• Sign Flag (SF) − It shows the sign of the result of an arithmetic
operation. This flag is set according to the sign of a data item
following the arithmetic operation.
• Zero Flag (ZF) − It indicates the result of an arithmetic or
comparison operation. A nonzero result clears the zero flag to 0, and
a zero result sets it to 1.
Control / Status registers
• Auxiliary Carry Flag (AF) − It contains the carry from bit 3 to bit 4
following an arithmetic operation;
• Carry Flag (CF) − It contains the carry of 0 or 1 from a high-order
bit (leftmost) after an arithmetic operation. It also stores the contents
of last bit of a shift or rotate operation.
• Overflow Flag (OF) − It indicates the overflow of a high-order bit (leftmost
bit) of data after a signed arithmetic operation.
Control / Status registers
• Direction Flag (DF) − It determines left or right direction for moving or
comparing string data.
• Interrupt Flag (IF) − It determines whether the external interrupts like
keyboard entry, etc., are to be ignored or processed.
• Trap Flag (TF) − It allows setting the operation of the processor in single-
step mode. The DEBUG program we used sets the trap flag, so we could step
through the execution one instruction at a time.
Control /Status registers
Processor Registers – Intel
Architecture
• There are ten 32-bit and six 16-bit processor registers in IA-32 architecture. The
registers are grouped into three categories −
• General registers
• Control registers
• Segment registers

• The general registers are further divided into the following groups −
• Data registers
• Pointer registers
• Index registers
Connection between processor
& memory
Data Registers
Data Registers
• Some of these data registers have specific use in arithmetical operations.
• AX is the primary accumulator
• BX is known as the base register
• CX is known as the count register
• DX is known as the data register
Pointer Registers

• The pointer registers are 32-bit EIP, ESP, and EBP registers and corresponding
16-bit right portions IP, SP, and BP. There are three categories of pointer
registers −
• Instruction Pointer (IP) − The 16-bit IP register stores the offset address of
the next instruction to be executed.
• Stack Pointer (SP) − The 16-bit SP register provides the offset value within
the program stack.
• Base Pointer (BP) − The 16-bit BP register mainly helps in referencing the
parameter variables passed to a subroutine. The address in SS register is
combined with the offset in BP to get the location of the parameter.
Index Registers

• The 32-bit index registers, ESI and EDI, and their 16-bit
rightmost portions.
• SI and DI, are used for indexed addressing and sometimes used
in addition and subtraction.
• There are two sets of index pointers −
• Source Index (SI) − It is used as source index for string operations.
• Destination Index (DI) − It is used as destination index for string
operations.
8086 Microprocessor
Register Organization
8086
Segment
Registers
8086 Register
Organization
Find the Registers

• Stores the address of the memory location

• Stores the data or instruction fetched from the memory
• Stores the Instruction
• Default register
• Stores the memory location of the next Instruction
Find the Registers

• Stores the address of the memory location -MAR

• Stores the data or instruction fetched from the memory
-MBR
• Stores the Instruction - IR
• Default register - AC
• Stores the memory location of the next Instruction - PC
History of
Computers
First Generation –
Vacuum Tubes
History of Computers

• First Generation – Vacuum Tubes

• The IAS machine was the first electronic computer built at the
Institute for Advanced Study (IAS) in Princeton, New Jersey.
• Stored Program Concept
• John von Neumann
History of
Computer
s
First Generation –
Structure of IAS Computer
Structure of IAS Computer

• Dedicated units for Addition, Subtraction, Multiplication,

Division
• CA – Central Arithmetic part, CC – Central Control, M –
Memory
• Memory size – 4096 words, word = 40 bits

• How many bits required to address the 4096 word

Structure of IAS Computer

• Fixed Program Computers – Their function is very

specific and they couldn’t be programmed, e.g.
Calculators.

• Stored Program Computers – These can be programmed

to carry out many different tasks, applications are
stored on them, hence the name.
Structure of IAS Computer

• Same memory is used to store both the program and

data.
• The program is executed in written sequence.
• A program can modify itself when computer executes
the program.
Structure of IAS Computer

• The memory contains words – data or instruction

• IAS instructions are 20 bits long  8-bit opcode, 12-bit
address
• IAS instruction allow only one memory address.
• A memory space can hold two instruction
• Data follows signed bit representation (1 MSB for sign,
39-bit data)
Structure of IAS
• 40–bit data, 20–bit instruction
Computer
Structure of IAS
• 40–bit data, 20–bit instruction
Computer

Why do we
use 12-bits to
store the
address?
Structure of IAS Computer

• MBR (Memory Buffer Register) – used to send/receive a word from

M/IO
• MAR – specifies the memory address for Read/Write (R/W)
• IR – holds the instruction being executed
• IBR – holds the right (second 20-bit) instruction
• PC – holds the address of the next instruction to be fetched
• AC, MQ – holds the intermediate results (e.g. multiplying two 40-bit
data)
Registers in IAS
Registers in IAS
Von Neumann Bottleneck

• Uses the same memory for both instructions and data

• Memory access time limit the performance

• To avoid this issue, later architectures uses more

(general purpose) registers to hold the data
IAS Computer – let’s execute this code

PC
MAR
MBR
IR
IBR
AC
IAS Computer – Find the Registers’
content

PC 1
MAR 1
MBR LOAD M(X) 500, ADD M(X) 501
IR LOAD M(X) 500
IBR ADD M(X) 501
AC
IAS Computer – Find the Registers’
content

Let’s execute this

PC 1 instruction
MAR 1
Assume that the memory
MBR LOAD M(X) 500, ADD M(X) 501 500 has the value 3
IR LOAD M(X) 500
IBR ADD M(X) 501
AC
IAS Computer – Find the Registers’
content

PC 1
MAR 500
MBR 3
IR LOAD M(X) 500
IBR ADD M(X) 501
AC 3
IAS Computer – Find the Registers’
content

PC 1 Let’s execute this

MAR 500 instruction
MBR 3
Assume that the memory
IR LOAD M(X) 500 501 has the value 4
IBR ADD M(X) 501
AC 3
IAS Computer – Find the Registers’
content

PC 1
MAR 501
MBR 4
IR ADD M(X) 501
IBR
AC 7
IAS Computer – Find the Registers’
content

PC 2
MAR 2
MBR STORE M(X) 500, (Other Ins)
IR STORE M(X) 500
IBR Other Ins
AC 7
IAS Computer – Find the Registers’
content

PC 2
MAR 500
MBR STORE M(X) 500, (Other Ins)
IR STORE M(X) 500
IBR Other Ins
AC 7
IAS Computer Instruction Set
IAS Computer Instruction Set
IAS Computer Instruction Set
IAS Computer Instruction Set
IAS Computer Instruction Set
IAS Computer Instruction Set
IAS Computer Instruction Set
IAS Computer Instruction Set
IAS Computer Instruction Set
Structure of IAS Computer

• IAS operates by repeatedly performing an instruction

cycle
• Instruction Cycle involves FETCH & EXECUTE cycle
• From where do we fetch?
• What do we fetch?
• Where do we store the fetched information?
• What is the processing element?
• Where do we store the intermediate results?
 History of
Computers

• Instruction Cycle – FETCH

• To execute a program, what

do we fetch at first?
Instruction / Data

• Where do we fetch?
Instructio
n Cycle –
Fetch
Instructio
n Cycle –
Execute
Exercise #01
Exercise #01

• Hint – find the total number of instructions in IAS

computer
Exercise #01
Exercise #02

• List IAS instructions that do not require memory access.

• Find the percentage of instructions require memory
access.
Exercise #02

• List the IAS instructions that do not require memory

access

• Find the percentage of instructions that require memory

access
 Separate memory for
Harvard programs and data

Architectu
re Parallel access to data
and instructions is
possible
Harvard Architecture
Harvard Architecture

• Different-sized cells can be allowed in both the

memories
• Greater memory bandwidth
• There is less chance of corruption since data and
instructions are transferred via different buses
Von Neumann vs Harvard Architecture
Architecture
Van Neumann Architecture
Harvard Architecture
• Stored program concept • Modern computer
• Common memory for both architecture
data and program • Separate memory for data
• Common bus b/w memory and program
and CPU • Separate buses for data and
program
• An instruction execution
requires 2 clock cycles • One clock cycle is enough
for instruction execution
• Parallel fetch is not possible
• Parallel fetch is possible
CISC | RISC
Instruction Set Computers

• Complex or Simple
• CISC (Complex Instruction Set Computer)
• RISC (Reduced Instruction Set Computer)
 CISC
Large amount of
different and complex
instructions
Make use of complex
addressing modes
Use micro-program
control unit
Limited number of
registers.
 RISC
Small and limited number of
instructions
Use a hardwired control unit

Consume less power and have high

performance
Limited instruction with memory
access
Simple addressing modes

RISC instruction is of uniform fixed

length
RISC vs
CISC
CISC vs RISC
Next
Module • Data Representation and Computer
Arithmetic

02