MULTIPLEXERS.ppt

MULTIPLEXERS
Name: M.LAVAN
Section: CSE-B
Rollno:23R01a05a9
Multiplexers :
• A multiplexer is often abbreviated as MUX.As in decoders,
multiplexer ICs may have an enable input to control the operation of
the unit. When the enable input is in a given binary state, the
outputs are disabled, and when it is in the other state (the enable
state), the circuit functions as a normal multi-plexer.
• Multiplexing means transmitting a large number of information units
over a smaller number of channels or lines.
• A digital multiplexer is a combinational circuit that selects binary
information from one of many input lines and directs it to a single
output line.
• The selection of a particular input line is controlled by a set of
selection lines.
4 x 1 multiplexer :
• A 4-to-1-line multiplexer is shown in Fig. 5-16.

• Each of the four input lines, lo to 13, is applied to one input of an AND gate. Selection lines s,
and so are decoded to select a particular AND gate. The OR gate output is now equal to the
value of 12, thus providing a path from the selected input to the output.
• A multiplexer is also called a data selector, since it selects one of many inputs and steers the
binary information to the output line.
• The AND gates and inverters in the multiplexer resemble a decoder circuit and, in-deed, they
decode the input-selection lines.
In general, a 2"-to-1-line multiplexer is constructed from an n-to-2" decoder by adding to it 2"
input lines, one to each AND gate.
•
• The outputs of the AND gates are applied to a single OR gate to provide the 1-line output. The
size of a multiplexer is specified by the number 2" of its input lines and the single output line. It
is then implied that it also contains n selection lines.
A quadruple 2-to-1-line multiplexer:
• In some cases, two or more multiplexers are enclosed within one IC
package. The selection and enable inputs in multiple-unit ICs may be
common to all multiplexers. As an illustration.
• a quadruple 2-to-1-line multiplexer IC is shown in Fig. 5-17. It has four
multiplexers, each capable of selecting one of two input lines. Output Y,
can be selectedto be equal to either A, or B,.
• Similarly, output Y, may have the value of A2 or B2, and so on. One input
selection line, S, suffices to select one of two lines in all four multi-plexers.
The control input E enables the multiplexers in the 0 state and disables
them in the 1 state. Although the circuit contains four multiplexers, we
may think of it as a cir cuit that selects one in a pair of 4-input lines. As
shown in the function table, the unitis selected when E = 0.Then, if S = 0,
the four A inputs have a path to the outputs.On the other hand, if S = 1,
the four B inputs are selected. The outputs have all O'swhen E = 1,
regardless of the value of S.
• As shown in the function table, the unitis
selected when E = 0.Then, if S = 0, the four
A inputs have a path to the outputs.On the
other hand, if S = 1, the four B inputs are
selected. The outputs have all O'swhen E =
1, regardless of the value of S.
• As shown in the function table, the unitis
selected when E = 0.Then, if S = 0, the four
A inputs have a path to the outputs.On the
other hand, if S = 1, the four B inputs are
selected. The outputs have all O'swhen E =
1, regardless of the value of S.
8 to 1 Multiplexer :
• An 8 to 1 multiplexer is a digital circuit that selects one of eight input signals and directs
it to a single output. It works by using select lines to determine which input is passed
through to the output.
• A multiplexer (MUX) is a type of logic circuit that selects one of many inputs and forwards
it to a single output. The selection of which input to forward is determined by a set of
control signals.
• Signal Selection : The multiplexer chooses one input signal out of several and routes it
to the output.
• Control Signals : The selection process is controlled by input signals, which determine
which of the data inputs is passed through.
• Digital Switching: Multiplexers operate on digital signals, allowing for the transmission
of data between different parts of a digital system.
Diagrams of Logical circuit ,implementation and truth table of 8 X 1 MUX
Boolean-Function Implementation:
• It was shown in the previous section that a decoder canbeused to implement

a Boolean function by employing an external OR gate. A quick reference to
the multiplexer of Fig. 5-16 reveals that it is essentially a decoder with th-he
OR gate already available. The minterms out of the decoder to be chose-n can
be controlled with the input lines.
• The minterms to be included with the function being implemented are chosen
by making their corresponding input lines equal to I; those minterms not
included in the function are disabled by making their input lines equal to 0.
• This gives a method for implementing any Boolean function of n variables
with a 2"-to-1 multiplexer. However, it is possible to do better than that.If we
have a Boolen function of n + 1 variables, we take n of these variables and
connect them to the selection lines of a multiplexer.
• The remaining single variable of the function is used for the
inputs of the multiplexer. If A is this single variable, the inputs
of the multiplexer are chosen to be either A or A' or 1 or 0.
• By judicious use of these four values for the inputs and by
connecting the other variables to the selection lines, one can
implement any Boolean function with a multiplexer. In this
way, it is possible to generate any function of n + 1 variables
with a 2"-to-1 multiplexer.
• The remaining single variable of the function is used for the
inputs of the multiplexer. If A is this single variable, the inputs
of the multiplexer are chosen to be either A or A' or 1 or 0.
• Implement the following function with a multiplexer:
• F (A, B, C, D) = £(0, 1, 3, 4, 8, 9, 15)
• This is a four-variable function and, therefore, we need a
multiplexer with three selec-tion lines and eight inputs.
We choose to apply variables B, C, and D to the
selectionlines.
• The implementation table is then as shown in Fig. 5-20.
The first half of the
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MULTIPLEXERS

• A 4-to-1-line multiplexer is shown in Fig. 5-16.

• It was shown in the previous section that a decoder canbeused to implement

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