Unit-3

Control Unit

Computer Organization & Architecture (KCA-105)

Prepared By Prof.Asheesh Pandey
Control Unit:- It effectively is the nerve center that sends signals to other units and senses their states. The actual timing
signals that govern the transfer of data between input unit, processor, memory and output unit are generated by the control
unit. To perform a given task, an appropriate program consisting of a list of instructions is stored in the memory. Individual
instructions are brought from the memory into the processor, which executes the specified operations.

Examples: - Add LOCA, Ro

This instruction adds the operand, stored at memory location LOCA, in register R 0 & places the sum into register.
This instruction requires the performance in several steps:-
1. First the instruction is fetched from the memory into the processor.
2. The operand at LOCA is fetched and added to the contents of R 0
3. Finally the resulting sum is stored in the register R.
In some computers, these two types of operations can be performed by separate instructions for performance
reasons.
1. Load LOCA, R1
2. Add R1, R0
Register: It is a special, high-speed storage area within the CPU. All data must be represented in a register before it can be
processed. For example, if two numbers are to be multiplied, both numbers must be in registers, and the result is also placed
in a register. (The register can contain the address of a memory location where data is stored rather than the actual data
itself.)
The number of registers that a CPU has and the size of each (number of bits) help determine the power and speed of a CPU.
For example a 32-bit CPU is one in which each register is 32 bits wide. Therefore, each CPU instruction can manipulate 32 bits
of data. In high-level languages, the compiler is responsible for translating high-level operations into low-level operations that
access registers. Computer Organization & Architecture (KCA-105) Prepared By Prof. Asheesh Pandey
INSTRUCTION- Instruction is a command to the processor to perform a given task on specified data. A computer
instruction refers to a binary code that controls how a computer performs micro-operations in a
series. They are saved in the memory. Every computer has its own set of instructions.

INSTRUCTION FORMATS- An instruction format or instruction code is a group of bits used to perform a particular operation
on the data stored in computer. • Processor fetches an instruction from memory and decodes the bits to execute the
instruction. • Different computers may have their own instruction set.
Suppose in a 16 bit instruction, First 12 bits (0-11) specify an address. •Next 3 bits specify operation cod (opcode).
• Left most bit specify the addressing model I = 0 for direct address I = 1 for indirect address.

Computer Organization & Architecture (KCA-105) Prepared By Prof. Asheesh Pandey

Computer Organization & Architecture (KCA-105) Prepared By Prof. Asheesh Pandey
Computer Organization & Architecture (KCA-105) Prepared By Prof. Asheesh Pandey
Computer Organization & Architecture (KCA-105) Prepared By Prof. Asheesh Pandey
The number of address fields in the instruction format of a computer depends on the internal organization of its registers.
Mostly computers fall into one of three types of CPU organizations:-
1. Single accumulator organization 2. General register organization. 3 Stack organization.
The instruction can be classified as three, two, one address instruction or zero address instruction,
depending on the number of address fields. Four types of instructions are available on the basis of referenced
address fields :
THREE-ADDRESS INSTRUCTIONS- Computers with three-address instruction formats can use each address field to specify
either a processor register or a memory operand. The program in assembly language that evaluates X = (A + B) ∗ (C + D) is
shown below:-
ADD R1, A, B R1 ← M [A] + M [B]
ADD R2, C, D R2 ← M [C] + M [D]
MUL X, R1, R2 M [X] ← R1 ∗ R2 OR MUL R3, R1, R2 R3 ← R1 ∗ R2
It is assumed that the computer has two processor registers, R1 and R2. The symbol M [X] denotes the operand at memory
address symbolized
TWO-ADDRESS by X.
INSTRUCTIONS- Two address instructions are the most common in commercial computers. Here again each
address field can specify either a processor register or a memory word. The program to evaluate X = (A + B) ∗ (C + D) is as
follows:-
MOV R1, A R1 ← M [A]
ADD R1, B R1 ← R1 + M [B]
MOV R2, C R2 ← M [C]
ADD R2, D R2 ← R2 + M [D]
MUL R1, R2 R1 ← R1∗ R2
MOV X, R1 M [X] ← R1 Computer Organization & Architecture (KCA-105) Prepared By Prof. Asheesh Pandey
The MOV instruction moves or transfers the operands to and from memory and processor registers.
ONE-ADDRESS INSTRUCTIONS- One-address instructions use an implied accumulator (AC) register for all data manipulation. For
multiplication and division there is a need for a second register. However, here we will neglect the second and assume that the
AC contains the result of tall operations. The program to evaluate X = (A + B) ∗ (C + D) is-
LOAD A AC ← M [A]
All operations are done between the AC register and a memory
ADD B AC ← A C + M [B]
operand. T is the address of a temporary memory location
STORE T M [T] ← AC
required for storing the intermediate result.
LOAD C AC ← M [C]
ADD D AC ← AC + M [D]
MUL T AC ← AC ∗ M [T]
STORE X M [X] ← AC
ZERO-ADDRESS INSTRUCTIONS- A stack-organized computer does not use an address field for the instructions ADD and MUL.
The PUSH and POP instructions need an address field to specify the operand that communicates with the stack. The following
program shows how X = (A + B) ∗ (C + D) will be written for a stack organized computer.
PUSH A TOS ← A
PUSH B TOS ← B
ADD TOS ← (A + B)
PUSH C TOS ← C To evaluate arithmetic expressions in a stack computer, it is necessary
PUSH D TOS ← D to convert the expression into Reverse Polish Notation RPN. The name
ADD TOS ← (C + D) “zero-address” is given to this type of computer because of the
MUL TOS ← (C + D) ∗ (A +B) absence of an address field in the computational instructions.
POP X M [X] ← TOS
Computer Organization & Architecture (KCA-105) Prepared By Prof. Asheesh Pandey
INSTRUCTION CYCLE:-
1. A program residing in the memory unit of the computer consists of a sequence of instructions.
2. The program is executed in the computer is going through a cycle for each instruction.
3. Each instruction cycle is subdivided into a sequence of sub cycles or phases. From fetching of instruction to the
completion of execution of instruction whatever happens is called instruction cycle.
4. The instruction cycle (also known as the fetch–decode–execute cycle, or simply the fetch-execute
cycle) is the cycle that the central processing unit (CPU) follows from boot-up until the computer
has shut down in order to process instructions.
5. The reason we called this cycle because it will happen for every instruction. Each instruction cycle consists of the
following phases:
• Fetch an instruction from memory.
• Decode the instruction.
• Read the effective address from memory if the instruction has an indirect address.
• Execute the instruction.
• Fetch and Decode

Computer Organization & Architecture (KCA-105) Prepared By Prof. Asheesh Pandey

MicroOperations-
 These are elementary operations performed on to the data stored in registers. OR
 In computer central processing units, micro-operations are the functional operations of a processor. These are low level
instructions used in some designs to implement complex machine instructions. They generally perform operations on data
stored in one or more registers.
 Micro Operation is a simple operation that can be performed during one clock period. The result of this operation may
replace the previous binary information of register or the result may be transferred to another register. • Examples of
micro-operations are shift, move, count, add and load etc.
 Types of Micro-Operation:-

1. Register Transfer Micro-Operation:- Ex- R1 R2+R3

2. Arithmetic Micro-Operation:- Ex- R3 → R1 + R2 (Addition) , R3 → R1 + R2′ + 1 (Subtraction) etc.
3. Logic Micro-Operations:- Ex- P: R1 ←R1 ⊕R2 XOR of R2 and R1
4. Shift Micro-Operations:- These operations are used for serial transfer of data. They are also used in conjunction with
arithmetic, logic, and other data-processing operation. The content of register can be shifted to the left or to the right.
At the same time the bits are shifted, the flip flop receives the binary information from the serial input.
• Logical Shift:- The symbol “shl” is used for logical shift left and “shr” is used for logical shift right.
• Circular Shift:-“cil” and “cir” are used for circular shift left and circular shift right respectively.
• Arithmetic Shift:- A shift operator, sometimes termed a signed shift. There are two types of arithmetic
left shift ashl and the arithmetic right shift ashr.
Computer Organization & Architecture (KCA-105) Prepared By Prof. Asheesh Pandey
Reduced Instruction Set Computer (RISC)-
• Computers that use fewer instructions with simple constructs so they can be executed much faster within the CPU without
having to use memory as often are classified as RISC.
• Relatively few instructions and few addressing modes
• Memory access limited to load and store instructions as all operations done within the registers of the CPU
• Fixed-length, easily decoded instruction format, single-cycle instruction execution.
• Hardwired rather than microprogrammed control.
• The small set of instructions of a typical RISC processor consists mostly of register-to-register operations, Thus, each
operand is brought into a processor register with a load instruction. All computations are done among the data stored in
processor registers. Results are transferred to memory by means of store instructions
• A RISC computer has a small set of simple and general instructions, rather than a large set of complex and specialized ones.
• A reduced instruction set computer (RISC) is a computer that
uses a central processing unit (CPU) that implements the
processor design principle of simplified instructions.
• To date, RISC is the most efficient CPU architecture
technology. This architecture is an evolution and alternative
to complex instruction set computing (CISC).
• With RISC, the basic concept is to have simple instructions
that do less but execute very quickly to provide better
performance

Computer Organization & Architecture (KCA-105) Prepared By Prof. Asheesh Pandey

Complex Instruction Set Computer (CISC)-

• It is a computer in which single instructions can execute several low level operations (such as a load from memory, an
arithmetic operation, and a memory store) or are capable of multi-step operations or addressing modes within single
instructions.
• The term is in contrast to reduced instruction set computer (RISC) and has therefore become something of an umbrella
term for everything that is not RISC, from large and complex mainframe computers to simplistic microcontrollers where
memory load and store operations are not separated from arithmetic instructions.
• A modern RISC processor can therefore be much more complex then a modern microcontroller using a CISC labeled
instruction set, especially in the complexity of its electronic circuits, but also in the number of instructions or the
complexity of their encoding patterns.
• The only typical differentiating characteristic is that most RISC designs use uniform instruction length for almost all
instructions, and employ strictly separate load/store-instructions.
• The main intend of the CISC processor architecture is to complete task by using less number of assembly lines. For this
purpose, the processor is built to execute a series of operations. Complex instruction is also termed as MULT, which
operates memory banks of a computer directly without making the compiler to perform storing and loading functions.
• To simplify the computer architecture, CISC supports microprogramming. CISC have more number of predefined instructions
which makes high level languages easy to design and implement. CISC consists of less number of registers and more number
of addressing modes, generally 5 to 20. CISC processor takes varying cycle time for execution of instructions – multi-clock
cycles.

Computer Organization & Architecture (KCA-105) Prepared By Prof. Asheesh Pandey

Advantages of CISC architecture-
1. Each machine language instruction is grouped into a microcode instruction and executed accordingly, and then are stored
inbuilt in the memory of the main processor, termed as microcode implementation.
2. As the microcode memory is faster than the main memory, the microcode instruction set can be implemented without
considerable speed reduction over hard wired implementation.
3. Entire new instruction set can be handled by modifying the micro program design.
4. CISC, the number of instructions required to implement a program can be reduced by building rich instruction sets and
can also be made to use slow main memory more efficiently.
5. Because of the superset of instructions that consists of all earlier instructions, this makes micro coding easy.

Drawbacks of CISC-
6. The amount of clock time taken by different instructions will be different – due to this – the performance of the machine
slows down.
7. The instruction set complexity and the chip hardware increases as every new version of the processor consists of a subset
of earlier generations.
8. Only 20% of the existing instructions are used in a typical programming event, even though there are many specialized
instructions in existence which are not even used frequently.
9. The conditional codes are set by the CISC instructions as a side effect of each instruction which takes time for this setting
– and, as the subsequent instruction changes the condition code bits – so, the compiler has to examine the condition
code bits before this happens

Computer Organization & Architecture (KCA-105) Prepared By Prof. Asheesh Pandey

Differences Between RISC Vs CISC-

Computer Organization & Architecture (KCA-105) Prepared By Prof.Asheesh Pandey

Hardwired v/s Micro-programmed Control Unit- To execute an instruction, the control unit of the CPU must generate the
required control signal in the proper sequence. There are two approaches used for generating the control signals in proper
sequence as Hardwired Control unit and Micro-programmed control unit.
Hardwired Control Unit – The control hardware can be viewed as a state machine that changes from one state to another in
every clock cycle, depending on the contents of the instruction register, the condition codes and the external inputs. The
outputs of the state machine are the control signals.
The sequence of the operation carried out by this machine is determined by the wiring of the logic elements and hence
named as “hardwired”.
1. Fixed logic circuits that correspond directly to the Boolean expressions are used to generate the control signals.
2. Hardwired control is faster than micro-programmed control.
3. A controller that uses this approach can operate at high speed.
Characteristics:-
1. It uses flags, decoder, logic gates and other digital circuits.
2. As name implies it is a hardware control unit.
3. On the basis of input Signal output is generated.
4. Difficult to design, test and implement.
5. Inflexible to modify.
6. Faster mode of operation.
7. Expensive and high error.
8. Used in RISC processor.

Computer Organization & Architecture (KCA-105) Prepared By Prof. Asheesh Pandey

Micro-programmed Control Unit –
1. The control signals associated with operations are stored in special memory units inaccessible by the programmer as
Control Words.
2. Control signals are generated by a program are similar to machine language programs.
3. Micro-programmed control unit is slower in speed because of the time it takes to fetch microinstructions from the control
memory

Characteristics-
1. It uses sequence of micro-instruction in micro programming
language.
2. It is mid-way between Hardware and Software.
3. It generates a set of control signal on the basis of control line.
4. Easy to design, test and implement.
5. Flexible to modify.
6. Slower mode of operation.
7. Cheaper and less error.
8. Used in CISC processor

Computer Organization & Architecture (KCA-105) Prepared By Prof. Asheesh Pandey

Differences between Hardwired & Micro-programmed Control Unit-

Characteristics Hardwired Micro-programmed Control

1. Speed Fast Slow
2. Implementation Hardware Software
3. Flexibility Not Flexible Flexible
4. Ability to handle
Complex instruction set Difficult Easier
5. Design process Difficult for more operation Easy
6. Memory Not Used Control memory used
7. Chip are efficiency Uses less area Uses more area
8. Used in RISC CISC

Computer Organization & Architecture (KCA-105) Prepared By Prof. Asheesh Pandey

Horizontal Micro-Program-
• The horizontal micro-programmed provides higher degree of parallelism & it is suitable in multi-processor system.
• It requires more bits for control word (1 it for every control signal)

Vertical Micro-Program-
• The vertical micro-programming reduces the size of control words by encoding, control signal pattern before it is stored in
control memory. it offers more flexibility than horizontal micro-programming.
• The pattern with vertical-programming is the maximum degree of parallelism is 1(due to the decoder).

Differences-

Horizontal Vertical
1. Long Format Short Format
2. Ability to express a high degree of parallelism Limited ability to express parallel micro-operations
3. Little encoding of control information Considerable encoding of the control information
4. Usefull when higher operating speed is desired Slower operating speed

Computer Organization & Architecture (KCA-105) Prepared By Prof. Asheesh Pandey

Pipelining-
1. Pipelining is a technique of decomposing a sequential process into sub-operations, with each sub-process being executed
in a special dedicated segment that operates concurrently with all other segments.
2. The processor executes a program by fetching and executing instructions, one after the other.
3. Let Fi and Ei refer to the fetch and execute steps for instruction I i .
4. Execution of a program consists of a sequence of fetch and execute steps as shows is Fig.
5. Now consider a computer that has two separate hardware units, one for fetching
instructions and another for executing them, as shown in Fig.
6. The instruction fetched by the fetch unit is deposited in an intermediated storage buffer Bi.
7. The results of execution are deposited in the destination location specified by the instructions.
8. For these purposes, we assume that both the source and destination of the data operated in by the instructions are
inside the block labelled “Execution unit”
9. The computer is controlled by a clock whose period is such that the fetch
and execute steps of any instruction can be completed in one clock cycle.
10. Operation of the computer proceeds as in Fig.
11. In the first clock cycle, the fetch unit fetches an instruction I1 (step F1 ) and stores it
in buffer Bi at the end of the clock cycle.
12. In the second clock cycle, the instruction fetch unit proceeds with the fetch operation for instruction I 2 (Step F2 ).
Meanwhile, the execution unit performs the operation specified by the instruction I 1 , which is available to it in buffer Bi
(Step E1 ). By the end of the second clock cycle, the execution of instruction I 1 is completed and instruction I2 is
available.
13. Instruction I2 is stored in Bi by replacing I1 , which is no longer needed. Step E2 is performed by the execution unit during
the third clock cycle, while instruction I3 is being
Computer Organization fetched
& Architecture by the fetch unit.
(KCA-105) In this
Prepared manner,
By Prof. Asheesh both
Pandey fetch and execute units
1.Arithmetic Pipeline :
An arithmetic pipeline divides an arithmetic problem into
various sub problems for execution in various pipeline
segments. It is used for floating point operations,
multiplication and various other computations. The
process or flowchart arithmetic pipeline for floating point
addition
Floatingispoint
shownaddition
in the diagram.
using arithmetic pipeline :
The following sub operations are performed in this case:
1.Compare the exponents.
2.Align the mantissas.
3.Add or subtract the mantissas.
4.Normalize the result

Steps-
• First of all the two exponents are compared and the
larger of two exponents is chosen as the result
exponent.
• The difference in the exponents then decides how
many times we must shift the smaller exponent to the
right.
• Then after shifting of exponent, both the mantissas
get aligned.
• Finally the addition of both numbers take place
Computer Organization & Architecture (KCA-105) Prepared By Prof. Asheesh Pandey
followed by normalization of the result in the last
2. Instruction Pipeline :
In this a stream of instructions can be executed by overlapping
fetch, decode and execute phases of an instruction cycle. This
type of technique is used to increase the throughput of the
computer system.
An instruction pipeline reads instruction from the memory
while previous instructions are being executed in other segments
of the pipeline. Thus we can execute multiple instructions
simultaneously. The pipeline will be more efficient if the
instruction cycle is divided into segments of equal duration.
In the most general case computer needs to process each
instruction in following sequence of steps:
1.Fetch the instruction from memory (FI)
2.Decode the instruction (DA)
3.Calculate the effective address
4.Fetch the operands from memory (FO)
5.Execute the instruction (EX)
6.Store the result in the proper place
The flowchart for instruction pipeline is shown in fig-.

Computer Organization & Architecture (KCA-105) Prepared By Prof. Asheesh Pandey

Advantages of pipelining
The biggest advantage of pipelining is that it reduces the processor's cycle time. This is because it can process
more instructions simultaneously, while reducing the delay between completed instructions. Although pipelining
doesn't reduce the time taken to perform an instruction. This would sill depend on its size, priority and complexity.
It does increase the processor's overall throughput.
pipelined processors usually operate at a higher clock frequency than the RAM clock frequency. This makes the
system more reliable and also supports its global implementation.
Possible issues in pipelines
Although processor pipelines are useful, they are prone to certain problems that can affect system performance and throughput.
Two such issues are data dependencies and branching.
Data dependencies
A data dependency happens when an instruction in one stage depends on the results of a previous instruction but that result is
not yet available. This can happen when the needed data has not yet been stored in a register by a preceding instruction
because that instruction has not yet reached that step in the pipeline.
Since the required instruction has not been written yet, the following instruction must wait until the required data is stored in the
register. This waiting causes the pipeline to stall. At the same time, several empty instructions, or bubbles, go into the pipeline,
slowing it down even more.
The data dependency problem can affect any pipeline. However, it affects long pipelines more than shorter ones because, in the
former, it takes longer for an instruction to reach the register-writing stage.
Branching
Branch instructions can be problematic in a pipeline if a branch is conditional on the results of an instruction that has not yet
completed its path through the pipeline. If the present instruction is a conditional branch and its result will lead to the next
instruction, the processor may not know the next instruction until the current instruction is processed. That's why it cannot make
a decision about which branch to take because the required values are not written into the registers.

Computer Organization & Architecture (KCA-105) Prepared By Prof. Asheesh Pandey