23CSE213

Computer Organization and

Architecture
Basics of hardware design

Department of CSE
2024-25 Even semester
 Contents
• Combinational vs sequential logic
• Physical constraints

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 Combinational vs Sequential logic

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 Comparison in terms of performance
• Combinational circuits are generally faster and perform better than sequential
circuits because they only require the current state as input:
• Speed: Combinational circuits are faster because they don't need to wait for past inputs or
clock cycles. The output is generated as soon as the input changes.
• Design: Combinational circuits are relatively straightforward to design.

• Sequential circuits are slower because they rely on previous inputs and memory elements to
store and process past data:
• Speed: Sequential circuits are slower because they rely on memory and clock signals.
• Design: Sequential circuits are more complex due to memory elements and timing
considerations.
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 Physical constraints
• In designing a system, a designed must consider aspects other than logic.
• Factors to be considered:
• Gate delay
• Fan-in
• Fan-out
• Power dissipation
• Noise margin

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 Gate delay
• When the input to a logic gate is changed, the
output will not change immediately.
• The switching elements within a gate take a finite
time to react to a change (transition) in input.
• As a result, the change in the gate output is
delayed with respect to the input change.
• Such delay is called the propagation delay of the
logic gate (tp)
• The propagation delay for a 0-to-1 output change
(tpLH) may be different than the delay for a 1-to-0
change (tpHL). (Due to the components like
transistors and capacitors)
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 Gate delays

the difference in delay happens because

the parts of the circuit responsible for
turning the signal on (low-to-high) are
slower than the parts responsible for
turning the signal off (high-to-low).
PMOS transistor-For on
NMOS transistor –For off

If the propagation delay is 10 ns for low-

to-high, the high-to-low delay might
range from 8 ns.

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 Why gate delay has to be considered?
• The analysis of a combinational circuit ignoring delays can predict only its
steady-state behavior.
–Predicts a circuit’s output as a function of its inputs assuming that the inputs have been
stable for a long time, relative to the delays in the circuit’s electronics.
• Because of circuit delays, the transient behavior of a combinational logic
circuit may differ from what is predicted by steady-state analysis.
• Timing hazard:
• circuit’s output may produce a short pulse (“glitch”) at a time when steady state
analysis predicts that the output should not change.

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 Logic families overview
• Logic families refer to groups of electronic circuits that implement logic gates
(like AND, OR, NOT) with similar electrical characteristics. Here's a brief
overview of major logic families:

• Different types of technologies being used to build different logic gates.

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 TTL and ECL
TTL and ECL – based on Bipolar Junction Transistor (BJT).
• TTL - well-established popular logic family.
Types of Bipolar Junction
• ECL - high-speed operation. Transistor
• NPN stands for Negative-Positive-Negative, where
(Collector (C) and Emitter (E) are N-type, while Base (B)
is P-type.). Current flows from Collector to
Emitter when a small current is applied to
the Base.

• PNP stands for Positive-Negative-Positive.

Collector and Emitter are P-type, while the
Base is N-type. Current flows from Emitter
to Collector when a small current is applied
to the Base. PNP transistors are used less
frequently in Dept
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 MOS and CMOS
• MOS and CMOS- based on Field Effect Transistor also said to be unipolar
transistor.
• large scale integrated circuits (high component density) and low power consumption.
• CMOS logic consumes far less power than MOS or bipolar logic ( MOSFET is used CMOS
technology).).

• Source (S), Drain (D), and Gate (G).

• JFET is simpler, cheaper, and operates in depletion mode. It’sTypes

usedoffor basic
field effect
amplifying and analog tasks. transistor

• MOSFET is faster, more versatile (enhancement and depletion modes), and is the
backbone of modern digital electronics.
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 Comparation

• Power Consumption: CMOS < TTL < ECL

• Speed: ECL > CMOS > TTL
• Cost: CMOS and TTL are cheaper and easier to manufacture.

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 Fan-in
• Fan-in refers to the maximum number of input signals that feed the input
equations of a logic cell.

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 Why Fan-in?
• A physical gate cannot have a large number of inputs.
• For CMOS technology, the more inputs a gate has the slower it is.
• Hence, for CMOS, the fan-in is restricted to 4 inputs.
• TTL gates can have fan-in as 8.

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 Fan-out
• Fan-out refers to the maximum number of output signals that are fed by the
output equations of a logic cell.
• If output of gate A is connected to input of gate B, then gate A is said to be
driver gate, gate B is said to be load gate.

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 Fan-out and Gate drive
• A driver gate may have more than one load gate. There is a limit to the
number of gate inputs that a single output can drive.
• More fan-out, gate delay increases.
• It is advisable to avoid loads much higher than 8 loads.

• Drive refers to the current driving-ability of a gate.

• It is the amount of current the gate can deliver to its load devices.

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 Power
• Power dissipation is the supplied power required to operate the desired logic
function.
• Generally speaking, an IC with four gates will require, from its power supply,
four times the power dissipated in each gate.
• The total power dissipation equals the sum of power consumed by all gates.
• If one gate consumes a power of P, then four gates consume 4×P.
• A complex electronic system may have many thousands of gates. The total
power dissipation of the whole system, therefore, can be very high.
Issue
• Heat Generation- cause thermal stress on components, reducing their
performance and reliability.
• Energy Inefficient
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 Example:
• In a microprocessor, if power dissipation is too high, it will require a large
heat sink and cooling fans to keep it operational.
• For a mobile phone, high power dissipation will drain the battery quickly,
making the device inconvenient for users.

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 Noise margin
• Noise margin is the maximum noise voltage added to
the input signal of a digital circuit that does not cause an
undesirable change in the output.
• There are two types of noise to be considered.
• DC noise is caused by a drift in the voltage levels of a signal.
• AC noise is a random pulse that may be created by other
switching signals.
• Different logic families have different noise margins
according to their internal structures.
• TTL gate will have a noise margin of 1V
• CMOS gate has a noise margin of 40% of the supply voltage
(i.e. if VDD = 5V, its noise margin is 2V)

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 Noise margin - example
• Consider the noise margin as 1 V.
5 V – Logic
1

4 V – Till 4 V – it is acceptable as
Logic 1

1 V – Till 1 V – it is acceptable as
Logic 0

0 V – Logic
0

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 Recap
• Sequential vs combinational concepts
• Physical constraints

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