Computer System Overview

Computer System Overview
Chapter 1
Operating System
Exploits the hardware resources of one or more processors Provides a set of services to system users Manages secondary memory and I/O devices
Basic Elements
Processor Main Memory volatile referred to as real memory or primary memory I/O modules secondary memory devices communications equipment terminals System bus communication among processors, memory, and I/O modules
3
Processor
Two internal registers
Memory address register (MAR)
Specifies the address for the next read or write
Memory buffer register (MBR)

Contains data written into memory or receives data read from memory
I/O address register I/O buffer register
Top-Level Components
CPU System Bus Main Memory

0 1 2
PC IR
MAR MBR I/O AR
Ins tru ction Ins tru ction Ins tru ction Data Data Data Data
Exe cution unit
I/O BR
I/O Module
n-2 n-1
Buffers
PC IR MAR MBR I/O AR I/O BR
= = = = = =
Program counter Ins truction regis ter Memory address register Memory buffer register Input/output address register Input/output buffer regis ter
Figure 1.1 Computer Components: Top-Level View
Processor Registers
User-visible registers
Enable programmer to minimize mainmemory references by optimizing register use
Control and status registers

Used by processor to control operating of the processor Used by privileged operating-system routines to control the execution of programs
6
User-Visible Registers
May be referenced by machine language Available to all programs - application programs and system programs Types of registers
Data Address
Index Segment pointer Stack pointer
7
User-Visible Registers
Address Registers
Index
Involves adding an index to a base value to get an address
Segment pointer
When memory is divided into segments, memory is referenced by a segment and an offset
Stack pointer
Points to top of stack
8
Control and Status Registers

Program Counter (PC)
Contains the address of an instruction to be fetched
Instruction Register (IR)

Contains the instruction most recently fetched
Program Status Word (PSW)

Condition codes Interrupt enable/disable Supervisor/user mode
Control and Status Registers

Condition Codes or Flags
Bits set by the processor hardware as a result of operations Examples
Positive result Negative result Zero Overflow
10
Instruction Execution
Two steps
Processor reads instructions from memory
Fetches
Processor executes each instruction
11
Instruction Cycle
12
Instruction Fetch and Execute

The processor fetches the instruction from memory Program counter (PC) holds address of the instruction to be fetched next Program counter is incremented after each fetch
13
Instruction Register
Fetched instruction is placed in the instruction register Categories
Processor-memory
Transfer data between processor and memory
Processor-I/O
Data transferred to or from a peripheral device
Data processing
Arithmetic or logic operation on data
Control
Alter sequence of execution
14
Characteristics of a Hypothetical Machine
15
Example of Program Execution
16
Direct Memory Access (DMA)

I/O exchanges occur directly with memory Processor grants I/O module authority to read from or write to memory Relieves the processor responsibility for the exchange
17
Interrupts
Interrupt the normal sequencing of the processor Most I/O devices are slower than the processor
Processor must pause to wait for device
18
Classes of Interrupts
19
Program Flow of Control Without Interrupts
20
Program Flow of Control With Interrupts, Short I/O Wait

User Program 1 I/O Program 4 I/O Command WRITE
2a
2b
Interrupt Handler 5 END
WRITE
3a
3b
WRITE (b) Interrupts; short I/O wait
21
Program Flow of Control With Interrupts; Long I/O Wait
22
Interrupt Handler
Program to service a particular I/O device Generally part of the operating system
23
Interrupts
Suspends the normal sequence of execution
24
Interrupt Cycle
25
Interrupt Cycle
Processor checks for interrupts If no interrupts fetch the next instruction for the current program If an interrupt is pending, suspend execution of the current program, and execute the interrupt-handler routine
26
Timing Diagram Based on Short I/O Wait
27
Timing Diagram Based on Short I/O Wait
28
Simple Interrupt Processing
29
Changes in Memory and Registers for an Interrupt
30
Changes in Memory and Registers for an Interrupt
31
Multiple Interrupts
Disable interrupts while an interrupt is being processed
32
Multiple Interrupts
Define priorities for interrupts
33
Multiple Interrupts
34
Multiprogramming
Processor has more than one program to execute The sequence the programs are executed depend on their relative priority and whether they are waiting for I/O After an interrupt handler completes, control may not return to the program that was executing at the time of the interrupt
35
Memory Hierarchy
Faster access time, greater cost per bit Greater capacity, smaller cost per bit Greater capacity, slower access speed
36
Memory Hierarchy
37
Going Down the Hierarchy

Decreasing cost per bit Increasing capacity Increasing access time Decreasing frequency of access of the memory by the processor
Locality of reference
38
Secondary Memory
Nonvolatile Auxiliary memory Used to store program and data files
39
Disk Cache
A portion of main memory used as a buffer to temporarily to hold data for the disk Disk writes are clustered Some data written out may be referenced again. The data are retrieved rapidly from the software cache instead of slowly from disk
40
Cache Memory
Invisible to operating system Increase the speed of memory Processor speed is faster than memory speed Exploit the principle of locality
41
Cache Memory
42
Cache Memory
Contains a copy of a portion of main memory Processor first checks cache If not found in cache, the block of memory containing the needed information is moved to the cache and delivered to the processor
43
Cache/Main Memory System

Line Number Tag 0 1 2 Block Memory address 0 1 2 3 Block (K words)
C-1
Block Length (K Words)
(a) Cache
Block 2n - 1
Word Length
(b) Main memory
Figure 1.17 Cache/Main-Memory Structure
Cache Read Operation
45
Cache Design
Cache size
Small caches have a significant impact on performance
Block size
The unit of data exchanged between cache and main memory Larger block size more hits until probability of using newly fetched data becomes less than the probability of reusing data that have to be moved out of cache
46
Cache Design
Mapping function
Determines which cache location the block will occupy
Replacement algorithm
Determines which block to replace Least-Recently-Used (LRU) algorithm
47
Cache Design
Write policy
When the memory write operation takes place Can occur every time block is updated Can occur only when block is replaced
Minimizes memory write operations Leaves main memory in an obsolete state
48
Programmed I/O
I/O module performs the action, not the processor Sets appropriate bits in the I/O status register No interrupts occur Processor checks status until operation is complete
49
Interrupt-Driven I/O
Processor is interrupted when I/O module ready to exchange data Processor saves context of program executing and begins executing interrupt-handler No needless waiting Consumes a lot of processor time because every word read or written passes through the processor
50
Direct Memory Access

Transfers a block of data directly to or from memory An interrupt is sent when the transfer is complete Processor continues with other work
51

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Computer System Overview

Memory buffer register (MBR)

I/O address register I/O buffer register

MAR MBR I/O AR

Exe cution unit

PC IR MAR MBR I/O AR I/O BR

Figure 1.1 Computer Components: Top-Level View

Control and status registers

Control and Status Registers

Instruction Register (IR)

Program Status Word (PSW)

Control and Status Registers

Processor executes each instruction

Instruction Fetch and Execute

Characteristics of a Hypothetical Machine

Example of Program Execution

Direct Memory Access (DMA)

Program Flow of Control Without Interrupts

Program Flow of Control With Interrupts, Short I/O Wait

Interrupt Handler 5 END

WRITE (b) Interrupts; short I/O wait

Program Flow of Control With Interrupts; Long I/O Wait

Timing Diagram Based on Short I/O Wait

Timing Diagram Based on Short I/O Wait

Simple Interrupt Processing

Changes in Memory and Registers for an Interrupt

Changes in Memory and Registers for an Interrupt

Going Down the Hierarchy

Cache/Main Memory System

(b) Main memory

Figure 1.17 Cache/Main-Memory Structure

Cache Read Operation

Direct Memory Access

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