Intel Microprocessor
Intel Microprocessor
Intel Microprocessor
Features
It is a 16-bit p. 8086 has a 20 bit address bus can access up to 220 memory locations (1 MB). It has multiplexed address and data bus AD0- AD15 and A16 A19. It requires +5V power supply. A 40 pin dual in line package.
It can prefetches up to 6 instruction bytes from memory and queues them in order to speed up instruction execution. Address ranges from 00000H to FFFFFH
Memory is byte addressable - Every byte has a separate address.
Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. This results in efficient use of the system bus and system performance. BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder.
EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register.
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These pre-fetching instructions are held in its FIFO queue. With its 16 bit data bus, the BIU fetches two instruction bytes in a single memory cycle. After a byte is loaded at the input end of the queue, it automatically shifts up through the FIFO to the empty location nearest the output. The EU accesses the queue from the output end. It reads one instruction byte after the other from the output of the queue.
The intervals of no bus activity, which may occur between bus cycles are known as Idle state.
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yes
Data Update Take 2nd byte from Q as queue opcode, decode 2nd byte opcode Is it Single byte?
Opcode
Opcode queue
Execute it with data bytes decoded by the decoder Repeat the same procedure for successive contents of Q
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Segmented Memory
The memory in an 8086/88 based system is organized as segmented memory. The CPU 8086 is able to address 1Mbyte of memory. The Complete physically available memory may be divided into a number of logical segments.
FFFFF 00000
Physical Memory
Code segment (64KB) Data segment (64KB) Extra segment (64KB) Stack segment (64KB)
1 MB
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The size of each segment is 64 KB A segment is an area that begins at any location which is divisible by 16. A segment may be located any where in the memory Each of these segments can be used for a specific function.
Code segment is used for storing the instructions. The stack segment is used as a stack and it is used to store the return addresses. The data and extra segments are used for storing data byte.
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The 4 segments are Code, Data, Extra and Stack segments. A Segment is a 64kbyte block of memory. The 16 bit contents of the segment registers in the BIU actually point to the starting location of a particular segment. Segments may be overlapped or non-overlapped
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Segment registers
In 8086/88 the processors have 4 segments registers
Code Segment register (CS), Data Segment register (DS), Extra Segment register (ES) and Stack Segment (SS) register. All are 16 bit registers.
Each of the Segment registers store the upper 16 bit address of the starting address of the corresponding segments.
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To form a 20bit address of the next instruction, the 16 bit address of the IP is added (by the address summing block) to the address contained in the CS , which has been shifted four bits to the left.
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Code segment
34BA0
Inserting a hexadecimal 0H (0000B) with the CSR or shifting the CSR four binary digits left
8AB4 (offset)
3D645
Example For Address Calculation (segment: offset) If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data?
0000
Required Address
0001
EXECUTION UNIT
Decodes instructions fetched by the BIU Generate control signals, Executes instructions. The main parts are: Control Circuitry Instruction decoder ALU
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AH
AX BX CX DX
AL BL CL DL SP
Accumulator Base Count Data Stack Pointer Base Pointer Source Index Destination Index
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BH CH DH
Pointer
BP
SI
Index
DI
Register
AX AL AH BX CX CL DX
Purpose
Word multiply, word divide, word I /O Byte multiply, byte divide, byte I/O, decimal arithmetic Byte multiply, byte divide Store address information String operation, loops Variable shift and rotate Word multiply, word divide, indirect I/O
(Used to hold I/O address during I/O instructions. If the result is more than 16-bits, the lower order 16-bits are stored in accumulator and higher order 22 16-bits are stored in DX register)
Pointer And Index Registers used to keep offset addresses. Used in various forms of memory addressing.
In the case of SP and BP the default reference to form a physical address is the Stack Segment (SSwill be discussed under the BIU) The index registers (SI & DI) and the BX generally default to the Data segment register (DS).
SP: Stack pointer Used with SS to access the stack segment BP: Base Pointer Primarily used to access data on the stack 23 Can be used to access data in other segments
SI: Source Index register is required for some string operations When string operations are performed, the SI register points to memory locations in the data segment which is addressed by the DS register. Thus, SI is associated with the DS in string operations. DI: Destination Index register is also required for some string operations. When string operations are performed, the DI register points to memory locations in the data segment which is addressed by the ES register. Thus, DI is associated with the ES in string operations.
The SI and the DI registers may also be used to access data stored in arrays 24
AF U
Auxiliary
PF U
CF
Carry
Parity
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U - Unused
Flag
Carry (CF)
Purpose
Holds the carry after addition or the borrow after subtraction. Also indicates some error conditions, as dictated by some programs and procedures . PF=0;odd parity, PF=1;even parity.
Parity (PF)
Auxiliary (AF) Holds the carry (half carry) after addition or borrow after subtraction between bit positions 3 and 4 of the result (for example, in BCD addition or subtraction.) Zero (ZF) Shows the result of the arithmetic or logic operation. Z=1; result is zero. Z=0; The result is 0
Sign (SF)
Holds the sign of the result after an arithmetic/logic instruction 26 execution. S=1; negative, S=0
Flag
Trap (TF)
Purpose
A control flag. Enables the trapping through an on-chip debugging feature. A control flag. Controls the operation of the INTR (interrupt request) I=0; INTR pin disabled. I=1; INTR pin enabled. A control flag. It selects either the increment or decrement mode for DI and /or SI registers during the string instructions. Overflow occurs when signed numbers are added or subtracted. An overflow indicates the result has exceeded the capacity of the Machine
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Interrupt (IF)
Direction (DF)
Overflow (OF)