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About: Quasi-delay-insensitive circuit

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In digital logic design, an asynchronous circuit is quasi delay-insensitive (QDI) when it operates correctly, independent of gate and wire delay with the weakest exception necessary to be turing-complete.

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  • In digital logic design, an asynchronous circuit is quasi delay-insensitive (QDI) when it operates correctly, independent of gate and wire delay with the weakest exception necessary to be turing-complete. (en)
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  • December 2021 (en)
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  • timing (en)
  • verification (en)
  • layout (en)
  • chips (en)
  • sizing (en)
  • synthesis (en)
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  • that the article uses very unusual style of citation: it excessively relies on the html-tag attribute . It would probably be better to use a numeric style. Please discuss. (en)
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  • In digital logic design, an asynchronous circuit is quasi delay-insensitive (QDI) when it operates correctly, independent of gate and wire delay with the weakest exception necessary to be turing-complete. (en)
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  • Quasi-delay-insensitive circuit (en)
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