Article

FinFETs for nanoscale CMOS digital integrated circuits

Author:

Tsu-Jae KingAuthors Info & Claims

ICCAD '05: Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

Pages 207 - 210

Published: 31 May 2005 Publication History

Abstract

Suppression of leakage current and reduction in device-to-device variability are key challenges for sub-45nm CMOS technologies. Nonclassical transistor structures such as the FinFET are likely necessary to meet transistor performance requirements in the sub-20nm gate length regime. This paper presents an overview of FinFET technology and describes how it can be used to improve the performance, standby power consumption, and variability in nanoscale-CMOS digital ICs.

References

[1]

{1} D. J. Frank et al., Proc. IEEE, Vol. 89, p. 259 (2001).

[2]

{2} A. Hokazono et al., IEDM Tech. Dig., p. 639 (2002).

[3]

{3} D. Antoniadis, Symp. VLSI Tech. Dig., p. 2 (2002).

[4]

{4} L. Chang et al., Proc. IEEE., Vol. 91, No. 11, p. 1860 (2003).

[5]

{5} C. Wann et al., IEEE Trans. Electron Devices, Vol. 43, p. 1742 (1996).

[6]

{6} L. Chang et al., IEDM Tech. Dig., p. 99 (2001).

[7]

{7} N. Lindert et al., IEEE Electron Device Letters, Vol. 22, p. 487 (2001).

[8]

{8} J. Kedzierski et al., IEDM Tech. Dig., p. 437 (2001).

[9]

{9} F.-L. Yang et al., Symp. VLSI Tech. Dig., p. 104 (2002).

[10]

{10} B. Yu et al., IEDM Tech. Dig., p. 251 (2002).

[11]

{11} F.-L. Yang et al., Symp. VLSI Tech. Dig., p. 196 (2004).

[12]

{12} A. R. Brown et al., IEEE Trans. Nanotechnology, Vol. 1, p. 195 (2002).

Digital Library

[13]

{13} N. Lindert et al., 59th Device Research Conf. Digest, p. 26 (2001).

[14]

{14} Y.-K. Choi et al., IEEE Trans. Electron Devices, p. 436 (2002).

[15]

{15} T. Sato et al., Physical Review B, Vol. 4, p. 1950 (1971).

[16]

{16} D. Hisamoto et al., IEDM Tech. Dig., p. 1032 (1998).

[17]

{17} Semiconductor Industry Association Int'l Technology Roadmap for Semiconductors, 2003 Edition, http://public.itrs.net/Files/2003ITRS/Home2003.htm

[18]

{18} F. Ootsuka et al., IEDM Tech. Dig., p. 575 (2000).

[19]

{19} K. Ota et al., IEDM Tech. Dig., p. 27 (2002).

[20]

{20} T. Ghani et al., IEDM Tech. Dig., p. 978 (2003).

[21]

{21} C.-H. Ge et al., IEDM Tech. Dig., p. 73 (2003).

[22]

{22} M. Yang et al., IEDM Tech. Dig., p. 453 (2003).

[23]

{23} P. Verheyen et al., Symp. VLSI Tech. Dig. (2005).

[24]

{24} K. Shin et al., Device Research Conf. Dig., p. 201 (2005).

[25]

{25} H. Kam et al., Proc. Silicon Nanoelectronics Workshop, p. 9 (2004).

[26]

{26} N. Lindert et al., IEEE Int'l SOI Conference, p. 111 (2001).

[27]

{27} L. Mathew et al., IEEE Int'l Conf. on Integrated Circuit Design and Technology, p. 97 (2004).

[28]

{28} Z. Guo et al., Proc. ISLPED (2005).

Cited By

Turi MDelgado-Frias J(2017)Full-VDD and near-threshold performance of 8T FinFET SRAM cellsIntegration, the VLSI Journal10.5555/3063717.306372357:C(169-183)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.5555/3063717.3063723
Li TAmbrose JRagel RParameswaran S(2016)Processor Design for Soft ErrorsACM Computing Surveys10.1145/299635749:3(1-44)Online publication date: 8-Nov-2016
https://dl.acm.org/doi/10.1145/2996357
Musiiwa PAkashe S(2016)Design of Low Power Memristor Non-Volatile Dram Cell with Footer SwitchProceedings of the Second International Conference on Information and Communication Technology for Competitive Strategies10.1145/2905055.2905302(1-6)Online publication date: 4-Mar-2016
https://dl.acm.org/doi/10.1145/2905055.2905302
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FinFETs for nanoscale CMOS digital integrated circuits
1. Hardware
  1. Electronic design automation
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  1. Network types
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cover image ACM Conferences

ICCAD '05: Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

May 2005

1032 pages

ISBN:078039254X

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SIGDA: ACM Special Interest Group on Design Automation

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IEEE Computer Society

United States

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Published: 31 May 2005

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Turi MDelgado-Frias J(2017)Full-VDD and near-threshold performance of 8T FinFET SRAM cellsIntegration, the VLSI Journal10.5555/3063717.306372357:C(169-183)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.5555/3063717.3063723
Li TAmbrose JRagel RParameswaran S(2016)Processor Design for Soft ErrorsACM Computing Surveys10.1145/299635749:3(1-44)Online publication date: 8-Nov-2016
https://dl.acm.org/doi/10.1145/2996357
Musiiwa PAkashe S(2016)Design of Low Power Memristor Non-Volatile Dram Cell with Footer SwitchProceedings of the Second International Conference on Information and Communication Technology for Competitive Strategies10.1145/2905055.2905302(1-6)Online publication date: 4-Mar-2016
https://dl.acm.org/doi/10.1145/2905055.2905302
Tahrim ‘Chin HLim CTan M(2015)Design and performance analysis of 1-bit FinFET full adder cells for subthreshold region at 16 nm process technologyJournal of Nanomaterials10.1155/2015/72617516:1(175-175)Online publication date: 1-Jan-2015
https://dl.acm.org/doi/10.1155/2015/726175
Abusultan MKhatri SCavallaro JZhang TJones ALi H(2014)A comparison of FinFET based FPGA LUT designsProceedings of the 24th edition of the great lakes symposium on VLSI10.1145/2591513.2591596(353-358)Online publication date: 20-May-2014
https://dl.acm.org/doi/10.1145/2591513.2591596
Zhang ZTuri MDelgado-Frias JBrunvard EStevens KCavallaro JZhang T(2012)SRAM leakage in CMOS, FinFET and CNTFET technologiesProceedings of the great lakes symposium on VLSI10.1145/2206781.2206846(267-270)Online publication date: 3-May-2012
https://dl.acm.org/doi/10.1145/2206781.2206846
Mishra PMuttreja AJha N(2009)Low-power FinFET circuit synthesis using multiple supply and threshold voltagesACM Journal on Emerging Technologies in Computing Systems10.1145/1543438.15434405:2(1-23)Online publication date: 16-Jul-2009
https://dl.acm.org/doi/10.1145/1543438.1543440

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