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Linear time fault simulation algorithm using a content addressable memory

Published: 01 November 1992 Publication History
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References

[1]
M. A. Breuer and A. D. Friedman: Diagnosis Reliable Design of Digital Systems. Computer Science Press (1976).
[2]
D. Harel and B. Krishnamurthy: "is There Hope for Linear Time Fault Simulation ?", Proc. FTCS- 17, pp. 28-33 (Jun. 1987).
[3]
N. Ishiura, M. Ito, and S. Yajima: "Dynamic Two-Dimensional Parallel Simulation Technique for High-Speed Fault Simulation on a Vector Processor", IEEE Trans. CAD, vol. CAD-9, no. 8, pp. 868-875 (Aug. 1990).
[4]
T. Ogura, J. Yamada, S. Yamada and M. Tanno: "A 20K-bit Associative Memory LSI for Artificial Intelligence Machines", IEEE Journal of Solid-State Circuits, vol. 24, no. 4, pp. 1014-1020 (Aug. 1989).
[5]
H. Yasuura, T. Tsujimoto and K. Tamaru: "Parallel exhaustive search for several NP-cornplete problems using content addressable memolries", Proc. ISCAS'88, pp. 333-336 (Jun. 1988).

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cover image ACM Conferences
EURO-DAC '92: Proceedings of the conference on European design automation
November 1992
765 pages
ISBN:0818627808

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IEEE Computer Society Press

Washington, DC, United States

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Published: 01 November 1992

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