Proceedings of the conference on European design automation

EURO-DAC '92: Proceedings of the conference on European design automation

November 1992

1992 Proceeding

Chairman:
G. Musgrave

Publisher:

IEEE Computer Society Press
Washington
DC
United States

Conference:

Congress Centrum Hamburg, Hamburg Germany

ISBN:

978-0-8186-2780-4

Published:

01 November 1992

Sponsors:

SIGDA, IEEE-CS

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62nd ACM/IEEE Design Automation Conference

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Citation count

228

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175

Downloads (12 months)

1,556

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19,284

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EURO-DAC '92: Proceedings of the conference on European design automation

1992

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Path breaker: a tool for the optimal design of speed independent asynchronous controllers

Yogesh Mishra,
S. D. Sherlekar,
G. Venkatesh

Pages 2–8

- 0
- 78
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Total Downloads78
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Asynchronous state machine synthesis using data driven clocks

Farhad Aghadasi

Pages 9–14

- 0
- 251
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Total Downloads251
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Design of delay insensitive circuits using multi-ring structures

Jens Sparsø,
Jørgen Staunstrup,
Michael Dantzer-Sørensen

Pages 15–20

- 6
- 250
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Total Downloads250
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DESB, a functional abstractor for CMOS VLSI circuits

M. Laurentin,
A. Greiner,
R. Marbot

Pages 22–27

- 2
- 140
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Total Citations2
Total Downloads140
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Automatic import of custom designs into a cell-based environment using switch-level analysis and circuit simulation

Ronald Stewart,
Véronique Anjubault,
Philippe Garcin,
Jacques Benkoski

Pages 28–31

- 0
- 91
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Total Downloads91
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Communication based logic partitioning

Mark Beardslee,
Bill Lin,
Alberto Sangiovanni-Vincentelli

Pages 32–37

- 5
- 155
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Parallel algorithms for slicing based final placement

Henning Spruth,
Georg Sigl

Pages 40–45

- 0
- 101
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Wolverines: standard cell placement on a network of workstations

S. Mohan,
P. Mazumder

Pages 46–51

- 0
- 101
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A genetic algorithm for macro cell placement

Henrik Esbensen

Pages 52–57

- 2
- 345
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Total Downloads345
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Timing models for high-level synthesis

Viraphol Chaiyakul,
Allen C.-H. Wu,
Daniel D. Gajski

Pages 60–65

- 8
- 191
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Total Citations8
Total Downloads191
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System clock estimation based on clock slack minimization

Sanjiv Narayan,
Daniel D. Gajski

Pages 66–71

- 14
- 237
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Total Downloads237
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Combined topological and functionality based delay estimation using a layout-driven approach for high level applications

Champaka Ramachandran,
Fadi J. Kurdahi

Pages 72–78

- 5
- 215
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Total Downloads215
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Correctness verification of concurrent controller specifications

M. T. L. Schaefer,
W. U. Klein

Pages 80–85

- 0
- 108
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Total Downloads108
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Design verification considering manufacturing tolerances by using worst-caste distances

Helmut E. Graeb,
Claudia U. Wieser,
Kurt J. Antreich

Pages 86–91

- 2
- 122
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Total Downloads122
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State machine abstraction from circuit layouts using BDD's: applications in verification and synthesis

Timothy Kam,
P. A. Subrahmanyam

Pages 92–97

- 0
- 211
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Verification of digital circuits based on formal semantics of a hardware description language

Matthias Mutz

Pages 98–103

- 0
- 137
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An integer programming approach to instruction implementation method selection problem

Masaharu Imai,
Jun Sato,
Alauddin Alomary,
Nobuyuki Hikichi

Pages 106–111

- 7
- 152
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Total Downloads152
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Flexible controlpath microarchitecture synthesis based on artificial intelligence

A. J. W. M. ten Berg

Pages 112–117

- 0
- 113
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Total Downloads113
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Performance-driven interconnection optimization for microarchitecture synthesis

Yi-Min Jiang,
Tsing-Fa Lee,
Ting-Ting Hwang,
Yaun-Long Lin

Pages 118–123

- 0
- 76
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Transient simulation of lossy coupled transmission lines

Shen Lin,
Ernest S. Kuh

Pages 126–131

- 0
- 147
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Total Downloads147
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The exact solution of timing verification

Edgar Bolender,
Hans Martin Lipp

Pages 132–137

- 0
- 92
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DynaTAPP: dynamic timing analysis with partial path activation in sequential circuits

Prathima Agrawal,
Vishwani D. Agrawal,
Sharad C. Seth

Pages 138–141

- 1
- 91
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Total Citations1
Total Downloads91
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Delay macromodels for the timing analysis of GaAs DCFL

A. I. Kayssi,
K. A. Sakallah

Pages 142–145

- 0
- 124
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An efficient methodology for symbolic compaction of analog IC's with multiple symmetry constraints

Eric Felt,
Edoardo Charbon,
Enrico Malavasi,
Alberto Sangiovanni-Vincentelli

Pages 148–153

- 3
- 138
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Total Downloads138
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PERFLEX: a performance driven module generator

Soohong Kim,
Robert M. Owens,
Mary J. Irwin

Pages 154–159

- 0
- 113
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P.SIZE: a sizing aid for optimized designs

N. Azemard,
V. Bonzom,
D. Auvergne

Pages 160–165

- 0
- 113
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Total Downloads113
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Boolean matching in logic synthesis

Hamid Savoj,
Mário J. Silva,
Robert K. Brayton,
Alberto Sangiovanni-Vincentelli

Pages 168–174

- 8
- 306
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Total Downloads306
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ALU synthesis from HDL descriptions to optimized multi-level logic

Frank Buijs

Pages 175–180

- 0
- 228
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Calculation of the Rademacher-Walsh spectrum from a reduced representation of Boolean functions

B. J. Falkowski,
I. Schäfer,
M. A. Perkowski

Pages 181–186

- 1
- 177
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High-level synthesis in a rapid-prototype environment for mechatronic systems

N. Wehn,
H.-J. Herpel,
T. Hollstein,
P. Poechmueller,
M. Glesner

Pages 188–193

- 0
- 141
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Contributors

Gerry Musgrave
Brunel University London
- Publication Years1992 - 1998
- Publication counts9
- Citation count7
- Available for Download2
- Downloads (cumulative)370
- Downloads (12 months)59
- Downloads (6 weeks)5
- Average Downloads per Article185
- Average Citation per Article1
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Index Terms

Proceedings of the conference on European design automation
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
  2. Integrated circuits
    1. Logic circuits

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