The exact solution of timing verification
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J. Benkoski, E. Vanden Meersch, L. Claesen, H. De Man,"Efficient Algorithms for Solving the False Path Problem in Timing Verification," IEEE lnt'l. Conf. on CAD, 1987, pp. 44--47
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J. Benkoski, E. Vanden Meersch, L. Claesen, H. De Man, "Timing Verification Using Statically Sensitizable Paths," IEEE Trans. on CAD, vol. q (1990), no. i0, pp. 1073-1084
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D. Bochmann, B. Steinbach, Logikentwurf mit XBOOLE (Logic Design with XBOOLE), Verlag Technik, Berlin, 1991 (in German)
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E. Bolender, H.M. Lipp,"Timing Verification: ANew Understanding of False Paths," Proc. of the European Conf. on Design Autom. 1992, pp. 383-387
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D. Brand, V.S. lyengar, "timing Analysis Using Functional Analysis," IEEE Trans. on Comp., vol. 37 (1988), no. 10, pp. 1309-1314
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D.H.C Du, S.H.C. Yen, S. Ghanta,"On the General False Path Problem in Timing Analysis," Proc. 26th ACM/IEEE Design Autom. Conf., 1989, pp. 555-560
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EC. McGeer, R.K. Brayton, "Efficient Algorithms for Computing the Longest Viable Path in a Combinational Netwo&," Proc. 26th ACM/IEEE Design Autom. Conf., 1989, pp. 561-567
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R.B. Hitchcock, G.L. Smith, D. Cheng, "Timing Analysis of Computer Hardware," IBM J. of Research & Development, vol. 26 (1982), no. 1, pp. 100-105
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K. Keutzer, S. Malik, A. Saldanha,"ls Redundancy Necessary to Reduce Delay?," IEEE Transactions on CAD, vol. 10 (1991), no. 4, pp. 427-435
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C.J. Lin, S.M. Reddy, "On Delay Fault Testing in Logical C'ircults," IEEE Int'l. Conf. on CAD, 1986, pp 148-151
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Index Terms
- The exact solution of timing verification
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Published: 01 November 1992
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