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Energy- and endurance-aware design of phase change memory caches

Published: 08 March 2010 Publication History

Abstract

Phase change memory (PCM) is one of the most promising technology among emerging non-volatile random access memory technologies. Implementing a cache memory using PCM provides many benefits such as high density, non-volatility, low leakage power, and high immunity to soft error. However, its disadvantages such as high write latency, high write energy, and limited write endurance prevent it from being used as a drop-in replacement of an SRAM cache. In this paper, we study a set of techniques to design an energy- and endurance-aware PCM cache. We also modeled the timing, energy, endurance, and area of PCM caches and integrated them into a PCM cache simulator to evaluate the techniques. Experiments show that our PCM cache design can achieve 8% of energy saving and 3.8 years of lifetime compared with a baseline PCM cache having less than a hour of lifetime.

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  • (2019)Sleepy-LRUThe Journal of Supercomputing10.1007/s11227-019-02758-075:7(3945-3974)Online publication date: 1-Jul-2019
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cover image ACM Conferences
DATE '10: Proceedings of the Conference on Design, Automation and Test in Europe
March 2010
1868 pages
ISBN:9783981080162

Sponsors

  • EDAA: European Design Automation Association
  • ECSI
  • EDAC: Electronic Design Automation Consortium
  • SIGDA: ACM Special Interest Group on Design Automation
  • The IEEE Computer Society TTTC
  • The IEEE Computer Society DATC
  • The Russian Academy of Sciences: The Russian Academy of Sciences

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European Design and Automation Association

Leuven, Belgium

Publication History

Published: 08 March 2010

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DATE '10
Sponsor:
  • EDAA
  • EDAC
  • SIGDA
  • The Russian Academy of Sciences
DATE '10: Design, Automation and Test in Europe
March 8 - 12, 2010
Germany, Dresden

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

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  • (2019)Software wear management for persistent memoriesProceedings of the 17th USENIX Conference on File and Storage Technologies10.5555/3323298.3323303(45-63)Online publication date: 25-Feb-2019
  • (2019)Reducing Writebacks Through In-Cache DisplacementACM Transactions on Design Automation of Electronic Systems10.1145/328918724:2(1-21)Online publication date: 10-Jan-2019
  • (2019)Sleepy-LRUThe Journal of Supercomputing10.1007/s11227-019-02758-075:7(3945-3974)Online publication date: 1-Jul-2019
  • (2018)HeteroOSACM SIGOPS Operating Systems Review10.1145/3273982.327398552:1(13-26)Online publication date: 28-Aug-2018
  • (2018)UnistorFSACM Transactions on Storage10.1145/317791814:1(1-22)Online publication date: 26-Feb-2018
  • (2017)HeteroOSACM SIGARCH Computer Architecture News10.1145/3140659.308024545:2(521-534)Online publication date: 24-Jun-2017
  • (2017)Ouroboros Wear Leveling for NVRAM Using Hierarchical Block MigrationACM Transactions on Storage10.1145/313953013:4(1-31)Online publication date: 14-Nov-2017
  • (2017)HeteroOSProceedings of the 44th Annual International Symposium on Computer Architecture10.1145/3079856.3080245(521-534)Online publication date: 24-Jun-2017
  • (2017)Durable Address Translation in PCM-Based Flash Storage SystemsIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2016.258605928:2(475-490)Online publication date: 1-Feb-2017
  • (2017)Optimization of Data Allocation on CMP Embedded System with Data MigrationInternational Journal of Parallel Programming10.1007/s10766-016-0436-345:4(965-981)Online publication date: 1-Aug-2017
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