Cited By
View all- Gaudesi MPomeranz IReorda MSquillero G(2017)New Techniques to Reduce the Execution Time of Functional Test ProgramsIEEE Transactions on Computers10.1109/TC.2016.264366366:7(1268-1273)Online publication date: 7-Jun-2017
Memory testing with a RISC microcontroller
Abstract
Many systems are based on embedded microcontrollers. Applications demand for production and Power-On testing, including memory testing. Because low-end microcontrollers may not have memory BIST, the CPU will be the only resource to perform at least the Power-On tests. This paper shows the problems, solutions and limitations of CPU-based at-speed memory testing, illustrated with examples from the ATMEL RISC microcontroller.
References
[1]
http://www.atmel.com/dyn/products/product_card.asp?family_id=607&f amily_name=AVR+8%2DBit+RISC+&part_id=2002#DataSheets
[2]
http://www.atmel.com/dyn/resources/prod_documents/0841s.pdf
[3]
X. Du, N. Mukherjee and W-T. Cheng, 'Full-Speed Field-Programmable Memory BIST Architecture", IEEE Int. Test Conf. paper 45.3, 2005.
[4]
T. Powell, et al., "Chasing Subtle Embedded RAM Defects for Nanometer Technologies", IEEE Int. Test Conf. paper 33.4, 2005.
[5]
T. Powell, et al., "BIST for Deep Submicron ASIC Memories with High Performance Application", IEEE Int. Test Conf., pp. 386--392, 2003.
[6]
Z. Conroy, et al. "A Practical Perspective on Reducing ASIC NTFs", IEEE Int. Test Conf., paper 14.2, 2005.
[7]
J. B. Khare, et al., "Embedded Memory Field returns-Trials and Tribulations", IEEE Int. Test Conf., Paper 26.3, 2006.
[8]
A. J. van de Goor, Testing Semiconductor Memories, Theory and Practice. ComTex Publishing, Gouda, The Netherlands., 1998. [email protected].
[9]
L. Dilillo, et. al, "ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions", Journal of Electronic Testing-Theory & Applications, Vol. 22, N°° 3, pp. 287--296, June 2006.
[10]
A. J. van de Goor, S. Hamdioui, and G. N. Gajdadjiev, "Memory Testing with a CISC Microcontroller", Submitted to DDECS conf., Vienna 2010.
[11]
A. J. van de Goor and I. Schanstra, "Address and Data Scrambling: Causes and Impact on Memory Tests", Proc. of IEEE Int. Workshop on Electronic Design, Test and Applications, pp. 128--136, 2002.
[12]
I. Schanstra, I. and A. J. van de Goor, "Logical and Topological Testing of Scrambled SRAMs", IEEE Latin-American Test Workshop, pp. 66--71, 2003
[13]
R. C. Aitken, "A Modular Wrapper Enabling High Speed BIST and Repair for Small Wide Memories", Int. Test Conf., pp. 997--1005, 2004.
[14]
A. J. van de Goor and A. Paalvast, "Industrial Evaluation of DRAM SIMM Tests", IEEE Int. Test Conf., pp. 426--435, 2000.
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Information & Contributors
Information
Published In
March 2010
1868 pages
ISBN:9783981080162
- General Chairs:
- Giovanni De Micheli,
- Bashir Al-Hashimi,
- Program Chairs:
- Wolfgang Mueller,
- Enrico Macii
Sponsors
- EDAA: European Design Automation Association
- ECSI
- EDAC: Electronic Design Automation Consortium
- SIGDA: ACM Special Interest Group on Design Automation
- The IEEE Computer Society TTTC
- The IEEE Computer Society DATC
- The Russian Academy of Sciences: The Russian Academy of Sciences
Publisher
European Design and Automation Association
Leuven, Belgium
Publication History
Published: 08 March 2010
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Conference
DATE '10
Sponsor:
- EDAA
- EDAC
- SIGDA
- The Russian Academy of Sciences
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Overall Acceptance Rate 518 of 1,794 submissions, 29%
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Cited By
View all- Gaudesi MPomeranz IReorda MSquillero G(2017)New Techniques to Reduce the Execution Time of Functional Test ProgramsIEEE Transactions on Computers10.1109/TC.2016.264366366:7(1268-1273)Online publication date: 7-Jun-2017
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