Cited By
View all- Ozturk OAkturk IKadayif ITosun S(2015)Energy reduction in 3D NoCs through communication optimizationComputing10.1007/s00607-013-0378-197:6(593-609)Online publication date: 1-Jun-2015
Design of networks on chips for 3D ICs
Pages 167 - 168
Abstract
Three-dimensional integrated circuits, where multiple silicon layers are stacked vertically have emerged recently. The 3D ICs have smaller form factor, shorter and efficient use of wires and allow integration of diverse technologies in the same device. The use of Networks on Chips (NoCs) to connect components in a 3D chip is a necessity. In this short paper, we present an outline on designing application-specific NoCs for 3D ICs.
References
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P. Guerrier, A. Greiner, "A generic architecture for on-chip packet switched interconnections", Proc. DATE, pp. 250--256, March 2000.
[2]
G. De Micheli, L. Benini, "Networks on Chips: Technology and Tools", Morgan Kaufmann, First Edition, July, 2006.
[3]
K. Banerjee et al., "3-D ICs: A Novel Chip Design for Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration", Proc. of the IEEE, vol. 89(5), pp. 602, 2001.
[4]
C. Seiculescu, S. Murali, L. Benini, and G. De Micheli, "SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3D Systems on Chip", DATE 2009, pages 9--14, 2009.
- Design of networks on chips for 3D ICs
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- TICD: TICD
- SIGDA: ACM Special Interest Group on Design Automation
- IEEE CAS
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IEEE Press
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Published: 18 January 2010
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Cited By
View all- Ozturk OAkturk IKadayif ITosun S(2015)Energy reduction in 3D NoCs through communication optimizationComputing10.1007/s00607-013-0378-197:6(593-609)Online publication date: 1-Jun-2015
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