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SunFloor 3D: a tool for networks on chip topology synthesis for 3D systems on chips

Published: 20 April 2009 Publication History

Abstract

Three-dimensional integrated circuits are a promising approach to address the integration challenges faced by current Systems on Chips (SoCs). Designing an efficient Network on Chip (NoC) interconnect for a 3D SoC that not only meets the application performance constraints, but also the constraints imposed by the 3D technology, is a significant challenge. In this work we present a design tool, SunFloor 3D, to synthesize application-specific 3D NoCs. The proposed tool determines the best NoC topology for the application, finds paths for the communication flows, assigns the network components on to the 3D layers and performs a placement of them in each layer. We perform experiments on several SoC benchmarks and present a comparative study between 3D and 2D NoC designs. Our studies show large improvements in interconnect power consumption (average of 38%) and delay (average of 13%) for the 3D NoC when compared to the corresponding 2D implementation. Our studies also show that the synthesized topologies result in large power (average of 54%) and delay savings (average of 21%) when compared to standard topologies.

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  • (2019)Impact of Electrostatic Coupling on Monolithic 3D-enabled Network on ChipACM Transactions on Design Automation of Electronic Systems10.1145/335715824:6(1-22)Online publication date: 17-Sep-2019
  • (2018)Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-ChipACM Transactions on Design Automation of Electronic Systems10.1145/322304623:5(1-25)Online publication date: 22-Aug-2018
  • (2018)Design Space Exploration of 3D Network-on-ChipACM Journal on Emerging Technologies in Computing Systems10.1145/319756714:3(1-26)Online publication date: 23-Oct-2018
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  1. SunFloor 3D: a tool for networks on chip topology synthesis for 3D systems on chips

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    Information

    Published In

    cover image ACM Conferences
    DATE '09: Proceedings of the Conference on Design, Automation and Test in Europe
    April 2009
    1776 pages
    ISBN:9783981080155

    Sponsors

    • EDAA: European Design Automation Association
    • ECSI
    • EDAC: Electronic Design Automation Consortium
    • SIGDA: ACM Special Interest Group on Design Automation
    • The IEEE Computer Society TTTC
    • The IEEE Computer Society DATC
    • The Russian Academy of Sciences: The Russian Academy of Sciences

    Publisher

    European Design and Automation Association

    Leuven, Belgium

    Publication History

    Published: 20 April 2009

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    Author Tags

    1. 3D ICs
    2. networks on chip (NoC)
    3. placement
    4. synthesis
    5. topology

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    • Research-article

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    DATE '09
    Sponsor:
    • EDAA
    • EDAC
    • SIGDA
    • The Russian Academy of Sciences

    Acceptance Rates

    Overall Acceptance Rate 518 of 1,794 submissions, 29%

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    DATE '25
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    March 31 - April 2, 2025
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    Cited By

    View all
    • (2019)Impact of Electrostatic Coupling on Monolithic 3D-enabled Network on ChipACM Transactions on Design Automation of Electronic Systems10.1145/335715824:6(1-22)Online publication date: 17-Sep-2019
    • (2018)Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-ChipACM Transactions on Design Automation of Electronic Systems10.1145/322304623:5(1-25)Online publication date: 22-Aug-2018
    • (2018)Design Space Exploration of 3D Network-on-ChipACM Journal on Emerging Technologies in Computing Systems10.1145/319756714:3(1-26)Online publication date: 23-Oct-2018
    • (2016)Integrated Through-Silicon Via Placement and Application Mapping for 3D Mesh-Based NoC DesignACM Transactions on Embedded Computing Systems10.1145/296844616:1(1-25)Online publication date: 3-Nov-2016
    • (2016)Dynamic Resource Sharing for High-Performance 3-D Networks-on-ChipIEEE Computer Architecture Letters10.1109/LCA.2015.244853215:1(5-8)Online publication date: 1-Jan-2016
    • (2015)REDELFACM Journal on Emerging Technologies in Computing Systems10.1145/275156012:3(1-22)Online publication date: 21-Sep-2015
    • (2012)Optimized 3D Network-on-Chip Design Using Simulated AllocationACM Transactions on Design Automation of Electronic Systems10.1145/2159542.215954417:2(1-19)Online publication date: 1-Apr-2012
    • (2011)Chemical-mechanical polishing aware application-specific 3D NoC designProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132372(207-212)Online publication date: 7-Nov-2011
    • (2011)B2RACProceedings of the 4th International Workshop on Network on Chip Architectures10.1145/2076501.2076505(17-22)Online publication date: 4-Dec-2011
    • (2011)Exploring partitioning methods for 3D Networks-on-Chip utilizing adaptive routing modelProceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip10.1145/1999946.1999958(73-80)Online publication date: 1-May-2011
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