research-article

Integrated Through-Silicon Via Placement and Application Mapping for 3D Mesh-Based NoC Design

Authors:

Santanu Chattopadhyay,

Indranil SenguptaAuthors Info & Claims

ACM Transactions on Embedded Computing Systems (TECS), Volume 16, Issue 1

Article No.: 24, Pages 1 - 25

https://doi.org/10.1145/2968446

Published: 03 November 2016 Publication History

Abstract

This article proposes a solution to the integrated problem of Through-Silicon Via (TSV) placement and mapping of cores to the routers in a three-dimensional mesh-based Network-on-Chip (NoC) system. TSV geometry restricts their number in three-dimensional (3D) ICs. As a result, only about 25% of routers in a 3D NoC can possess vertical connections. Mapping plays an important role in evolving good system solutions in such a situation. TSVs have been placed with detailed consultation with the application mapping process. The integrated problem was first solved using the exact method of Integer Liner Programming (ILP). Next, a solution was obtained via a Particle Swarm Optimization (PSO) formulation. Several augmentations to the basic PSO strategy have been proposed to generate good-quality solutions. The results obtained are better than many of the contemporary approaches and close to the theoretical situation in which all routers are 3D in nature.

References

[1]

2010. Single-Chip Cloud Computer. http://techresearch.intel.com/UserFiles/en-us/File/SCC_Symposium_Mar162010_GML_final.pdf.

[2]

2010. The AMD opteron 6000 series platform. http://www.amd.com.

[3]

A. B. Ahmed and A. B. Abdallah. 2012. Low-overhead routing algorithm for 3d network-on-chip. In 3rd Int. Conf. on Networking and Computing (ICNC’12). 5--7.

Digital Library

[4]

S. Azampanah, A. Eskandari, A. Khademzadeh, and F. Karimi. 2013. Traffic-aware selection strategy for application-specific 3d NoC. Advances in Computer Science: An Intl. Journal 2, 5 (2013), 107--114.

[5]

M. Bahmani, A. Sheibanyrad, F. Petrot, F. Dubois, and P. Durante. 2012. A 3d-NoC router implementation exploiting vertically-partially-connected topologies. In Proc. of Computer Society Annual Symposium on VLSI (ISVLSI’12). 9--14.

Digital Library

[6]

L. Benini and G. De Micheli. 2002. Networks-on-chips: A new SoC paradigm. Computer 35, (2002), 70--78.

Digital Library

[7]

S. Chen and J. Montgomery. 2011. Selection strategies for initial positions and initial velocities in multi-optima particle swarms. In Proc. of the 13th Annual Conference on Genetic and Evolutionary Computation. 53--60.

Digital Library

[8]

C. L. Chou and R. Marculescu. 2008. Contention-aware application mapping for network-on-chip communication architectures. In Proc. of Int. Conference on Computer Design (ICCD’08). 164--169.

[9]

L. Congying, Z. Huanping, and Y. Xinfeng. 2011. Particle swarm optimization algorithm for quadratic assignment problem. In Proc. of IEEE Int. Conference Computer Science Networking Technology. 1728--1731.

[10]

Cplex. 2013. http://www.ibm.com/software/in/integration/optimization/cplex.

[11]

W. J. Dally and B. Towles. 2001. Route packets, not wires: On-chip interconnection networks. In Proc. of Design Automation Conf. (DAC’01). 683--689.

Digital Library

[12]

W. R. Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, A. M. Sule, M. Steer, and P. D. Franzon. 2005. Demystifying 3d ICs: The pros and cons of going vertical. IEEE Design Test 22 (2005), 498--510.

Digital Library

[13]

R. P. Dick, D. L. Rhodes, and W. Wolf. 1998. TGFF: Task graphs for free. In Proc. of Int. Workshop on Hardware/Software Codesign.

Digital Library

[14]

H. Ding, H. Gu, Y. Yang, and D. Fan. 2013. Traffic-aware selection strategy for application-specific 3d NoC. IEICE Electronics Express (2013), 1--6.

[15]

F. Dubois, A. Sheibanyrad, F. Petrot, and M. Bahmani. 2013. Elevator-first: A deadlock-free distributed routing algorithm for vertically partially connected 3d-NoCs. IEEE Transactions on Computers 62, 3 (2013), 609--615.

Digital Library

[16]

B. S. Feero and P. P. Pande. 2009. Networks-on-chip in a three dimensional environment: A performance evaluation. IEEE Transactions on Computers 58, 1 (2009), 32--45.

Digital Library

[17]

M. R. Garcy and D. S. Johson. 1979. Computers and Intractability: A Guide to the Theory of NP-Completeness. W. H. Freeman Publisher.

Digital Library

[18]

L. Guilan, Z. Hai, and S. Chunhe. 2008. Convergence analysis of a dynamic discrete PSO algorithm. In International Conference on Intelligent Networks and Intelligent Systems. 89--92.

Digital Library

[19]

A. R. Guner and M. Sevkli. 2008. A discrete particle swarm optimization algorithm for uncapacitated facility location problem. Journal of Artificial Evolution and Application 2008 (2008), 1--9.

[20]

P. K. Hamedani, S. Hessabi, H. Sarbazi-Azad, and N. E. Jerger. 2012. Exploration of temperature constraints for thermal aware mapping of 3d networks-on-chip. In Proc. of Euromicro Int. Conference on Parallel, Distributed and Network-Based Processing (PDP’12). 499--506.

Digital Library

[21]

R. Ho, K. W. Mai, and M. A. Horowitz. 2001. The future of wires. In Proc. of IEEE. 490--504.

[22]

Y. Hoskote, S. Vangal, A. Singh, N. Borkar, and S. Borkar. 2007. A 5-GHz mesh interconnect for a teraflops processor. IEEE Micro 27, 5 (2007), 51--61.

Digital Library

[23]

Y. J. Hwang, J. H. Lee, and T. H. Han. 2011. 3D network-on-chip system communication using minimum number of TSVs. In Proc. of ICT Convergence (ICTC’11). 517--522.

[24]

K. Jheng, C. Chao, H. Wang, and A. Wu. 2013. http://access.ee.ntu.edu.tw/noxim/index.html.

[25]

X. Jiang and T. Watanabe. 2010. An efficient 3d NoC synthesis by using genetic algorithms. In Proc. of IEEE Region 10 Conference (TENCON’10). 1207--1212.

[26]

N. Kapadia and S. Pasricha. 2012. A power delivery network aware framework for synthesis of 3d networks-on-chip with multiple voltage islands. In Proc. of Int. Conference on VLSI Design (VLSID’12). 262--267.

Digital Library

[27]

N. Kapadia and S. Pasricha. 2013. A co-synthesis methodology for power delivery and data interconnection networks in 3d ICs. In Proc. of Int. Symposium on Quality Electronic Design (ISQED’13). 73--79.

[28]

J. Kennedy and R. Eberhart. 1995. Particle swarm optimization. In Proc. of Int. Conference on Neural Networks. 1942--1948.

[29]

D. H. Kim, K. Athikulwongse, and S. K. Lim. 2009. A study of through-silicon-via impact on the 3D stacked IC layout. In Proc. of Int. Conference on Computer-Aided Design (ICCAD’09). 674--680.

Digital Library

[30]

S. Kundu, J. Soumya, and S. Chattopadhyay. 2012. Design and evaluation of mesh-of-tree based network-on-chip using virtual channel router. Microprocessors and Microsystems 36, 6 (2012), 471--488.

Digital Library

[31]

J. Lee and K. Choi. 2013. A deadlock-free routing algorithm requiring no virtual channel on 3d-NoCs with partial vertical connections. In Proc. of Int. Symposium on Networks on Chip (NoCS’13). 1--2.

[32]

C. Liu, L. Zhang, Y. Han, and X. Li. 2011. Vertical interconnects squeezing in symmetric 3d mesh network-on-chip. In Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC’11). 357--362.

Digital Library

[33]

P. Magarshack and P. G. Paulin. 2003. System-on-chip beyond the nanometer wall. In Proc. of 40th Design Automation Conf. (DAC’03). 419--424.

Digital Library

[34]

K. Manna, S. Chattopadhyay, and I. Sengupta. 2014. Through silicon via placement and mapping strategy for 3d mesh based network-on-chip. In Proc. of the IFIP/IEEE Intelligent Conference on Very Large Scale Integration (VLSI-SoC’14). 1--6.

[35]

K. Manna, V. S. Teja, S. Chattopadhyay, and I. Sengupta. 2015. TSV placement and mapping strategy for 3d mesh based network-on-chip using extended Kernighan-Lin partitioning technique. In Proc. of the IEEE Intl. Symposium on VLSI (ISVLSI’15). 392--397.

[36]

F. Miller, T. Wild, and A. Herkersdorf. 2012. TSV-virtualization for multi-protocol-interconnect in 3d-ICs. In Proc. of Euromicro Conference on Digital System Design (DSD’12). 374--381.

Digital Library

[37]

S. Murali and G. De Micheli. 2004. Bandwidth constrained mapping of cores onto NoC architectures. In Proc. of Design, Automation and Test in Europe (DATE’04). 896--901.

Digital Library

[38]

S. Murali, C. Seiculescu, L. Benini, and G. De Micheli. 2009. Synthesis of networks on chips for 3d systems on chips. In Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC’09). 242--247.

Digital Library

[39]

S. Pasricha. 2009. Exploring serial vertical interconnects for 3d ICs. In Proc. of Design Automation Conference (DAC’09). 581--586.

Digital Library

[40]

S. Pasricha. 2012. A framework for TSV serialization-aware synthesis of application specific 3d networks-on-chip. In Proc. of Int. Conference on VLSI Design (VLSID’12). 268--273.

Digital Library

[41]

V. F. Pavlidis and E. G. Friedman. 2007. 3-d topologies for networks-on-chip. IEEE Transactions on Very Large Scale Integration Systems 15 (2007), 1081--1090.

Digital Library

[42]

A.-M. Rahmani, K. R. Vaddina, K. Latif, P. Liljeberg, J. Plosila, and H. Tenhunen. 2012. Design and management of high-performance, reliable and thermal-aware 3d networks-on-chip. IET Circuits, Devices Systems 6, 5 (2012), 308--321.

[43]

A. B. Rhler and S. Chen. 2011. An analysis of sub-swarms in multi-swarm systems. In Proc. of Joint Austral. Conf. on Artificial Intelligence. 271--280.

Digital Library

[44]

P. K. Sahu and S. Chattopadyay. 2013. A survey on application mapping strategies for network-on-chip design. Journal of System Architecture 59, 1 (2013), 60--76.

Digital Library

[45]

P. K. Sahu, T. Shah, K. Manna, and S. Chattopadyay. 2014. Application mapping onto mesh based network-on-chip using discrete particle swarm optimization. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22, 2 (2014), 300--312.

Digital Library

[46]

M. Saito and M. Matsumoto. 2008. SIMD-Oriented Fast Mersenne Twister: A 128-Bit Pseudorandom Number Generator. Monte Carlo and Quasi-Monte Carlo Methods, A. Keller, S. Heinrich, and H. Niederreiter, Eds. Berlin, Germany: Springer-Verlag. pp. 607--622.

[47]

C. Seiculescu, S. Murali, L. Benini, and G. D. Micheli. 2009. SunFloor 3d: A tool for networks on chip topology synthesis for 3d systems on chips. In Proc. of Design Automation Test in Europe (DATE’09). 9--14.

Digital Library

[48]

C. Seiculescu, S. Murali, L. Benini, and G. D. Micheli. 2010. SunFloor 3d: A tool for networks on chip topology synthesis for 3-d systems on chips. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29, 12 (2010), 1987--2000.

Digital Library

[49]

Semiconductor Industry Association et al. 2007. The International Technology Roadmap for Semiconductors (ITRS).

[50]

K. Tatas, K. Siozios, D. Soudris, and A. Jantsch. 2014. Designing 2D and 3D Network-on-Chip Architectures. Springer, New York.

Digital Library

[51]

A. W. Topol, D. C. La Tulipe, Jr., L. Shi, D. J. Frank, K. Bernstein, S. E. Steen, A. Kumar, G. U. Singco, A. M. Young, K. W. Guarini, and M. Ieong. 2006. Three-dimensional integrated circuits. IBM Journal on Research and Development 50, 4/5 (2006), 491--506.

Digital Library

[52]

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar. 2008. An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS. IEEE Journal on Solid-State Circuits 43 (2008), 29--41.

[53]

G. V. Varatkar and R. Marculescu. 2004. On-chip traffic modelling and synthesis for MPEG-2 video applications. IEEE Transactions on Very Large Scale Integration (VLSI) System 12, 1 (2004), 108--119.

Digital Library

[54]

J. Wang, L. Li, H. Pan, S. He, and R. Zhang. 2011. Latency-aware mapping for 3d NoC using rank-based multi-objective genetic algorithm. In Proc. of Int. Conference on ASIC (ASICON’11). 413--416.

[55]

P. K. Wang, L. Huang, C. G. Zhou, and W. Pang. 2003. Particle swarm optimization for traveling salesman problem. In Proc. of Int. Conf. on Machine Learning and Cybernetics. 1583--1585.

[56]

T. C. Xu, P. Liljeberg, and H. Tenhunen. 2010. A study of through silicon via impact to 3d network-on-chip design. In Proc. of Int. Conf. on Electronics and Information Engineering (ICEIE’10). 333--337.

[57]

T. C. Xu, P. Liljeberg, and H. Tenhunen. 2011. Optimal number and placement of through silicon vias in 3D network-on-chip. In Proc. of Int. Symposium on Design and Diagnostics of Electronic Circuits 8 Systems (DDECS’11). 105 --110.

[58]

Y. Xu, Y. Du, B. Zhao, X. Zhou, Y. Zhang, and J. Yang. 2009. A low-radix and low-diameter 3d interconnection network design. In Proc. of Symposium on High Performance Computer Architecture (HPCA’09). 30--42.

[59]

Y. Xie, J. Cong, and S. Sapatnekar. 2009. Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures. Springer Publishing Company.

Digital Library

[60]

S. Yan and B. Lin. 2008. Design of application-specific 3d networks-on-chip architectures. In Proc. of Int. Conf. on Computer Design (ICCD’08). 142--149.

[61]

H. Ying, K. Heid, T. Hollstein, and K. Hofmann. 2012a. A genetic algorithm based optimization method for low vertical link density 3-dimensional networks-on-chip many core systems. In Proc. of NORCHIP. 1--4.

[62]

H. Ying, T. Hollstein, and K. Hofmann. 2012b. Communication-centric high level synthesis metrics for low vertical channel density 3-dimensional networks-on-chip. In Proc. of Int. Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC’12). 1--6.

[63]

W. Zhong, S. Chen, F. Ma, T. Yoshimura, and S. Goto. 2011. Floorplanning driven network-on-chip synthesis for 3-d socs. In Proc. of Int. Symposium on Circuits and Systems (ISCAS’11). 1203--1206.

[64]

P. Zhou, P.-H. Yuh, and S. Sapatnekar. 2012. Optimized 3d network-on-chip design using simulated allocation. ACM Transactions on Design Automation of Electronic Systems 17, 2, Article 12 (April 2012), 19 pages.

Digital Library

Cited By

Ramesh SManna KGogineni VChattopadhyay SMahapatra S(2024)Congestion-Aware Vertical Link Placement and Application Mapping Onto 3-D Network-on-Chip ArchitecturesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.337125543:8(2249-2262)Online publication date: 1-Aug-2024
https://dl.acm.org/doi/10.1109/TCAD.2024.3371255
Kaur SGhose MPathak APatole R(2024)A survey on mapping and scheduling techniques for 3D Network-on-chipJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2024.103064147:COnline publication date: 17-Apr-2024
https://dl.acm.org/doi/10.1016/j.sysarc.2024.103064
Do CKim CChung S(2023)Aggressive GPU cache bypassing with monolithic 3D-based NoCThe Journal of Supercomputing10.1007/s11227-022-04878-679:5(5421-5442)Online publication date: 1-Mar-2023
https://dl.acm.org/doi/10.1007/s11227-022-04878-6
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Index Terms

Integrated Through-Silicon Via Placement and Application Mapping for 3D Mesh-Based NoC Design
1. Computer systems organization
  1. Dependable and fault-tolerant systems and networks
    1. Redundancy
  2. Embedded and cyber-physical systems
    1. Embedded systems

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cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 16, Issue 1

Special Issue on VIPES, Special Issue on ICESS2015 and Regular Papers

February 2017

602 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/3008024

Editor:
Sandeep K. Shukla
Indian Institute of Technology, India

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Copyright © 2016 ACM.

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 03 November 2016

Accepted: 01 July 2016

Revised: 01 May 2016

Received: 01 August 2015

Published in TECS Volume 16, Issue 1

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Cited By

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https://dl.acm.org/doi/10.1109/TCAD.2024.3371255
Kaur SGhose MPathak APatole R(2024)A survey on mapping and scheduling techniques for 3D Network-on-chipJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2024.103064147:COnline publication date: 17-Apr-2024
https://dl.acm.org/doi/10.1016/j.sysarc.2024.103064
Do CKim CChung S(2023)Aggressive GPU cache bypassing with monolithic 3D-based NoCThe Journal of Supercomputing10.1007/s11227-022-04878-679:5(5421-5442)Online publication date: 1-Mar-2023
https://dl.acm.org/doi/10.1007/s11227-022-04878-6
Zheng YMeng DBai L(2022)PCB Network Analysis for Circuit PartitioningApplied Sciences10.3390/app1216820012:16(8200)Online publication date: 17-Aug-2022
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Zhi CDong GWang YZhu ZYang Y(2022)Trade-Off-Oriented Impedance Optimization of Chiplet-Based 2.5-D Integrated Circuits With a Hybrid MDP Algorithm for Noise EliminationIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2022.320041069:12(5247-5258)Online publication date: Dec-2022
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Bamberg LJoseph JGarcía-Ortiz APionteck TBamberg LJoseph JGarcía-Ortiz APionteck T(2022)Network Synthesis and SoC Floor Planning3D Interconnect Architectures for Heterogeneous Technologies10.1007/978-3-030-98229-4_15(323-361)Online publication date: 12-Mar-2022
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Gan YGuo HZhou Z(2021)3D NoC Low-Power Mapping Optimization Based on Improved Genetic AlgorithmMicromachines10.3390/mi1210121712:10(1217)Online publication date: 6-Oct-2021
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Fu YZhang CSong WChen QChen HZhou MLi L(2021)Optimizing Vertical Link Placement and Congestion Aware Dynamic Elevator Assignment for Partially Connected 3D-NoCsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.303833840:10(1957-1970)Online publication date: Oct-2021
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Joseph JErmel DBamberg LGarcía-Oritz APionteck T(2020)Application-Specific SoC Design Using Core Mapping to 3D Mesh NoCs with Nonlinear Area Optimization and Simulated AnnealingTechnologies10.3390/technologies80100108:1(10)Online publication date: 23-Jan-2020
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