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A performance-constrained template-based layout retargeting algorithm for analog integrated circuits

Authors:

Zheng Liu,

Lihong ZhangAuthors Info & Claims

ASPDAC '10: Proceedings of the 2010 Asia and South Pacific Design Automation Conference

Pages 293 - 298

Published: 18 January 2010 Publication History

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Abstract

Performance of analog integrated circuits is highly sensitive to layout parasitics. This paper presents an improved template-based algorithm that automatically conducts performance-constrained parasitic-aware retargeting and optimization of analog layouts. In order to achieve desired circuit performance, performance sensitivities with respect to layout parasitics are first determined. Then the algorithm applies a piecewise-sensitivity model to control parasitic-related layout geometries by directly constructing a set of performance constraints subject to maximum performance deviation due to parasitics. The formulated problem is finally solved using graph-based techniques combined with mixed-integer nonlinear programming. The proposed method has been incorporated into a parasitic-aware automatic layout optimization and retargeting tool. It has been demonstrated to be effective and efficient especially when adapting layout design for new technologies or updated specifications.

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Cited By

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Li YLin YMadhusudan MSharma AXu WSapatnekar SHarjani RHu JXie Y(2020)A customized graph neural network model for guiding analog IC placementProceedings of the 39th International Conference on Computer-Aided Design10.1145/3400302.3415624(1-9)Online publication date: 2-Nov-2020
https://dl.acm.org/doi/10.1145/3400302.3415624
Dong XZhang L(2018)PV-Aware Analog Sizing for Robust Analog Layout Retargeting with Optical Proximity CorrectionACM Transactions on Design Automation of Electronic Systems10.1145/323662423:6(1-19)Online publication date: 6-Nov-2018
https://dl.acm.org/doi/10.1145/3236624
Xu BBasaran BSu MPan DChu CBustany I(2018)Analog Placement Constraint Extraction and Exploration with the Application to Layout RetargetingProceedings of the 2018 International Symposium on Physical Design10.1145/3177540.3178245(98-105)Online publication date: 25-Mar-2018
https://dl.acm.org/doi/10.1145/3177540.3178245
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Published In

ASPDAC '10: Proceedings of the 2010 Asia and South Pacific Design Automation Conference

January 2010

920 pages

ISBN:9781605588377

General Chair:
Youn-Long Lin
National Tsing Hua University

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IEEE Press

Publication History

Published: 18 January 2010

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ASPDAC '10

Sponsor:

TICD
SIGDA

ASPDAC '10: Asia and South Pacific Design Automation Conference

January 18 - 21, 2010

Taipei, Taiwan

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Li YLin YMadhusudan MSharma AXu WSapatnekar SHarjani RHu JXie Y(2020)A customized graph neural network model for guiding analog IC placementProceedings of the 39th International Conference on Computer-Aided Design10.1145/3400302.3415624(1-9)Online publication date: 2-Nov-2020
https://dl.acm.org/doi/10.1145/3400302.3415624
Dong XZhang L(2018)PV-Aware Analog Sizing for Robust Analog Layout Retargeting with Optical Proximity CorrectionACM Transactions on Design Automation of Electronic Systems10.1145/323662423:6(1-19)Online publication date: 6-Nov-2018
https://dl.acm.org/doi/10.1145/3236624
Xu BBasaran BSu MPan DChu CBustany I(2018)Analog Placement Constraint Extraction and Exploration with the Application to Layout RetargetingProceedings of the 2018 International Symposium on Physical Design10.1145/3177540.3178245(98-105)Online publication date: 25-Mar-2018
https://dl.acm.org/doi/10.1145/3177540.3178245
Dong XZhang L(2018)Analog Layout Retargeting With Process-Variation-Aware Hybrid OPCIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.277348126:3(594-598)Online publication date: 1-Mar-2018
https://dl.acm.org/doi/10.1109/TVLSI.2017.2773481
Martins RLourenço NHorta NMoore J(2012)LAYGEN IIProceedings of the 14th annual conference on Genetic and evolutionary computation10.1145/2330163.2330319(1127-1134)Online publication date: 7-Jul-2012
https://dl.acm.org/doi/10.1145/2330163.2330319

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Directly performance-constrained template-based layout retargeting and optimization for analog integrated circuits

Performance-constrained template-driven retargeting for analog and RF layouts

A layout verification system for analog bipolar integrated circuits

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